Patent Application
20240250070
The present invention generally relates to fabrication methods and resulting structures for stacked semiconductor devices, and more specifically, to facilitator dies for heterogeneous die stacks.
In microelectronics a stacked semiconductor device, also referred to as a three-dimensional integrated circuit (3D IC), refers to an integrated circuit manufactured by stacking silicon wafers, chips, and/or dies and interconnecting them vertically so that they behave as a single, vertically integrated device to achieve performance improvements at reduced power and at smaller footprint than conventional two-dimensional (2D) processes. During the stacking process, often referred to as through silicon stacking (TSS), any number of chips and/or dies can be stacked to form the 3D IC. In such devices, through silicon vias (TSVs) serve as interconnects between the circuit layers.
Each circuit layer within the 3D IC architecture can be built with different processes, or even on different types of wafers. Notably, this flexibility means that components can be optimized to a much greater degree than if they were built together on a single wafer. Moreover, components with incompatible manufacturing requirements can be built separately and later combined in a single 3D IC.
Embodiments of the invention are directed to a method for providing a three-dimensional integrated circuit (3D IC) having facilitator dies in a hierarchical configuration. A non-limiting example of the method includes forming a plurality of stacked dies. The plurality of stacked dies includes a bottom die having a first die type, a plurality of upper dies having a second die type different than the first die type, and a facilitator die having a third die type different than the first die type and the second die type. At least one of a signal connection and a power distribution line are formed hierarchically between the bottom die, the plurality of upper dies, and the facilitator die. Connections between the bottom die and the facilitator die define a first hierarchical level and connections between the facilitator die and one or more of the plurality of upper dies define a second hierarchical level.
Embodiments of the invention are directed to a semiconductor structure. A non-limiting example of the semiconductor structure includes a plurality of stacked dies. The plurality of stacked dies includes a bottom die having a first die type, a plurality of upper dies having a second die type different than the first die type, and a facilitator die having a third die type different than the first die type and the second die type. At least one of a signal connection and a power distribution line are positioned hierarchically between the bottom die, the plurality of upper dies, and the facilitator die. Connections between the bottom die and the facilitator die define a first hierarchical level and connections between the facilitator die and one or more of the plurality of upper dies define a second hierarchical level.
Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings.
The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified.
In the accompanying figures and following detailed description of the described embodiments of the invention, the various elements illustrated in the figures are provided with two or three-digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.
It is understood in advance that although example embodiments of the invention are described in connection with a particular three-dimensional integrated circuit (3D IC) architecture, embodiments of the invention are not limited to the particular architecture layout described in this specification. Rather, embodiments of the present invention are capable of being implemented in conjunction with any of a number of 3D IC layouts having any number of devices now known or later developed distributed across any number of circuit layers.
For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
Turning now to an overview of technologies that are more specifically relevant to aspects of the present invention, ICs are fabricated in a series of stages, including a front-end-of-line (FEOL) stage, a middle-of-line (MOL) stage, a back-end-of-line (BEOL) stage, and a far back end of line (FBEOL) stage. The process flows for fabricating modern ICs are often identified based on whether the process flows fall in the FEOL stage, the MOL stage, the BEOL stage, and/or the FBEOL stage. Generally, the FEOL stage is where device elements (e.g., transistors, capacitors, resistors, etc.) are patterned onto a semiconductor substrate/wafer. The FEOL stage processes include wafer preparation, isolation, gate patterning, and the formation of wells, source/drain (S/D) regions, extension junctions, silicide regions, and liners. The MOL stage typically includes process flows for forming the contacts (e.g., CA) and other structures that communicatively couple to active regions (e.g., gate, source, and drain) of the device element. For example, the silicidation of source/drain regions, as well as the deposition of metal contacts, can occur during the MOL stage to connect the elements patterned during the FEOL stage. Layers of interconnections (e.g., metallization layers) are formed above these logical and functional layers during the BEOL stage and off-chip wiring (e.g., under bump metals, redistribution layers, etc.) is incorporated during the FBEOL to complete the IC. Most ICs need more than one layer of wires to form all the necessary connections, and as many as 5-12 layers are added in the BEOL process. The various BEOL layers are interconnected by vias that couple from one layer to another. Insulating dielectric materials are used throughout the layers of an IC to perform a variety of functions, including stabilizing the IC structure and providing electrical isolation of the IC elements. For example, the metal interconnecting wires in the BEOL region of the IC are isolated by dielectric layers to prevent the wires from creating a short circuit with other metal layers.
Generally, current 3D IC designs rely on a single bottom die, commonly referred to as a type-1 die, and a plurality of homogeneous upper dies, commonly referred to as type-2 dies. The type-1 die is not homogenous with the type-2 dies. Signal connections and power distribution are fly-by. As used herein, a “fly-by” topology refers to an arrangement whereby a command signal, an address signal, and a clock signal are supplied through one wire to each of the memory devices of the 3D IC. Unfortunately, such 3D IC configurations are natively limited in total stack size (number of layers) by run (wire) lengths, latency and voltage drop considerations, as each die is serviced from a same wire connected back to the bottom (type-1) die. In other words, the connectivity burden for each fly-by wire increases directly with an increase in circuit layers (i.e., number of stacked dies).
Turning now to an overview of aspects of the present invention, one or more embodiments of the invention address the above-described shortcomings by providing fabrication methods and resulting structures that leverage one or more facilitator dies within a heterogeneous die stack in a 3D IC layout. As used herein, a “facilitator die” refers to a so-called type-3 die which can be incorporated along with the type-2 upper dies into a die stack, and which serves as a hierarchical contact layer for signal connections and/or power distribution between the type-1 die and the type-2 dies.
Advantageously, configuring a 3D IC in this manner allows for arbitrary stack heights largely decoupled from fly-by wire requirements. For example, 16 layer, 32, layer, 64 layer (or even 128 layer, 256 layer, etc.) stack heights can be hierarchically serviced by distributing one or more facilitator (type-3) dies throughout a stack. In some embodiments, the type-3 dies are heterogenous to the type-2 and/or type-3 dies. Notably, the facilitator dies can be flexibly located at any desired layer of the stack depending on the needs of a particular application. For example, a facilitator die can be located at the bottom of the stack (e.g., as the first non type-1 die), the top of the stack (e.g., as the topmost upper die), at common intervals (e.g., at ¼, ½, ¾, of the stack height), or at asymmetrical intervals (e.g., all at the top, or bottom, etc.) throughout the stack.
Turning now to a more detailed description of fabrication operations and resulting structures according to aspects of the invention,
In some embodiments, the bottom die 102 is made of a first die type (e.g., type-1), the plurality of upper dies 104 are each made of a second die type (e.g., type-2), and the one or more facilitator dies 106 are each made of a third die type (e.g., type-2). In some embodiments, the first die type, the second die type, and/or the third die type are heterogeneous with respect to one or both of the other die types.
As further shown in
In some embodiments, each of the one or more facilitator dies 106 includes a voltage converter 112. In some embodiments, the voltage converter 112 is an on-chip voltage converter. In some embodiments, the voltage converter 112 is a voltage regulator. In some embodiments, the voltage converter 112 is electrically coupled to the global power line 108 by way of a TSV 110 (using, e.g., a wire, interconnect line, etc., not separately indicated).
In some embodiments, each of the voltage converters 112 is also electrically coupled to a local power line 114 by way of another TSV 110. In some embodiments, the local power line 114 is a low voltage power line. As used herein, a “low” voltage power line refers to a voltage lower than a voltage of the global power line 108. For example, in some embodiments, the global power line 108 is a 12 volt (12V) line and the local power line 114 is a 1 volt (1V) line (or 2V, 5V, etc.). In some embodiments, the local power line 114 runs from the respective one of the facilitator dies 106 to one or more of the upper dies 104. The local power line 114 can electrically couple to each of the upper dies 104 by way of a TSV 110.
As further shown in
In some embodiments, each of the one or more facilitator dies 106 includes a serializer/de-serializer 118. In some embodiments, the serializer/de-serializer 118 is an on-chip serializer/de-serializer. In some embodiments, the serializer/de-serializer 118 is electrically coupled to the global signal line 116 by way of a TSV 110.
In some embodiments, each of the serializer/de-serializers 118 is also electrically coupled to a local signal bus 120 by way of one or more of the TSVs 110. In some embodiments, the local signal bus 120 is a parallel signal line. In some embodiments, the local signal bus 120 runs from the respective one of the facilitator dies 106 to one or more of the upper dies 104. The local signal bus 120 can electrically couple to each of the upper dies 104 by way of a TSV 110.
As further shown in
In some embodiments, each of the one or more facilitator dies 106 includes an electrostatic discharge (ESD) protection circuit 124. In some embodiments, the ESD protection circuit 124 is an on-chip ESD protection circuit. In some embodiments, the ESD protection circuit 124 is electrically coupled to the common signal line 122 by way of a TSV 110. In some embodiments, each of the ESD protection circuits 124 are further electrically coupled to one or more downstream fly-by-signal lines (not separately shown).
As shown in
As further shown in
In some embodiments, the facilitator die 106 can include a local memory 208. In some embodiments, the local memory 208 is an SRAM. In some embodiments, the local memory 208 is configured to receive data 210 (e.g., a request/data signal) from the bottom die 102 and to store the data 210.
In some embodiments, the facilitator die 106 can include a memory controller 212. In some embodiments, the memory controller 212 is configured to receive data 214 (e.g., a request/data signal) from the bottom die 102, to process the data 214, and to transmit memory data 216 to an upper die(s) 104.
The additional functional blocks shown in
In some embodiments, the one or more die groups 402 can be stacked together to define an intermediate die stack 504. Stacking the die groups 402 can be referred to as a second stacking step. As further shown in
In some embodiments, the intermediate die stack 504 can be stacked together with one or more other intermediate die stacks 504 to define a final die stack 506. Stacking the intermediate die stacks 504 can be referred to as a third stacking step.
As shown at block 602, a plurality of stacked dies are formed. In some embodiments, the plurality of stacked dies include a bottom die having a first die type, a plurality of upper dies having a second die type different than the first die type, and a facilitator die having a third die type different than the first die type and the second die type.
At block 604, at least one of a signal connection and a power distribution line are positioned hierarchically between the bottom die, the plurality of upper dies, and the facilitator die. In some embodiments, connections between the bottom die and the facilitator die define a first hierarchical level. In some embodiments, connections between the facilitator die and one or more of the plurality of upper dies define a second hierarchical level. In some embodiments, the first hierarchical level and the second hierarchical level define a redrive configuration. In some embodiments, the first hierarchical level and the second hierarchical level define an N-level tree configuration (e.g., 2-level tree, 3-level tree, 8-level tree, etc.). In some embodiments, the first hierarchical level and the second hierarchical level define a both-end drive configuration.
The method can further include forming a global power line having a first voltage (e.g., 12V). In some embodiments, the global power line is coupled to the bottom die and the facilitator die in the first hierarchical level. In some embodiments, a local power line having a second voltage (e.g., 1V) less than the first voltage is coupled to the facilitator die and one or more of the plurality of upper dies in the second hierarchical level. In some embodiments, a voltage converter is formed on the facilitator die. In some embodiments, the voltage converter is coupled to the global power line and the local power line.
The method can include forming a global signal line coupled to the bottom die and the facilitator die in the first hierarchical level. In some embodiments, a local signal bus is coupled to the facilitator die and one or more of the plurality of upper dies in the second hierarchical level. In some embodiments, a serializer is formed on the facilitator die. In some embodiments, the serializer is coupled to the global signal line and the local signal bus.
The method can include forming a common signal line (e.g., a fly-by-signal). In some embodiments, the common signal line is coupled to the bottom die and the facilitator die in the first hierarchical level. In some embodiments, an ESD protection circuit is formed on the facilitator die. In some embodiments, the ESD protection circuit is coupled to the common signal line.
The method can include forming a near memory processor on the facilitator die. In some embodiments, the near memory processor is configured to receive an execution code from the bottom die, process the execution code, and transmit memory data to an upper die of the plurality of upper dies.
The method can include forming a local memory on the facilitator die. In some embodiments, the local memory is configured to receive request and data signals from the bottom die.
The method can include forming a memory controller on the facilitator die. In some embodiments, the memory controller is configured to receive data from the bottom die, process the data, and transmit memory data to an upper die of the plurality of upper dies.
The methods and resulting structures described herein can be used in the fabrication of IC chips. The resulting IC chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes IC chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. Although various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings, persons skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functionality is maintained even though the orientation is changed. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Similarly, the term “coupled” and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include an indirect “connection” and a direct “connection.”
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,” “upper,” and the like, are used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.
The terms “about,” “substantially,” “approximately,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.
As previously noted herein, for the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. By way of background, however, a more general description of the semiconductor device fabrication processes that can be utilized in implementing one or more embodiments of the present invention will now be provided. Although specific fabrication operations used in implementing one or more embodiments of the present invention can be individually known, the described combination of operations and/or resulting structures of the present invention are unique. Thus, the unique combination of the operations described in connection with the fabrication of a semiconductor device according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.
In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), chemical-mechanical planarization (CMP), and the like. Reactive ion etching (RIE), for example, is a type of dry etching that uses chemically reactive plasma to remove a material, such as a masked pattern of semiconductor material, by exposing the material to a bombardment of ions that dislodge portions of the material from the exposed surface. The plasma is typically generated under low pressure (vacuum) by an electromagnetic field. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators and selectively doped regions are built up to form the final device.
The flowchart and block diagrams in the Figures illustrate possible implementations of fabrication and/or operation methods according to various embodiments of the present invention. Various functions/operations of the method are represented in the flow diagram by blocks. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the Figures. For example, two blocks shown in succession can, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.
