Kaushik Kumar

Person

Clifton Park, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for bottom-up deposition of a film in a recessed feature
- Patent number 10,079,151
- Issue date Sep 18, 2018
- Tokyo Electron Limited
- Kandabara N Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for using post-processing methods for accelerating EUV litho...
- Patent number 9,653,319
- Issue date May 16, 2017
- Tokyo Electron Limited
- Anton J. deVilliers
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Etch process for reducing directed self assembly pattern defectivit...
- Patent number 9,153,457
- Issue date Oct 6, 2015
- Tokyo Electron Limited
- Vidhya Chakrapani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch process for reducing directed self assembly pattern defectivity
- Patent number 8,945,408
- Issue date Feb 3, 2015
- Tokyo Electron Limited
- Vidhya Chakrapani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of SiOCl-containing layer on spacer sidewalls to prevent...
- Patent number 8,809,194
- Issue date Aug 19, 2014
- Tokyo Electron Limited
- Alok Ranjan
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Dry metal etching method
- Patent number 8,808,562
- Issue date Aug 19, 2014
- Tokyo Electron Limited
- Yusuke Ohsawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Combined silicon oxide etch and contamination removal process
- Patent number 8,664,012
- Issue date Mar 4, 2014
- Tokyo Electron Limited
- Richard H. Gaylord
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of SiOCl-containing layer on exposed low-k surfaces to re...
- Patent number 8,592,327
- Issue date Nov 26, 2013
- Tokyo Electron Limited
- Alok Ranjan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sidewall and chamfer protection during hard mask removal for interc...
- Patent number 8,551,877
- Issue date Oct 8, 2013
- Tokyo Electron Limited
- Alok Ranjan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On-chip cooling for integrated circuits
- Patent number 8,492,295
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Kaushik A. Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned patterned etch stop layers for semiconductor devices
- Patent number 8,367,544
- Issue date Feb 5, 2013
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On-chip cooling systems for integrated circuits
- Patent number 8,298,966
- Issue date Oct 30, 2012
- International Business Machines Corporation
- Kaushik A. Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of patterning insulating layers using etching techniques th...
- Patent number 8,058,176
- Issue date Nov 15, 2011
- Samsung Electronics Co., Ltd.
- Wan-jae Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Liner protection in deep trench etching
- Patent number 8,030,157
- Issue date Oct 4, 2011
- International Business Machines Corporation
- Habib Hichri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal gradient control of high aspect ratio etching and depositio...
- Patent number 8,008,209
- Issue date Aug 30, 2011
- International Business Machines Corporation
- Michael R. Sievers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contact
- Patent number 7,888,252
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Johnathan E. Faltermeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polycarbosilane buried etch stops in interconnect structures
- Patent number 7,879,717
- Issue date Feb 1, 2011
- International Business Machines Corporation
- Elbert E. Huang
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Metal interconnect and IC chip including metal interconnect
- Patent number 7,851,919
- Issue date Dec 14, 2010
- International Business Machines Corporation
- Karl W. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming conductive structures
- Patent number 7,833,893
- Issue date Nov 16, 2010
- International Business Machines Corporation
- Stephan Grunow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structures and methods for reduction of parasitic capacitances in s...
- Patent number 7,825,019
- Issue date Nov 2, 2010
- International Business Machines Corporation
- Lawrence A. Clevenger
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Dual damascene integration of ultra low dielectric constant porous...
- Patent number 7,737,561
- Issue date Jun 15, 2010
- International Business Machines Corporation
- Kaushik A Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor structure
- Patent number 7,732,288
- Issue date Jun 8, 2010
- International Business Machines Corporation
- Huilong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal interconnect forming methods and IC chip including metal inte...
- Patent number 7,718,525
- Issue date May 18, 2010
- International Business Machines Corporation
- Karl W. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sidewall semiconductor transistors
- Patent number 7,696,025
- Issue date Apr 13, 2010
- International Business Machines Corporation
- Huilong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistors (FETS) with inverted source/drain metallic...
- Patent number 7,659,160
- Issue date Feb 9, 2010
- International Business Machines Corporation
- Michael P. Belyansky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On-chip cooling systems for integrated circuits
- Patent number 7,659,616
- Issue date Feb 9, 2010
- International Business Machines Corporation
- Kaushik A. Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistors (FETS) with inverted source/drain metallic...
- Patent number 7,648,871
- Issue date Jan 19, 2010
- International Business Machines Corporation
- Michael P. Belyansky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for hybrid tungsten copper metal contact
- Patent number 7,629,264
- Issue date Dec 8, 2009
- International Business Machines Corporation
- Griselda Bonilla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress relaxation, selective nitride phase removal
- Patent number 7,541,277
- Issue date Jun 2, 2009
- International Business Machines Corporation
- Kevin Shawn Petrarca
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Back end interconnect with a shaped interface
- Patent number 7,494,915
- Issue date Feb 24, 2009
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR BOTTOM-UP DEPOSITION OF A FILM IN A RECESSED FEATURE
- Publication number 20170092508
- Publication date Mar 30, 2017
- TOKYO ELECTRON LIMITED
- Kandabara N. Tapily
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Using Post-Processing Methods for Accelerating EUV Litho...
- Publication number 20150132965
- Publication date May 14, 2015
- TOKYO ELECTRON LIMITED
- Anton J. deVilliers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH PROCESS FOR REDUCING DIRECTED SELF ASSEMBLY PATTERN DEFECTIVITY
- Publication number 20140370717
- Publication date Dec 18, 2014
- TOKYO ELECTRON LIMITED
- VIDHYA CHAKRAPANI
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
ETCH PROCESS FOR REDUCING DIRECTED SELF ASSEMBLY PATTERN DEFECTIVIT...
- Publication number 20140370718
- Publication date Dec 18, 2014
- TOKYO ELECTRON LIMITED
- VIDHYA CHAKRAPANI
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
SIDEWALL AND CHAMFER PROTECTION DURING HARD MASK REMOVAL FOR INTERC...
- Publication number 20130236989
- Publication date Sep 12, 2013
- TOKYO ELECTRON LIMITED
- Alok RANJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF SiOCl-CONTAINING LAYER ON EXPOSED LOW-K SURFACES TO RE...
- Publication number 20130237060
- Publication date Sep 12, 2013
- TOKYO ELECTRON LIMITED
- Alok RANJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF SiOCl-CONTAINING LAYER ON SPACER SIDEWALLS TO PREVENT...
- Publication number 20130237059
- Publication date Sep 12, 2013
- TOKYO ELECTRON LIMITED
- Alok RANJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMBINED SILICON OXIDE ETCH AND CONTAMINATION REMOVAL PROCESS
- Publication number 20130084654
- Publication date Apr 4, 2013
- TOKYO ELECTRON LIMITED
- Richard H. Gaylord
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRY METAL ETCHING METHOD
- Publication number 20130065398
- Publication date Mar 14, 2013
- TOKYO ELECTRON LIMITED
- Yusuke OHSAWA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON-CHIP COOLING FOR INTEGRATED CIRCUITS
- Publication number 20130012018
- Publication date Jan 10, 2013
- International Business Machines Corporation
- Kaushik A. Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ultra-low-k dual damascene structure and method of fabricating
- Publication number 20120064713
- Publication date Mar 15, 2012
- TOKYO ELECTRON LIMITED
- Noel RUSSELL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES
- Publication number 20110092069
- Publication date Apr 21, 2011
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACT
- Publication number 20100210098
- Publication date Aug 19, 2010
- International Business Machines Corporation
- Johnathan E. Faltermeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON-CHIP COOLING SYSTEMS FOR INTEGRATED CIRCUITS
- Publication number 20100136800
- Publication date Jun 3, 2010
- International Business Machines Corporation
- Kaushik A. Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL INTERCONNECT AND IC CHIP INCLUDING METAL INTERCONNECT
- Publication number 20100133694
- Publication date Jun 3, 2010
- Karl W. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DAMASCENE WIRING FABRICATION METHODS INCORPORATING DIELECTRIC CAP E...
- Publication number 20090283912
- Publication date Nov 19, 2009
- Hakeem B.S. AKINMADE-YUSUFF
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR HYBRID TUNGSTEN COPPER METAL CONTACT
- Publication number 20090256263
- Publication date Oct 15, 2009
- International Business Machines Corporation
- Griselda Bonilla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
- Publication number 20090142894
- Publication date Jun 4, 2009
- Huilong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT
- Publication number 20090117360
- Publication date May 7, 2009
- International Business Machines Corporation
- Lawrence A. Clevenger
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Thermal Gradient Control of High Aspect Ratio Etching and Depositio...
- Publication number 20090107956
- Publication date Apr 30, 2009
- International Business Machines Corporation
- Michael R. Sievers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON-CHIP COOLING SYSTEMS FOR INTEGRATED CIRCUITS
- Publication number 20090096056
- Publication date Apr 16, 2009
- International Business Machines Corporation
- Kaushik A. Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN S...
- Publication number 20090085210
- Publication date Apr 2, 2009
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MINIMIZING VIA SIDEWALL DAMAGES DURING DUAL DAMASCENE TRE...
- Publication number 20090087992
- Publication date Apr 2, 2009
- Chartered Semiconductor Manufacturing LTD.
- Ravi Prakash SRIVASTAVA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Patterning Insulating Layers Using Etching Techniques th...
- Publication number 20090081873
- Publication date Mar 26, 2009
- SAMSUNG ELECTRONICS CO., LTD.
- Wan-jae Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING CONDUCTIVE STRUCTURES
- Publication number 20090017616
- Publication date Jan 15, 2009
- Stephan Grunow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MANUFACTURING IC CHIP IN PORTIONS FOR LATER COMBINING, AND RELATED...
- Publication number 20090014868
- Publication date Jan 15, 2009
- International Business Machines Corporation
- Karl W. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL INTERCONNECT FORMING METHODS AND IC CHIP INCLUDING METAL INTE...
- Publication number 20090001592
- Publication date Jan 1, 2009
- International Business Machines Corporation
- Karl W. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIDEWALL SEMICONDUCTOR TRANSISTORS
- Publication number 20080286909
- Publication date Nov 20, 2008
- Huilong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLYCARBOSILANE BURIED ETCH STOPS IN INTERCONNECT STRUCTURES
- Publication number 20080254612
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Elbert E. Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR...
- Publication number 20080197495
- Publication date Aug 21, 2008
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS

Kaushik Kumar

Person

Patents Grantslast 30 patents

Method for bottom-up deposition of a film in a recessed feature

Method for using post-processing methods for accelerating EUV litho...

Etch process for reducing directed self assembly pattern defectivit...

Etch process for reducing directed self assembly pattern defectivity

Formation of SiOCl-containing layer on spacer sidewalls to prevent...

Dry metal etching method

Combined silicon oxide etch and contamination removal process

Formation of SiOCl-containing layer on exposed low-k surfaces to re...

Sidewall and chamfer protection during hard mask removal for interc...

On-chip cooling for integrated circuits

Self-aligned patterned etch stop layers for semiconductor devices

On-chip cooling systems for integrated circuits

Methods of patterning insulating layers using etching techniques th...

Liner protection in deep trench etching

Thermal gradient control of high aspect ratio etching and depositio...

Self-aligned contact

Polycarbosilane buried etch stops in interconnect structures

Metal interconnect and IC chip including metal interconnect

Method for forming conductive structures

Structures and methods for reduction of parasitic capacitances in s...

Dual damascene integration of ultra low dielectric constant porous...

Method for fabricating a semiconductor structure

Metal interconnect forming methods and IC chip including metal inte...

Sidewall semiconductor transistors

Field effect transistors (FETS) with inverted source/drain metallic...

On-chip cooling systems for integrated circuits

Field effect transistors (FETS) with inverted source/drain metallic...

Structure and method for hybrid tungsten copper metal contact

Stress relaxation, selective nitride phase removal

Back end interconnect with a shaped interface

Patents Applicationslast 30 patents

METHOD FOR BOTTOM-UP DEPOSITION OF A FILM IN A RECESSED FEATURE

Method for Using Post-Processing Methods for Accelerating EUV Litho...

ETCH PROCESS FOR REDUCING DIRECTED SELF ASSEMBLY PATTERN DEFECTIVITY

ETCH PROCESS FOR REDUCING DIRECTED SELF ASSEMBLY PATTERN DEFECTIVIT...

SIDEWALL AND CHAMFER PROTECTION DURING HARD MASK REMOVAL FOR INTERC...

FORMATION OF SiOCl-CONTAINING LAYER ON EXPOSED LOW-K SURFACES TO RE...

FORMATION OF SiOCl-CONTAINING LAYER ON SPACER SIDEWALLS TO PREVENT...

COMBINED SILICON OXIDE ETCH AND CONTAMINATION REMOVAL PROCESS

DRY METAL ETCHING METHOD

ON-CHIP COOLING FOR INTEGRATED CIRCUITS

Ultra-low-k dual damascene structure and method of fabricating

SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES

SELF-ALIGNED CONTACT

ON-CHIP COOLING SYSTEMS FOR INTEGRATED CIRCUITS

METAL INTERCONNECT AND IC CHIP INCLUDING METAL INTERCONNECT

DAMASCENE WIRING FABRICATION METHODS INCORPORATING DIELECTRIC CAP E...

STRUCTURE AND METHOD FOR HYBRID TUNGSTEN COPPER METAL CONTACT

METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE

SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT

Thermal Gradient Control of High Aspect Ratio Etching and Depositio...

ON-CHIP COOLING SYSTEMS FOR INTEGRATED CIRCUITS

STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN S...

METHOD OF MINIMIZING VIA SIDEWALL DAMAGES DURING DUAL DAMASCENE TRE...

Methods of Patterning Insulating Layers Using Etching Techniques th...

METHOD FOR FORMING CONDUCTIVE STRUCTURES

MANUFACTURING IC CHIP IN PORTIONS FOR LATER COMBINING, AND RELATED...

METAL INTERCONNECT FORMING METHODS AND IC CHIP INCLUDING METAL INTE...

SIDEWALL SEMICONDUCTOR TRANSISTORS

POLYCARBOSILANE BURIED ETCH STOPS IN INTERCONNECT STRUCTURES

STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR...