Manuel M. Mejia

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable logic device architectures with super-regions having l...
- Patent number 6,879,183
- Issue date Apr 12, 2005
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with hierarchical interconnection resources
- Patent number 6,798,242
- Issue date Sep 28, 2004
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with hierarchical interconnection resources
- Patent number 6,577,160
- Issue date Jun 10, 2003
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device architectures with super-regions having l...
- Patent number 6,480,028
- Issue date Nov 12, 2002
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with hierarchical interconnection resources
- Patent number 6,417,694
- Issue date Jul 9, 2002
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual port programmable logic device variable depth and width memory...
- Patent number 6,392,954
- Issue date May 21, 2002
- Altera Corporation
- Srinivas T. Reddy
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device with redundant circuitry
- Patent number 6,344,755
- Issue date Feb 5, 2002
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuitry and methods for internal interconnection of programmable...
- Patent number 6,335,634
- Issue date Jan 1, 2002
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with hierarchical interconnection resources
- Patent number 6,300,794
- Issue date Oct 9, 2001
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device memory array circuit having combinable si...
- Patent number 6,288,970
- Issue date Sep 11, 2001
- Altera Corporation
- Srinivas T. Reddy
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device architecture with super-regions having lo...
- Patent number 6,215,326
- Issue date Apr 10, 2001
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with redundant circuitry
- Patent number 6,201,404
- Issue date Mar 13, 2001
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device memory array circuit having combinable si...
- Patent number 6,191,998
- Issue date Feb 20, 2001
- Altera Corporation
- Srinivas T. Reddy
- G11 - INFORMATION STORAGE
Information Patent Grant
Compact, low voltage, noise-immune RAM cell
- Patent number 6,172,900
- Issue date Jan 9, 2001
- Altera Corporation
- Manuel Mejia
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry and methods for internal interconnection of programmable...
- Patent number 6,107,824
- Issue date Aug 22, 2000
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device incorporating and input/output overflow bus
- Patent number 6,094,064
- Issue date Jul 25, 2000
- Altera Corporation
- Manuel Mejia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual-port programmable logic device variable depth and width memory...
- Patent number 6,052,327
- Issue date Apr 18, 2000
- Altera Corporation
- Srinivas T. Reddy
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for protecting a circuit during a hot socket c...
- Patent number 6,040,712
- Issue date Mar 21, 2000
- Altera Corporation
- Manuel Mejia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with hierarchical interconnection resources
- Patent number 5,977,793
- Issue date Nov 2, 1999
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hierarchical interconnect for programmable logic devices
- Patent number 5,883,526
- Issue date Mar 16, 1999
- Altera Corporation
- Srinivas Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic datastream compression/decompression
- Patent number 5,872,529
- Issue date Feb 16, 1999
- Altera Corporation
- Manuel M. Mejia
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20030201794
- Publication date Oct 30, 2003
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device architectures with super-regions having l...
- Publication number 20030080778
- Publication date May 1, 2003
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20030076130
- Publication date Apr 24, 2003
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device architectures with super-regions having l...
- Publication number 20020084801
- Publication date Jul 4, 2002
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20020041191
- Publication date Apr 11, 2002
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dual port programmable logic device variable depth and width memory...
- Publication number 20010015933
- Publication date Aug 23, 2001
- Altera Corporation
- Srinivas T. Reddy
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable logic device architectures
- Publication number 20010006348
- Publication date Jul 5, 2001
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY

Manuel M. Mejia

Person

Patents Grantslast 30 patents

Programmable logic device architectures with super-regions having l...

Programmable logic device with hierarchical interconnection resources

Programmable logic device with hierarchical interconnection resources

Programmable logic device architectures with super-regions having l...

Programmable logic device with hierarchical interconnection resources

Dual port programmable logic device variable depth and width memory...

Programmable logic device with redundant circuitry

Circuitry and methods for internal interconnection of programmable...

Programmable logic device with hierarchical interconnection resources

Programmable logic device memory array circuit having combinable si...

Programmable logic device architecture with super-regions having lo...

Programmable logic device with redundant circuitry

Programmable logic device memory array circuit having combinable si...

Compact, low voltage, noise-immune RAM cell

Circuitry and methods for internal interconnection of programmable...

Programmable logic device incorporating and input/output overflow bus

Dual-port programmable logic device variable depth and width memory...

Apparatus and method for protecting a circuit during a hot socket c...

Programmable logic device with hierarchical interconnection resources

Hierarchical interconnect for programmable logic devices

Dynamic datastream compression/decompression

Patents Applicationslast 30 patents

Programmable logic device with hierarchical interconnection resources

Programmable logic device architectures with super-regions having l...

Programmable logic device with hierarchical interconnection resources

Programmable logic device architectures with super-regions having l...

Programmable logic device with hierarchical interconnection resources

Dual port programmable logic device variable depth and width memory...

Programmable logic device architectures