Miron Abramovici

Person

Naperville, IL, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable interconnect for reconfigurable system-on-chip
- Patent number 7,650,545
- Issue date Jan 19, 2010
- Agere Systems Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Determining the value of internal signals in a malfunctioning integ...
- Patent number 7,493,434
- Issue date Feb 17, 2009
- Dafca, Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Methods for delay-fault testing in field-programmable gate arrays
- Patent number 7,412,343
- Issue date Aug 12, 2008
- University of North Carolina at Charlotte
- Charles Eugene Stroud
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serial implementation of assertion checking logic circuit
- Patent number 7,305,635
- Issue date Dec 4, 2007
- Dafca, Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Method to locate logic errors and defects in digital circuits
- Patent number 7,296,201
- Issue date Nov 13, 2007
- Dafca, Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Fixing functional errors in integrated circuits
- Patent number 7,146,548
- Issue date Dec 5, 2006
- Dafca, Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Assertion checking using two or more cores
- Patent number 7,137,086
- Issue date Nov 14, 2006
- Dafca, Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Reconfigurable fabric for SoCs using functional I/O leads
- Patent number 7,058,918
- Issue date Jun 6, 2006
- Dafca, Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Sequential test pattern generation using clock-control design for t...
- Patent number 7,017,096
- Issue date Mar 21, 2006
- Agere Systems Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Fault tolerant operation of field programmable gate arrays
- Patent number 6,973,608
- Issue date Dec 6, 2005
- Agere Systems Inc.
- Miron Abramovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying faulty programmable interconnect resources of field pro...
- Patent number 6,966,020
- Issue date Nov 15, 2005
- Agere Systems Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Fault tolerant operation of reconfigurable devices utilizing an adj...
- Patent number 6,874,108
- Issue date Mar 29, 2005
- Agere Systems Inc.
- Miron Abramovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential test pattern generation using combinational techniques
- Patent number 6,728,917
- Issue date Apr 27, 2004
- Agere Systems Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
On-line testing of field programmable gate array resources
- Patent number 6,631,487
- Issue date Oct 7, 2003
- Lattice Semiconductor Corp.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
On-line testing of the programmable interconnect network in field p...
- Patent number 6,574,761
- Issue date Jun 3, 2003
- Lattice Semiconductor Corp.
- Miron Abramovici
- G11 - INFORMATION STORAGE
Information Patent Grant
On-line testing of the programmable logic blocks in field programma...
- Patent number 6,550,030
- Issue date Apr 15, 2003
- Lattice Semiconductor Corp.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
On-line fault tolerant operation via incremental reconfiguration of...
- Patent number 6,530,049
- Issue date Mar 4, 2003
- Lattice Semiconductor Corporation
- Miron Abramovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual logic system for solving satisfiability problems using reco...
- Patent number 6,442,732
- Issue date Aug 27, 2002
- Lucent Technologies, Inc.
- Miron Abramovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel backtracing for satisfiability on reconfigurable hardware
- Patent number 6,292,916
- Issue date Sep 18, 2001
- Lucent Technologies Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Fault tolerant operation of field programmable gate arrays
- Patent number 6,256,758
- Issue date Jul 3, 2001
- Agere Systems Guardian Corp.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing field programmable gate arrays
- Patent number 6,202,182
- Issue date Mar 13, 2001
- Lucent Technologies Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Method of testing and diagnosing field programmable gate arrays
- Patent number 6,108,806
- Issue date Aug 22, 2000
- Lucent Technologies Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Virtual logic system for reconfigurable hardware
- Patent number 6,034,538
- Issue date Mar 7, 2000
- Lucent Technologies Inc.
- Miron Abramovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for testing field programmable gate arrays
- Patent number 6,003,150
- Issue date Dec 14, 1999
- Lucent Technologies Inc.
- Charles E. Stroud
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing field programmable gate arrays
- Patent number 5,991,907
- Issue date Nov 23, 1999
- Lucent Technologies Inc.
- Charles E. Stroud
- G01 - MEASURING TESTING
Information Patent Grant
Fault simulator for digital circuitry
- Patent number 5,896,401
- Issue date Apr 20, 1999
- Lucent Technologies Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Digital circuit test generator
- Patent number 5,831,996
- Issue date Nov 3, 1998
- Lucent Technologies Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Increasing testability by clock transformation
- Patent number 5,625,630
- Issue date Apr 29, 1997
- Lucent Technologies Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Testing a sequential circuit
- Patent number 5,590,135
- Issue date Dec 31, 1996
- Lucent Technologies Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Method for identifying untestable faults in logic circuits
- Patent number 5,566,187
- Issue date Oct 15, 1996
- Lucent Technologies Inc.
- Miron Abramovici
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
PROTECTING ELECTRONIC SYSTEMS FROM COUNTERFEITING AND REVERSE-ENGIN...
- Publication number 20110148457
- Publication date Jun 23, 2011
- Miron Abramovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS DISTRIBUTED PROGRAMMABLE LOGIC FOR MONITORING AND SECURI...
- Publication number 20110145934
- Publication date Jun 16, 2011
- Miron ABRAMOVICI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method to locate logic errors and defects in digital circuits
- Publication number 20070101216
- Publication date May 3, 2007
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit with autonomous power management
- Publication number 20060218424
- Publication date Sep 28, 2006
- Miron Abramovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Assertion checking
- Publication number 20060031807
- Publication date Feb 9, 2006
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Application
Methods for delay-fault testing in field-programmable gate arrays
- Publication number 20050154552
- Publication date Jul 14, 2005
- Charles Eugene Stroud
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reconfigurable fabric for SoCs
- Publication number 20040212393
- Publication date Oct 28, 2004
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Application
Sequential test pattern generation using clock-control design for t...
- Publication number 20030188245
- Publication date Oct 2, 2003
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Application
Sequential test pattern generation using combinational techniques
- Publication number 20020112209
- Publication date Aug 15, 2002
- Miron Abramovici
- G01 - MEASURING TESTING

Miron Abramovici

Person

Patents Grantslast 30 patents

Programmable interconnect for reconfigurable system-on-chip

Determining the value of internal signals in a malfunctioning integ...

Methods for delay-fault testing in field-programmable gate arrays

Serial implementation of assertion checking logic circuit

Method to locate logic errors and defects in digital circuits

Fixing functional errors in integrated circuits

Assertion checking using two or more cores

Reconfigurable fabric for SoCs using functional I/O leads

Sequential test pattern generation using clock-control design for t...

Fault tolerant operation of field programmable gate arrays

Identifying faulty programmable interconnect resources of field pro...

Fault tolerant operation of reconfigurable devices utilizing an adj...

Sequential test pattern generation using combinational techniques

On-line testing of field programmable gate array resources

On-line testing of the programmable interconnect network in field p...

On-line testing of the programmable logic blocks in field programma...

On-line fault tolerant operation via incremental reconfiguration of...

Virtual logic system for solving satisfiability problems using reco...

Parallel backtracing for satisfiability on reconfigurable hardware

Fault tolerant operation of field programmable gate arrays

Method and apparatus for testing field programmable gate arrays

Method of testing and diagnosing field programmable gate arrays

Virtual logic system for reconfigurable hardware

Method for testing field programmable gate arrays

Method for testing field programmable gate arrays

Fault simulator for digital circuitry

Digital circuit test generator

Increasing testability by clock transformation

Testing a sequential circuit

Method for identifying untestable faults in logic circuits

Patents Applicationslast 30 patents

PROTECTING ELECTRONIC SYSTEMS FROM COUNTERFEITING AND REVERSE-ENGIN...

AUTONOMOUS DISTRIBUTED PROGRAMMABLE LOGIC FOR MONITORING AND SECURI...

Method to locate logic errors and defects in digital circuits

Integrated circuit with autonomous power management

Assertion checking

Methods for delay-fault testing in field-programmable gate arrays

Reconfigurable fabric for SoCs

Sequential test pattern generation using clock-control design for t...

Sequential test pattern generation using combinational techniques