Nevine Nassif

Person

Arlington, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,899,615
- Issue date Feb 13, 2024
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,586,579
- Issue date Feb 21, 2023
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,294,852
- Issue date Apr 5, 2022
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functionally redundant semiconductor dies and package
- Patent number 11,127,712
- Issue date Sep 21, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 10,795,853
- Issue date Oct 6, 2020
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing verifier for MOS devices and related method
- Patent number 6,877,142
- Issue date Apr 5, 2005
- Hewlett-Packard Development Company, L.P.
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing timing verification of a circuit
- Patent number 6,658,506
- Issue date Dec 2, 2003
- Compaq Computer Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to compress a piecewise linear waveform so compression error...
- Patent number 6,654,713
- Issue date Nov 25, 2003
- Hewlett-Packard Development Company, L.P.
- Nicholas L. Rethman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for estimating elmore delays within circuit de...
- Patent number 6,606,587
- Issue date Aug 12, 2003
- Hewlett-Packard Development Company, L.P.
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing verifier for MOS devices and related method
- Patent number 6,473,888
- Issue date Oct 29, 2002
- Compaq Computer Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for modeling gate capacitance of symmetrically...
- Patent number 6,438,732
- Issue date Aug 20, 2002
- Compaq Computer Corporation
- James Arthur Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pruning of short paths in static timing verifier
- Patent number 6,046,984
- Issue date Apr 4, 2000
- Digital Equipment Corp.
- Joel Joseph Grodstein
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
QUASI-MONOLITHIC INTEGRATED PACKAGING ARCHITECTURE WITH MID-DIE SER...
- Publication number 20230197676
- Publication date Jun 22, 2023
- Intel Corporation
- Gerald S. Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINE-GRAINED DISAGGREGATED SERVER ARCHITECTURE
- Publication number 20230187407
- Publication date Jun 15, 2023
- Intel Corporation
- Carleton L. Molnar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20230169032
- Publication date Jun 1, 2023
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20220050805
- Publication date Feb 17, 2022
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONALLY REDUNDANT SEMICONDUCTOR DIES AND PACKAGE
- Publication number 20210375825
- Publication date Dec 2, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20200334196
- Publication date Oct 22, 2020
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONALLY REDUNDANT SEMICONDUCTOR DIES AND PACKAGE
- Publication number 20190206834
- Publication date Jul 4, 2019
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20180101502
- Publication date Apr 12, 2018
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing verifier for MOS devices and related method
- Publication number 20030149951
- Publication date Aug 7, 2003
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING

Nevine Nassif

Person

Patents Grantslast 30 patents

Multiple dies hardware processors and methods

Multiple dies hardware processors and methods

Multiple dies hardware processors and methods

Functionally redundant semiconductor dies and package

Multiple dies hardware processors and methods

Timing verifier for MOS devices and related method

Method and apparatus for performing timing verification of a circuit

Method to compress a piecewise linear waveform so compression error...

Method and apparatus for estimating elmore delays within circuit de...

Timing verifier for MOS devices and related method

Method and apparatus for modeling gate capacitance of symmetrically...

Pruning of short paths in static timing verifier

Patents Applicationslast 30 patents

QUASI-MONOLITHIC INTEGRATED PACKAGING ARCHITECTURE WITH MID-DIE SER...

FINE-GRAINED DISAGGREGATED SERVER ARCHITECTURE

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

FUNCTIONALLY REDUNDANT SEMICONDUCTOR DIES AND PACKAGE

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

FUNCTIONALLY REDUNDANT SEMICONDUCTOR DIES AND PACKAGE

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

Timing verifier for MOS devices and related method