Nivo Rovedo

Person

Lagrangeville, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Substantially L-shaped silicide for contact
- Patent number 8,643,119
- Issue date Feb 4, 2014
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for manufacturing asymmetric devices
- Patent number 8,482,075
- Issue date Jul 9, 2013
- International Business Machines Corporation
- Hasan M. Nayfeh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for manufacturing asymmetric devices
- Patent number 8,232,151
- Issue date Jul 31, 2012
- International Business Machines Corporation
- Hasan M. Nayfeh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for manufacturing asymmetric devices
- Patent number 8,034,692
- Issue date Oct 11, 2011
- International Business Machines Corporation
- Hasan M. Nayfeh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of creating asymmetric field-effect-transistors
- Patent number 8,017,483
- Issue date Sep 13, 2011
- International Business Machines Corporation
- Gregory G. Freeman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method to form multilayer embedded stressors
- Patent number 7,960,798
- Issue date Jun 14, 2011
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual stress memory technique method and related structure
- Patent number 7,785,950
- Issue date Aug 31, 2010
- International Business Machines Corporation
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method to form multilayer embedded stressors
- Patent number 7,618,866
- Issue date Nov 17, 2009
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
N-channel MOSFETs comprising dual stressors, and methods for formin...
- Patent number 7,473,608
- Issue date Jan 6, 2009
- International Business Machines Corporation
- Jinghong H. Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to engineer etch profiles in Si substrate for advanced semic...
- Patent number 7,442,618
- Issue date Oct 28, 2008
- Chartered Semiconductor Manufacturing, Ltd.
- Yung Fu Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming substantially L-shaped silicide contact for a sem...
- Patent number 7,442,619
- Issue date Oct 28, 2008
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
N-channel MOSFETs comprising dual stressors, and methods for formin...
- Patent number 7,279,758
- Issue date Oct 9, 2007
- International Business Machines Corporation
- Jinghong H. Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Salicide formation method
- Patent number 6,916,729
- Issue date Jul 12, 2005
- Infineon Technologies AG
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for low topography semiconductor device formation
- Patent number 6,797,569
- Issue date Sep 28, 2004
- International Business Machines Corporation
- David B. Colavito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for low topography semiconductor device formation
- Patent number 6,624,486
- Issue date Sep 23, 2003
- International Business Machines Corporation
- David B. Colavito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming junction on insulator (JOI) structure
- Patent number 6,544,874
- Issue date Apr 8, 2003
- International Business Machines Corporation
- Jack A. Mandelman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with junction isolation
- Patent number 6,525,340
- Issue date Feb 25, 2003
- International Business Machines Corporation
- David Colavito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterned buried insulator
- Patent number 6,429,091
- Issue date Aug 6, 2002
- International Business Machines Corporation
- Bomy A. Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned junction isolation
- Patent number 6,403,482
- Issue date Jun 11, 2002
- International Business Machines Corporation
- Nivo Rovedo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried strap for DRAM using junction isolation technique
- Patent number 6,391,703
- Issue date May 21, 2002
- International Business Machines Corporation
- Nivo Rovedo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Junction isolation
- Patent number 6,352,903
- Issue date Mar 5, 2002
- International Business Machines Corporation
- Nivo Rovedo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for detecting defective NVRAM cells
- Patent number 6,256,755
- Issue date Jul 3, 2001
- International Business Machines Corporation
- Terence B. Hook
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance/high density BICMOS process
- Patent number 6,071,767
- Issue date Jun 6, 2000
- International Business Machines Corporation
- Michael Monkowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packing density for flash memories
- Patent number 5,892,257
- Issue date Apr 6, 1999
- International Business Machines Corporation
- Joyce Elizabeth Acocella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making and programming a flash memory array
- Patent number 5,681,770
- Issue date Oct 28, 1997
- International Business Machines Corporation
- Seiki Ogura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making and programming a flash memory array
- Patent number 5,672,892
- Issue date Sep 30, 1997
- International Business Machines Corporation
- Seiki Ogura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making and programming a flash memory array
- Patent number 5,654,917
- Issue date Aug 5, 1997
- International Business Machines Corporation
- Seiki Ogura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making self-aligned stacked gate EEPROM with improved cou...
- Patent number 5,650,345
- Issue date Jul 22, 1997
- International Business Machines Corporation
- Seiki Ogura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packing density for flash memories by using a pad oxide
- Patent number 5,643,813
- Issue date Jul 1, 1997
- International Business Machines Corporation
- Joyce Elizabeth Acocella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packing density for flash memories
- Patent number 5,622,881
- Issue date Apr 22, 1997
- International Business Machines Corporation
- Joyce E. Acocella
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Structure and Method for Manufacturing Asymmetric Devices
- Publication number 20120217585
- Publication date Aug 30, 2012
- International Business Machines Corporation
- Hasan M. Nayfeh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES
- Publication number 20110254059
- Publication date Oct 20, 2011
- International Business Machines Corporation
- Hasan M. Nayfeh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES
- Publication number 20110089499
- Publication date Apr 21, 2011
- International Business Machines Corporation
- Hasan M. Nayfeh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF CREATING ASYMMETRIC FIELD-EFFECT-TRANSISTORS
- Publication number 20100330763
- Publication date Dec 30, 2010
- International Business Machines Corporation
- Gregory G. Freeman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS
- Publication number 20100059764
- Publication date Mar 11, 2010
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPACER UNDERCUT FILLER, METHOD OF MANUFACTURE THEREOF AND ARTICLES...
- Publication number 20090057755
- Publication date Mar 5, 2009
- International Business Machines Corporation
- Thomas W. Dyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD
- Publication number 20080283934
- Publication date Nov 20, 2008
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS
- Publication number 20080006818
- Publication date Jan 10, 2008
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING ISOLATION REGION WITH VARIABLE LI...
- Publication number 20070293016
- Publication date Dec 20, 2007
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMIN...
- Publication number 20070281413
- Publication date Dec 6, 2007
- International Business Machines Corporation
- Jinghong H. Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD
- Publication number 20070267753
- Publication date Nov 22, 2007
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor devices and methods of manufacture thereof
- Publication number 20070134861
- Publication date Jun 14, 2007
- Jin-Ping Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE
- Publication number 20070105299
- Publication date May 10, 2007
- International Business Machines Corporation
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to engineer etch profiles in Si substrate for advanced semic...
- Publication number 20070020861
- Publication date Jan 25, 2007
- Chartered Semiconductor MFG LTD and 2) IBM
- Yung Fu Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Salicide formation method
- Publication number 20040203229
- Publication date Oct 14, 2004
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR LOW TOPOGRAPHY SEMICONDUCTOR DEVICE FORMATION
- Publication number 20030170941
- Publication date Sep 11, 2003
- International Business Machines Corporation
- David B. Colavito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING JUNCTION ON INSULATOR (JOI) STRUCTURE
- Publication number 20030032272
- Publication date Feb 13, 2003
- International Business Machines Corporation
- Jack A. Mandelman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH JUNCTION ISOLATION
- Publication number 20020179905
- Publication date Dec 5, 2002
- David Colavito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for low topography semiconductor device formation
- Publication number 20020175369
- Publication date Nov 28, 2002
- International Business Machines Corporation
- David B. Colavito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Patterned buried insulator
- Publication number 20020072206
- Publication date Jun 13, 2002
- IBM
- Bomy A. Chen
- H01 - BASIC ELECTRIC ELEMENTS

Nivo Rovedo

Person

Patents Grantslast 30 patents

Substantially L-shaped silicide for contact

Structure and method for manufacturing asymmetric devices

Structure and method for manufacturing asymmetric devices

Structure and method for manufacturing asymmetric devices

Method of creating asymmetric field-effect-transistors

Structure and method to form multilayer embedded stressors

Dual stress memory technique method and related structure

Structure and method to form multilayer embedded stressors

N-channel MOSFETs comprising dual stressors, and methods for formin...

Method to engineer etch profiles in Si substrate for advanced semic...

Method of forming substantially L-shaped silicide contact for a sem...

N-channel MOSFETs comprising dual stressors, and methods for formin...

Salicide formation method

Method for low topography semiconductor device formation

Method for low topography semiconductor device formation

Method for forming junction on insulator (JOI) structure

Semiconductor device with junction isolation

Patterned buried insulator

Self-aligned junction isolation

Buried strap for DRAM using junction isolation technique

Junction isolation

Apparatus and method for detecting defective NVRAM cells

High performance/high density BICMOS process

Packing density for flash memories

Process for making and programming a flash memory array

Process for making and programming a flash memory array

Process for making and programming a flash memory array

Method of making self-aligned stacked gate EEPROM with improved cou...

Packing density for flash memories by using a pad oxide

Packing density for flash memories

Patents Applicationslast 30 patents

Structure and Method for Manufacturing Asymmetric Devices

STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES

STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES

METHOD OF CREATING ASYMMETRIC FIELD-EFFECT-TRANSISTORS

STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS

SPACER UNDERCUT FILLER, METHOD OF MANUFACTURE THEREOF AND ARTICLES...

SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD

STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS

SEMICONDUCTOR STRUCTURE INCLUDING ISOLATION REGION WITH VARIABLE LI...

N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMIN...

SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD

Semiconductor devices and methods of manufacture thereof

DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE

Method to engineer etch profiles in Si substrate for advanced semic...

Salicide formation method

METHOD FOR LOW TOPOGRAPHY SEMICONDUCTOR DEVICE FORMATION

METHOD FOR FORMING JUNCTION ON INSULATOR (JOI) STRUCTURE

SEMICONDUCTOR DEVICE WITH JUNCTION ISOLATION

Method for low topography semiconductor device formation

Patterned buried insulator