Oskar Kowarik

Person

Grafing, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Evaluation configuration for semiconductor memories
- Patent number 6,806,550
- Issue date Oct 19, 2004
- Infineon Technologies AG
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 6,768,667
- Issue date Jul 27, 2004
- Infineon Technologies AG
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for non-destructive, self-normalizing reading-out of MRAM m...
- Patent number 6,747,891
- Issue date Jun 8, 2004
- Infineon Technologies AG
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive ferroelectric memory cell
- Patent number 6,627,935
- Issue date Sep 30, 2003
- Siemens Aktiengesellschaft
- Oskar Kowarik
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor circuit configuration
- Patent number 6,480,044
- Issue date Nov 12, 2002
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory configuration including a plurality of resistive ferroelectr...
- Patent number 6,452,830
- Issue date Sep 17, 2002
- Infineon Technologies AG
- Oskar Kowarik
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reading nonvolatile semiconductor memory configurations
- Patent number 6,407,945
- Issue date Jun 18, 2002
- Infineon Technologies AG
- Andreas Graf von Schwerin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory configuration including a plurality of resistive ferroelectr...
- Patent number 6,404,668
- Issue date Jun 11, 2002
- Infineon Technologies AG
- Oskar Kowarik
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for generating a reference voltage for readin...
- Patent number 6,392,918
- Issue date May 21, 2002
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for nondestructively reading memory cells of an MRAM memory
- Patent number 6,388,917
- Issue date May 14, 2002
- Infineon Technologies AG
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration for self-referencing ferroelectric memory cells
- Patent number 6,317,356
- Issue date Nov 13, 2001
- Infineon Technologies AG
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor memory
- Patent number RE36061
- Issue date Jan 26, 1999
- Siemens Aktiengesellschaft
- Kurt Hoffmann
- 365 - Static information storage and retrieval
Information Patent Grant
Integrated buffer circuit which functions independently of fluctuat...
- Patent number 5,774,014
- Issue date Jun 30, 1998
- Siemens Aktiengesellschaft
- Johannes Stecker
- G05 - CONTROLLING REGULATING
Information Patent Grant
Integrated semiconductor circuit
- Patent number 5,276,643
- Issue date Jan 4, 1994
- Siemens Aktiengesellschaft
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor memory
- Patent number 5,253,209
- Issue date Oct 12, 1993
- Siemens Aktiengesellschaft
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor memory of the dram type and method for tes...
- Patent number 5,184,326
- Issue date Feb 2, 1993
- Siemens Aktiengesellschaft
- Kurt Hoffmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate circuit having MOS transistors
- Patent number 5,030,861
- Issue date Jul 9, 1991
- Siemens Aktiengesellschaft
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration and a method of testing storage cells
- Patent number 4,956,819
- Issue date Sep 11, 1990
- Siemens Aktiengesellschaft
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Testable redundancy decoder of an integrated semiconductor memory
- Patent number 4,922,134
- Issue date May 1, 1990
- Siemens Aktiengesellschaft
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-stage integrated decoder device
- Patent number 4,906,994
- Issue date Mar 6, 1990
- Siemens Aktiengelsellschaft
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration and a method for the testing of storage cells
- Patent number 4,896,322
- Issue date Jan 23, 1990
- Siemens Atkiengesellschaft
- Rainer Kraus
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit configuration of the parallel input of data into...
- Patent number 4,885,748
- Issue date Dec 5, 1989
- Siemens Aktiengesellschaft
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-stage, integrated decoder device having redundancy test enable
- Patent number 4,855,621
- Issue date Aug 8, 1989
- Siemens Aktiengesellschaft
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital amplifier configuration in integrated circuits
- Patent number 4,803,386
- Issue date Feb 7, 1989
- Siemens Aktiengesellschaft
- Rainer Kraus
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Circuit for non-destructive, self-normalizing reading-out of MRAM m...
- Publication number 20040017712
- Publication date Jan 29, 2004
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device
- Publication number 20030058710
- Publication date Mar 27, 2003
- Kurt Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Evaluation configuration for semiconductor memories
- Publication number 20030052344
- Publication date Mar 20, 2003
- Kurt Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory configuration including a plurality of resistive ferroelectr...
- Publication number 20020018356
- Publication date Feb 14, 2002
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR NONDESTRUCTIVELY READING MEMORY CELLS OF AN MRAM MEMORY
- Publication number 20020018361
- Publication date Feb 14, 2002
- Kurt Hoffmann
- G11 - INFORMATION STORAGE
Information Patent Application
Method for reading nonvolatile semiconductor memory configurations
- Publication number 20020018366
- Publication date Feb 14, 2002
- Andreas Graf von Schwerin
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive ferroelectric memory cell
- Publication number 20010038109
- Publication date Nov 8, 2001
- Oskar Kowarik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuit configuration for generating a reference voltage for readin...
- Publication number 20010038557
- Publication date Nov 8, 2001
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Application
Memory configuration including a plurality of resistive ferroelectr...
- Publication number 20010033516
- Publication date Oct 25, 2001
- Oskar Kowarik
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor circuit configuration
- Publication number 20010028090
- Publication date Oct 11, 2001
- Georg Braun
- G11 - INFORMATION STORAGE

Oskar Kowarik

Person

Patents Grantslast 30 patents

Evaluation configuration for semiconductor memories

Semiconductor memory device

Circuit for non-destructive, self-normalizing reading-out of MRAM m...

Resistive ferroelectric memory cell

Semiconductor circuit configuration

Memory configuration including a plurality of resistive ferroelectr...

Method for reading nonvolatile semiconductor memory configurations

Memory configuration including a plurality of resistive ferroelectr...

Circuit configuration for generating a reference voltage for readin...

Method for nondestructively reading memory cells of an MRAM memory

Configuration for self-referencing ferroelectric memory cells

Integrated semiconductor memory

Integrated buffer circuit which functions independently of fluctuat...

Integrated semiconductor circuit

Integrated semiconductor memory

Integrated semiconductor memory of the dram type and method for tes...

Gate circuit having MOS transistors

Circuit configuration and a method of testing storage cells

Testable redundancy decoder of an integrated semiconductor memory

Multi-stage integrated decoder device

Circuit configuration and a method for the testing of storage cells

Method and circuit configuration of the parallel input of data into...

Multi-stage, integrated decoder device having redundancy test enable

Digital amplifier configuration in integrated circuits

Patents Applicationslast 30 patents

Circuit for non-destructive, self-normalizing reading-out of MRAM m...

Semiconductor memory device

Evaluation configuration for semiconductor memories

Memory configuration including a plurality of resistive ferroelectr...

METHOD FOR NONDESTRUCTIVELY READING MEMORY CELLS OF AN MRAM MEMORY

Method for reading nonvolatile semiconductor memory configurations

Resistive ferroelectric memory cell

Circuit configuration for generating a reference voltage for readin...

Memory configuration including a plurality of resistive ferroelectr...

Semiconductor circuit configuration