Patrick Chuang

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Orthogonal data transposition system and method during data transfe...
- Patent number 11,409,528
- Issue date Aug 9, 2022
- GSI Technology, Inc.
- Bob Haig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Results processing circuits and methods associated with computation...
- Patent number 11,194,519
- Issue date Dec 7, 2021
- GSI Technology, Inc.
- Bob Haig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ultra low VDD memory cell with ratioless write port
- Patent number 10,943,648
- Issue date Mar 9, 2021
- GSI Technology, Inc.
- Lee-Lean Shu
- G11 - INFORMATION STORAGE
Information Patent Grant
Results processing circuits and methods associated with computation...
- Patent number 10,891,076
- Issue date Jan 12, 2021
- GSI Technology, Inc.
- Bob Haig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Orthogonal data transposition system and method during data transfe...
- Patent number 10,860,320
- Issue date Dec 8, 2020
- GSI Technology, Inc.
- Bob Haig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computational memory cell and processing array device with ratioles...
- Patent number 10,854,284
- Issue date Dec 1, 2020
- GSI Technology, Inc.
- Patrick Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Read and write data processing circuits and methods associated with...
- Patent number 10,770,133
- Issue date Sep 8, 2020
- Bob Haig
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods involving multi-bank, dual-pipe memory circuitry
- Patent number 10,720,205
- Issue date Jul 21, 2020
- GSI Technology, Inc.
- Mu-Hsiang Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods involving lock loop circuits, distributed duty...
- Patent number 10,659,058
- Issue date May 19, 2020
- GSI Technology, Inc.
- Yu-Chi Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods involving lock-loop circuits, clock signal alig...
- Patent number 10,425,070
- Issue date Sep 24, 2019
- GSI Technology, Inc.
- Yu-Chi Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods involving pseudo complementary output buffer ci...
- Patent number 9,935,635
- Issue date Apr 3, 2018
- GSI Technology, Inc.
- Jae-Hyeong Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods involving lock-loop circuits, clock signal alig...
- Patent number 9,853,633
- Issue date Dec 26, 2017
- GSI Technology, Inc.
- Yu-Chi Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
- Patent number 9,679,631
- Issue date Jun 13, 2017
- GSI Technology, Inc.
- Robert Haig
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory systems and methods involving high speed local address circu...
- Patent number 9,613,670
- Issue date Apr 4, 2017
- GSI Technology, Inc.
- Patrick Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods involving data inversion devices, circuitry, sc...
- Patent number 9,494,647
- Issue date Nov 15, 2016
- GSI Technology, Inc.
- Patrick T. Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory systems and methods involving high speed local address circu...
- Patent number 9,318,174
- Issue date Apr 19, 2016
- GSI Technology, Inc.
- Patrick Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
- Patent number 9,196,324
- Issue date Nov 24, 2015
- GSI Technology, Inc.
- Robert Haig
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
- Patent number 8,982,649
- Issue date Mar 17, 2015
- GSI Technology, Inc.
- Robert Haig
- G11 - INFORMATION STORAGE
Information Patent Grant
Minimized line skew generator
- Patent number 8,542,050
- Issue date Sep 24, 2013
- Sony Corporation
- Jae-Hyeong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient method for implementing programmable impedance output dri...
- Patent number 7,646,215
- Issue date Jan 12, 2010
- Sony Corporation
- Robert B. Haig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic dual control on-die termination
- Patent number 7,595,657
- Issue date Sep 29, 2009
- Sony Corporation
- Robert Haig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shift registers free of timing race boundary scan registers with tw...
- Patent number 7,389,457
- Issue date Jun 17, 2008
- Sony Corporation
- Hsin-Ley Suzanne Chen
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic sense amplifier for SRAM
- Patent number 7,313,040
- Issue date Dec 25, 2007
- Sony Corporation
- Mu-Hsiang Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for effectively implementing a high speed DRAM de...
- Patent number 6,798,687
- Issue date Sep 28, 2004
- Sony Corporation
- Kuoyuan Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line voltage supply circuit
- Patent number 6,078,531
- Issue date Jun 20, 2000
- Sony Corporation
- Yoshifumi Miyazima
- G11 - INFORMATION STORAGE
Information Patent Grant
Duty cycle independent tunable clock
- Patent number 5,617,563
- Issue date Apr 1, 1997
- Sony Corporation of Japan
- Pradip Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital circuit for performing multicycle addressing in a digital m...
- Patent number 5,577,228
- Issue date Nov 19, 1996
- Sony Corporation of Japan
- Pradip Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheme to test/repair multiple large RAM blocks
- Patent number 5,537,355
- Issue date Jul 16, 1996
- Sony Corporation of Japan
- Pradip Banerjee
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge shared precharge scheme to reduce compare output delays
- Patent number 5,528,541
- Issue date Jun 18, 1996
- Sony Corporation of Japan
- Atul V. Ghia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance dynamic compare circuit
- Patent number 5,515,024
- Issue date May 7, 1996
- Sony Corporation of Japan
- Atul V. Ghia
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
RESULTS PROCESSING CIRCUITS AND METHODS ASSOCIATED WITH COMPUTATION...
- Publication number 20210216246
- Publication date Jul 15, 2021
- GSI TECHNOLOGY, INC.
- Bob Haig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ORTHOGONAL DATA TRANSPOSITION SYSTEM AND METHOD DURING DATA TRANSFE...
- Publication number 20210173647
- Publication date Jun 10, 2021
- GSI TECHNOLOGY, INC.
- Bob HAIG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESULTS PROCESSING CIRCUITS AND METHODS ASSOCIATED WITH COMPUTATION...
- Publication number 20200117398
- Publication date Apr 16, 2020
- GSI TECHNOLOGY, INC.
- Bob Haig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS INVOLVING LOCK-LOOP CIRCUITS, CLOCK SIGNAL ALIG...
- Publication number 20180109248
- Publication date Apr 19, 2018
- GSI Technology, Inc.
- Yu-Chi Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS INVOLVING PSEUDO COMPLEMENTARY OUTPUT BUFFER CI...
- Publication number 20170063372
- Publication date Mar 2, 2017
- GSI TECHNOLOGY, INC.
- Jae-Hyeong KIM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory Systems and Methods Involving High Speed Local Address Circu...
- Publication number 20160196858
- Publication date Jul 7, 2016
- GSI TECHNOLOGY, INC.
- Patrick CHUANG
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods Involving Multi-Bank, Dual- or Multi-Pipe SRAMs
- Publication number 20160189766
- Publication date Jun 30, 2016
- GSI TECHNOLOGY, INC.
- Robert HAIG
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods Involving Multi-Bank, Dual-Pipe Memory Circuitry
- Publication number 20150357028
- Publication date Dec 10, 2015
- GSI TECHNOLOGY, INC.
- Mu-Hsiang HUANG
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods Involving Multi-Bank, Dual- or Multi-Pipe SRAMs
- Publication number 20140304463
- Publication date Oct 9, 2014
- GSI TECHNOLOGY, INC.
- Robert HAIG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems And Methods Involving Multi-Bank, Dual- Or Multi-Pipe SRAMs
- Publication number 20130039131
- Publication date Feb 14, 2013
- Robert Haig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient method for implementing programmable impedance output dri...
- Publication number 20090237109
- Publication date Sep 24, 2009
- Sony Corporation, a Japanese corporation
- Robert B. Haig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dynamic dual control on-die termination
- Publication number 20080272800
- Publication date Nov 6, 2008
- SONY CORPORATION
- Robert Haig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Minimized line skew generator
- Publication number 20070096790
- Publication date May 3, 2007
- Sony Corporation
- Jae-Hyeong Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic sense amplifier for SRAM
- Publication number 20070097765
- Publication date May 3, 2007
- Sony Corporation
- Mu-Hsiang Huang
- G11 - INFORMATION STORAGE
Information Patent Application
Shift registers free of timing race boundary scan registers with tw...
- Publication number 20070101222
- Publication date May 3, 2007
- Sony Corporation
- Hsin-Ley Suzanne Chen
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor device tester pin contact resistance measurement
- Publication number 20070080697
- Publication date Apr 12, 2007
- Sony Corporation
- Chih-Chiang Tseng
- G01 - MEASURING TESTING
Information Patent Application
System and method for effectively implementing a high-speed DRAM de...
- Publication number 20040114420
- Publication date Jun 17, 2004
- Sony Corporation
- Kuoyuan Hsu
- G11 - INFORMATION STORAGE

Patrick Chuang

Person

Patents Grantslast 30 patents

Orthogonal data transposition system and method during data transfe...

Results processing circuits and methods associated with computation...

Ultra low VDD memory cell with ratioless write port

Results processing circuits and methods associated with computation...

Orthogonal data transposition system and method during data transfe...

Computational memory cell and processing array device with ratioles...

Read and write data processing circuits and methods associated with...

Systems and methods involving multi-bank, dual-pipe memory circuitry

Systems and methods involving lock loop circuits, distributed duty...

Systems and methods involving lock-loop circuits, clock signal alig...

Systems and methods involving pseudo complementary output buffer ci...

Systems and methods involving lock-loop circuits, clock signal alig...

Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

Memory systems and methods involving high speed local address circu...

Systems and methods involving data inversion devices, circuitry, sc...

Memory systems and methods involving high speed local address circu...

Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

Minimized line skew generator

Efficient method for implementing programmable impedance output dri...

Dynamic dual control on-die termination

Shift registers free of timing race boundary scan registers with tw...

Dynamic sense amplifier for SRAM

System and method for effectively implementing a high speed DRAM de...

Word line voltage supply circuit

Duty cycle independent tunable clock

Digital circuit for performing multicycle addressing in a digital m...

Scheme to test/repair multiple large RAM blocks

Charge shared precharge scheme to reduce compare output delays

High performance dynamic compare circuit

Patents Applicationslast 30 patents

RESULTS PROCESSING CIRCUITS AND METHODS ASSOCIATED WITH COMPUTATION...

ORTHOGONAL DATA TRANSPOSITION SYSTEM AND METHOD DURING DATA TRANSFE...

RESULTS PROCESSING CIRCUITS AND METHODS ASSOCIATED WITH COMPUTATION...

SYSTEMS AND METHODS INVOLVING LOCK-LOOP CIRCUITS, CLOCK SIGNAL ALIG...

SYSTEMS AND METHODS INVOLVING PSEUDO COMPLEMENTARY OUTPUT BUFFER CI...

Memory Systems and Methods Involving High Speed Local Address Circu...

Systems and Methods Involving Multi-Bank, Dual- or Multi-Pipe SRAMs

Systems and Methods Involving Multi-Bank, Dual-Pipe Memory Circuitry

Systems and Methods Involving Multi-Bank, Dual- or Multi-Pipe SRAMs

Systems And Methods Involving Multi-Bank, Dual- Or Multi-Pipe SRAMs

Efficient method for implementing programmable impedance output dri...

Dynamic dual control on-die termination

Minimized line skew generator

Dynamic sense amplifier for SRAM

Shift registers free of timing race boundary scan registers with tw...

Semiconductor device tester pin contact resistance measurement

System and method for effectively implementing a high-speed DRAM de...