Pin-Chin Connie Wang

Person

Menlo Park, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of using ternary copper alloy to obtain a low resistance and...
- Patent number 7,696,092
- Issue date Apr 13, 2010
- GLOBALFOUNDRIES Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of using an adhesion precursor layer for chemical vapor depo...
- Patent number 7,169,706
- Issue date Jan 30, 2007
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implanted barrier layer to improve line reliability and method of f...
- Patent number 6,992,004
- Issue date Jan 31, 2006
- Advanced Micro Devices, Inc.
- Paul R. Besser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with dielectric diffusion barrier layer formed b...
- Patent number 6,979,903
- Issue date Dec 27, 2005
- Advanced Micro Devices, Inc.
- Steven C. Avanzino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming conductor reservoir volume for integrated circui...
- Patent number 6,939,803
- Issue date Sep 6, 2005
- Advanced Micro Devices, Inc.
- Amit P. Marathe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing seedless barrier layers in integrated circuits
- Patent number 6,893,955
- Issue date May 17, 2005
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an adhesion layer with an element reactive with a...
- Patent number 6,861,349
- Issue date Mar 1, 2005
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing an integrated circuit with low solubility metal-condu...
- Patent number 6,841,473
- Issue date Jan 11, 2005
- Advanced Micro Devices, Inc.
- Pin-Chin Connie Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned barrier formed with an alloy having at least two dopan...
- Patent number 6,833,625
- Issue date Dec 21, 2004
- Advanced Micro Devices, Inc.
- Pin-Chin C. Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Continuous barrier for interconnect structure formed in porous diel...
- Patent number 6,831,003
- Issue date Dec 14, 2004
- Advanced Micro Devices, Inc.
- Richard J. Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an electroless nucleation layer on a via bottom
- Patent number 6,815,340
- Issue date Nov 9, 2004
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Coherent diffusion barriers for integrated circuit interconnects
- Patent number 6,710,452
- Issue date Mar 23, 2004
- Advanced Micro Devices, Inc.
- Pin-Chin Connie Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier metal oxide interconnect cap in integrated circuits
- Patent number 6,674,170
- Issue date Jan 6, 2004
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned barrier formed with an alloy having at least two dopan...
- Patent number 6,664,185
- Issue date Dec 16, 2003
- Advanced Micro Devices, Inc.
- Pin-Chin C. Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of performing a two stage anneal in the formation of an allo...
- Patent number 6,656,836
- Issue date Dec 2, 2003
- Advanced Micro Devices, Inc.
- Pin-Chin Connie Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with low solubility metal-conductor interconnect...
- Patent number 6,657,303
- Issue date Dec 2, 2003
- Advanced Micro Devices, Inc.
- Pin-Chin Connie Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electro-chemical metal alloying for semiconductor manufacturing
- Patent number 6,649,034
- Issue date Nov 18, 2003
- Advanced Micro Devices, Inc.
- Minh Quoc Tran
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Method of manufacturing an integrated circuit with a dielectric dif...
- Patent number 6,642,145
- Issue date Nov 4, 2003
- Advanced Micro Devices, Inc.
- Steven C. Avanzino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Characterization of barrier layers in integrated circuit interconnects
- Patent number 6,621,290
- Issue date Sep 16, 2003
- Advanced Micro Devices, Inc.
- Amit P. Marathe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING ME...
- Patent number 6,617,176
- Issue date Sep 9, 2003
- Advanced Micro Devices, Inc.
- John E. Sanchez
- G01 - MEASURING TESTING
Information Patent Grant
Selective deposition in integrated circuit interconnects
- Patent number 6,590,288
- Issue date Jul 8, 2003
- Advanced Micro Devices, Inc.
- Christy Mei-Chu Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar copper alloy target for plasma vapor deposition systems
- Patent number 6,589,408
- Issue date Jul 8, 2003
- Advanced Micro Devices, Inc.
- Pin-Chin Connie Wang
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Forming a strong interface between interconnect and encapsulation t...
- Patent number 6,573,179
- Issue date Jun 3, 2003
- Advanced Micro Devices, Inc.
- Pin-Chin C. Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Graphoepitaxial conductor cores in integrated circuit interconnects
- Patent number 6,566,248
- Issue date May 20, 2003
- Advanced Micro Devices, Inc.
- Pin-Chin Connie Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Seedless barrier layers in integrated circuits and a method of manu...
- Patent number 6,555,909
- Issue date Apr 29, 2003
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of promoting void free copper interconnects
- Patent number 6,548,395
- Issue date Apr 15, 2003
- Advanced Micro Devices, Inc.
- Christy Mei-Chu Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier-to-seed layer alloying in integrated circuit interconnects
- Patent number 6,541,860
- Issue date Apr 1, 2003
- Advanced Micro Devices, Inc.
- Christy Mei-Chu Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of enhanced fill of vias and trenches
- Patent number 6,534,865
- Issue date Mar 18, 2003
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Via formation in integrated circuit interconnects
- Patent number 6,531,780
- Issue date Mar 11, 2003
- Advanced Micro Devices, Inc.
- Christy Mei-Chu Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Depositing an adhesion skin layer and a conformal seed layer to fil...
- Patent number 6,528,412
- Issue date Mar 4, 2003
- Advanced Micro Devices, Inc.
- Pin-Chin C. Wang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT HAVING A BARRIER...
- Publication number 20040175926
- Publication date Sep 9, 2004
- Advanced Micro Devices, Inc.
- Pin-Chin Connie Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of using ternary copper alloy to obtain a low resistance and...
- Publication number 20040005773
- Publication date Jan 8, 2004
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for improving electromigration performance of metallization...
- Publication number 20030217462
- Publication date Nov 27, 2003
- Fei Wang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method for forming conductor reservoir volume for integrated circui...
- Publication number 20020195714
- Publication date Dec 26, 2002
- Amit P. Marathe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conductor reservoir volume for integrated circuit interconnects
- Publication number 20020093057
- Publication date Jul 18, 2002
- Amit P. Marathe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTROLLED ANNEAL CONDUCTORS FOR INTEGRATED CIRCUIT INTERCONNECTS
- Publication number 20020076923
- Publication date Jun 20, 2002
- Steven C. Avanzino
- H01 - BASIC ELECTRIC ELEMENTS

Pin-Chin Connie Wang

Person

Patents Grantslast 30 patents

Method of using ternary copper alloy to obtain a low resistance and...

Method of using an adhesion precursor layer for chemical vapor depo...

Implanted barrier layer to improve line reliability and method of f...

Integrated circuit with dielectric diffusion barrier layer formed b...

Method for forming conductor reservoir volume for integrated circui...

Manufacturing seedless barrier layers in integrated circuits

Method of forming an adhesion layer with an element reactive with a...

Manufacturing an integrated circuit with low solubility metal-condu...

Self-aligned barrier formed with an alloy having at least two dopan...

Continuous barrier for interconnect structure formed in porous diel...

Method of forming an electroless nucleation layer on a via bottom

Coherent diffusion barriers for integrated circuit interconnects

Barrier metal oxide interconnect cap in integrated circuits

Self-aligned barrier formed with an alloy having at least two dopan...

Method of performing a two stage anneal in the formation of an allo...

Integrated circuit with low solubility metal-conductor interconnect...

Electro-chemical metal alloying for semiconductor manufacturing

Method of manufacturing an integrated circuit with a dielectric dif...

Characterization of barrier layers in integrated circuit interconnects

METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING ME...

Selective deposition in integrated circuit interconnects

Non-planar copper alloy target for plasma vapor deposition systems

Forming a strong interface between interconnect and encapsulation t...

Graphoepitaxial conductor cores in integrated circuit interconnects

Seedless barrier layers in integrated circuits and a method of manu...

Method of promoting void free copper interconnects

Barrier-to-seed layer alloying in integrated circuit interconnects

Method of enhanced fill of vias and trenches

Via formation in integrated circuit interconnects

Depositing an adhesion skin layer and a conformal seed layer to fil...

Patents Applicationslast 30 patents

METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT HAVING A BARRIER...

Method of using ternary copper alloy to obtain a low resistance and...

Method for improving electromigration performance of metallization...

Method for forming conductor reservoir volume for integrated circui...

Conductor reservoir volume for integrated circuit interconnects

CONTROLLED ANNEAL CONDUCTORS FOR INTEGRATED CIRCUIT INTERCONNECTS