Richard G. Cliff

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Phase-locked loop architecture and clock distribution system
- Patent number 9,654,123
- Issue date May 16, 2017
- Altera Corporation
- Tien Duc Pham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop architecture and clock distribution system
- Patent number 9,350,530
- Issue date May 24, 2016
- Altera Corporation
- Tien Duc Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 9,094,014
- Issue date Jul 28, 2015
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop architecture and clock distribution system
- Patent number 8,866,520
- Issue date Oct 21, 2014
- Altera Corporation
- Tien Duc Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,732,646
- Issue date May 20, 2014
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for improving performance of field programmable gate arra...
- Patent number 8,698,516
- Issue date Apr 15, 2014
- Altera Corporation
- Irfan Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop architecture and clock distribution system
- Patent number 8,542,042
- Issue date Sep 24, 2013
- Altera Corporation
- Tien Duc Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus for configuring performance of field programmable gate ar...
- Patent number 8,461,869
- Issue date Jun 11, 2013
- Altera Corporation
- Irfan Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,407,649
- Issue date Mar 26, 2013
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop architecture and clock distribution system
- Patent number 8,228,102
- Issue date Jul 24, 2012
- Altera Corporation
- Tien Duc Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,201,129
- Issue date Jun 12, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for adjusting performance of programmable log...
- Patent number 8,198,914
- Issue date Jun 12, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for adjusting performance of programmable log...
- Patent number 7,936,184
- Issue date May 3, 2011
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Passgate structures for use in low-voltage applications
- Patent number 7,800,405
- Issue date Sep 21, 2010
- Altera Corporation
- Andy L Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-power transceiver architectures for programmable logic integrat...
- Patent number 7,750,674
- Issue date Jul 6, 2010
- Altera Corporation
- Sergey Shumarayev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reducing false positives in configuration error detection for progr...
- Patent number 7,620,876
- Issue date Nov 17, 2009
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 7,584,447
- Issue date Sep 1, 2009
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Passgate structures for use in low-voltage applications
- Patent number 7,557,608
- Issue date Jul 7, 2009
- Altera Corporation
- Andy L Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-power transceiver architectures for programmable logic integrat...
- Patent number 7,403,035
- Issue date Jul 22, 2008
- Altera Corporation
- Sergey Shumarayev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple size memories in a programmable logic device
- Patent number 7,236,008
- Issue date Jun 26, 2007
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic integrated circuit devices with low voltage diff...
- Patent number 7,196,556
- Issue date Mar 27, 2007
- Altera Corporation
- Khai Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase-locked loop circuitry for programmable logic devices
- Patent number 7,190,755
- Issue date Mar 13, 2007
- Altera Corporation
- Chiakang Sung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple size memories in a programmable logic device
- Patent number 7,161,381
- Issue date Jan 9, 2007
- Altera Corporation
- Srinivas Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PCI-compatible programmable logic devices
- Patent number 7,148,722
- Issue date Dec 12, 2006
- Altera Corporation
- Richard G Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Passage structures for use in low-voltage applications
- Patent number 7,119,574
- Issue date Oct 10, 2006
- Altera Corporation
- Andy L Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuits with reduced standby power consumption
- Patent number 7,109,748
- Issue date Sep 19, 2006
- Altera Corporation
- Yow-Juang W Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for designing PLD architectures for flexible placement of I...
- Patent number 7,058,920
- Issue date Jun 6, 2006
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
I/O cell configuration for multiple I/O standards
- Patent number 7,034,570
- Issue date Apr 25, 2006
- Altera Corporation
- Cameron McClintock
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Time-multiplexed routing in a programmable logic device architecture
- Patent number 6,977,520
- Issue date Dec 20, 2005
- Altera Corporation
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Routing architecture for a programmable logic device
- Patent number 6,970,014
- Issue date Nov 29, 2005
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20140210515
- Publication date Jul 31, 2014
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20130214815
- Publication date Aug 22, 2013
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS FOR IMPROVING PERFORMANCE OF FIELD PROGRAMMABLE GATE ARRA...
- Publication number 20130043902
- Publication date Feb 21, 2013
- Irfan Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20120217998
- Publication date Aug 30, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and methods for adjusting performance of programmable log...
- Publication number 20110204919
- Publication date Aug 25, 2011
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EMBEDDED DIGITAL IP STRIP CHIP
- Publication number 20100277201
- Publication date Nov 4, 2010
- Curt Wortman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PASSGATE STRUCTURES FOR USE IN LOW-VOLTAGE APPLICATIONS
- Publication number 20090267645
- Publication date Oct 29, 2009
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20090224800
- Publication date Sep 10, 2009
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low-power transceiver architectures for programmable logic integrat...
- Publication number 20080258765
- Publication date Oct 23, 2008
- Sergey Shumarayev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and methods for adjusting performance of programmable log...
- Publication number 20070200596
- Publication date Aug 30, 2007
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Passgate structures for use in low-voltage applications
- Publication number 20070008000
- Publication date Jan 11, 2007
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reducing false positives in configuration error detection for progr...
- Publication number 20070011578
- Publication date Jan 11, 2007
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLD architecture for flexible placement of IP functions blocks
- Publication number 20060033527
- Publication date Feb 16, 2006
- ALTERA CORPORATION, a corporation of Delaware
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
I/O cell configuration for multiple I/O standards
- Publication number 20050151564
- Publication date Jul 14, 2005
- Altera Corporation
- Cameron McClintock
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuits
- Publication number 20040066212
- Publication date Apr 8, 2004
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD architecture for flexible placement of IP function blocks
- Publication number 20030237071
- Publication date Dec 25, 2003
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20030201794
- Publication date Oct 30, 2003
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuit devices
- Publication number 20030128051
- Publication date Jul 10, 2003
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuits
- Publication number 20030128052
- Publication date Jul 10, 2003
- ALTERA CORPORATION, a corporation of Delaware
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device architectures with super-regions having l...
- Publication number 20030080778
- Publication date May 1, 2003
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20030076130
- Publication date Apr 24, 2003
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuit devices
- Publication number 20030016053
- Publication date Jan 23, 2003
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD architecture for flexible placement of IP function blocks
- Publication number 20020163356
- Publication date Nov 7, 2002
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for asymmetric routing lines
- Publication number 20020166106
- Publication date Nov 7, 2002
- David M. Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programming mode selection with JTAG circuits
- Publication number 20020157078
- Publication date Oct 24, 2002
- Altera Corporation
- Xiaobao Wang
- G01 - MEASURING TESTING
Information Patent Application
Programmable logic array integrated circuits
- Publication number 20020130681
- Publication date Sep 19, 2002
- Richard G. Cliff
- G01 - MEASURING TESTING
Information Patent Application
Programmable logic device architectures with super-regions having l...
- Publication number 20020084801
- Publication date Jul 4, 2002
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20020041191
- Publication date Apr 11, 2002
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device logic modules with shift register capabil...
- Publication number 20010048320
- Publication date Dec 6, 2001
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE LOGIC ARRAY INTEGRATED CIRCUITS WITH BLOCKS OF LOGIC R...
- Publication number 20010043083
- Publication date Nov 22, 2001
- RICHARD G. CLIFF
- H03 - BASIC ELECTRONIC CIRCUITRY

Richard G. Cliff

Person

Patents Grantslast 30 patents

Phase-locked loop architecture and clock distribution system

Phase-locked loop architecture and clock distribution system

PLD architecture for flexible placement of IP function blocks

Phase-locked loop architecture and clock distribution system

PLD architecture for flexible placement of IP function blocks

Apparatus for improving performance of field programmable gate arra...

Phase-locked loop architecture and clock distribution system

Apparatus for configuring performance of field programmable gate ar...

PLD architecture for flexible placement of IP function blocks

Phase-locked loop architecture and clock distribution system

PLD architecture for flexible placement of IP function blocks

Apparatus and methods for adjusting performance of programmable log...

Apparatus and methods for adjusting performance of programmable log...

Passgate structures for use in low-voltage applications

Low-power transceiver architectures for programmable logic integrat...

Reducing false positives in configuration error detection for progr...

PLD architecture for flexible placement of IP function blocks

Passgate structures for use in low-voltage applications

Low-power transceiver architectures for programmable logic integrat...

Multiple size memories in a programmable logic device

Programmable logic integrated circuit devices with low voltage diff...

Phase-locked loop circuitry for programmable logic devices

Multiple size memories in a programmable logic device

PCI-compatible programmable logic devices

Passage structures for use in low-voltage applications

Integrated circuits with reduced standby power consumption

Methods for designing PLD architectures for flexible placement of I...

I/O cell configuration for multiple I/O standards

Time-multiplexed routing in a programmable logic device architecture

Routing architecture for a programmable logic device

Patents Applicationslast 30 patents

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

APPARATUS FOR IMPROVING PERFORMANCE OF FIELD PROGRAMMABLE GATE ARRA...

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

Apparatus and methods for adjusting performance of programmable log...

EMBEDDED DIGITAL IP STRIP CHIP

PASSGATE STRUCTURES FOR USE IN LOW-VOLTAGE APPLICATIONS

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

Low-power transceiver architectures for programmable logic integrat...

Apparatus and methods for adjusting performance of programmable log...

Passgate structures for use in low-voltage applications

Reducing false positives in configuration error detection for progr...

PLD architecture for flexible placement of IP functions blocks

I/O cell configuration for multiple I/O standards

Programmable logic array integrated circuits

PLD architecture for flexible placement of IP function blocks

Programmable logic device with hierarchical interconnection resources

Programmable logic array integrated circuit devices

Programmable logic array integrated circuits

Programmable logic device architectures with super-regions having l...

Programmable logic device with hierarchical interconnection resources

Programmable logic array integrated circuit devices

PLD architecture for flexible placement of IP function blocks

System and method for asymmetric routing lines

Programming mode selection with JTAG circuits

Programmable logic array integrated circuits

Programmable logic device architectures with super-regions having l...

Programmable logic device with hierarchical interconnection resources

Programmable logic device logic modules with shift register capabil...

PROGRAMMABLE LOGIC ARRAY INTEGRATED CIRCUITS WITH BLOCKS OF LOGIC R...