Robert Kaiser

Person

Kaufering, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit
- Patent number 7,808,272
- Issue date Oct 5, 2010
- Qimonda AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Loop-back method for measuring the interface timing of semiconducto...
- Patent number 7,398,444
- Issue date Jul 8, 2008
- Infineon Technologies AG
- Martin Brox
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing semiconductor memory modules
- Patent number 7,296,198
- Issue date Nov 13, 2007
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for comparing the address of a memory access with an already...
- Patent number 7,181,643
- Issue date Feb 20, 2007
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing an integrated circuit using multiple test modes
- Patent number 7,165,198
- Issue date Jan 16, 2007
- Infineon Technologies AG
- Robert Kaiser
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit having a data processing unit and a buffer memory
- Patent number 7,047,454
- Issue date May 16, 2006
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated test circuit in an integrated circuit
- Patent number 7,034,559
- Issue date Apr 25, 2006
- Infineon Technologies AG
- Gerd Frankowsky
- G01 - MEASURING TESTING
Information Patent Grant
Circuit configuration for driving a programmable link
- Patent number 6,868,028
- Issue date Mar 15, 2005
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for driving a programmable link
- Patent number 6,807,123
- Issue date Oct 19, 2004
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for operating a semiconductor memory at double...
- Patent number 6,804,166
- Issue date Oct 12, 2004
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor component for connection to a test system
- Patent number 6,800,817
- Issue date Oct 5, 2004
- Infineon Technologies AG
- Helmut Schneider
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for driving a programmable link
- Patent number 6,768,695
- Issue date Jul 27, 2004
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a self-test device for carrying out a sel...
- Patent number 6,728,902
- Issue date Apr 27, 2004
- Infineon Technologies AG
- Robert Kaiser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor module
- Patent number 6,717,437
- Issue date Apr 6, 2004
- Infineon Technologies AG
- Heinrich Hemmert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration for generating signal impulses of defined lengths in...
- Patent number 6,715,118
- Issue date Mar 30, 2004
- Infineon Technologies AG
- Robert Kaiser
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit having a timing circuit, and method for adjustme...
- Patent number 6,628,156
- Issue date Sep 30, 2003
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory configuration with a central connection area
- Patent number 6,560,134
- Issue date May 6, 2003
- Infineon Technologies AG
- Martin Brox
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of reading electrical fuses/antifuses
- Patent number 6,552,549
- Issue date Apr 22, 2003
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor circuit with an increased operating voltage
- Patent number 6,535,046
- Issue date Mar 18, 2003
- Infineon Technologies AG
- Robert Kaiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor circuit configuration
- Patent number 6,449,206
- Issue date Sep 10, 2002
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor circuit with an increased operating voltage
- Patent number 6,441,677
- Issue date Aug 27, 2002
- Infineon Technologies AG
- Robert Kaiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having a self-test device and method for produci...
- Patent number 6,415,406
- Issue date Jul 2, 2002
- Siemens Aktiengesellschaft
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Refresh drive circuit for a DRAM
- Patent number 6,404,690
- Issue date Jun 11, 2002
- Infineon Technologies AG
- Bret Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for programming an electrically programmable...
- Patent number 6,366,518
- Issue date Apr 2, 2002
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling transistor threshold potentials using substrate potentials
- Patent number 6,353,357
- Issue date Mar 5, 2002
- Infineon Technologies AG
- Robert Kaiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated semiconductor memory
- Patent number 6,304,491
- Issue date Oct 16, 2001
- Infineon Technologies AG
- Bret Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for repairing defective memory cells of an integrated semico...
- Patent number 6,292,414
- Issue date Sep 18, 2001
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for monitoring states of a memory device
- Patent number 6,288,939
- Issue date Sep 11, 2001
- Infineon Technologies
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor memory configuration with self-buffering o...
- Patent number 6,236,612
- Issue date May 22, 2001
- Siemens Aktiengesellschaft
- Athanasia Chrysostomides
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated memory having a self-repair function
- Patent number 6,178,124
- Issue date Jan 23, 2001
- Siemens Aktiengesllschaft
- Robert Kaiser
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Integrated circuit
- Publication number 20060265440
- Publication date Nov 23, 2006
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Semi-conductor component, as well as a process for the reading of t...
- Publication number 20060085704
- Publication date Apr 20, 2006
- Infineon Technologies AG
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Loop-back method for measuring the interface timing of semiconducto...
- Publication number 20060059397
- Publication date Mar 16, 2006
- Martin Brox
- G01 - MEASURING TESTING
Information Patent Application
Integrated test circuit in an integrated circuit
- Publication number 20040222810
- Publication date Nov 11, 2004
- Gerd Frankowsky
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit having a test circuit
- Publication number 20040222812
- Publication date Nov 11, 2004
- Gerd Frankowsky
- G01 - MEASURING TESTING
Information Patent Application
Method for comparing the address of a memory access with an already...
- Publication number 20040153843
- Publication date Aug 5, 2004
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for operating a semiconductor memory at double...
- Publication number 20040066701
- Publication date Apr 8, 2004
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for driving a programmable link
- Publication number 20040037128
- Publication date Feb 26, 2004
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for driving a programmable link
- Publication number 20040032787
- Publication date Feb 19, 2004
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for driving a programmable link
- Publication number 20040004892
- Publication date Jan 8, 2004
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
System for testing an integrated circuit
- Publication number 20030028824
- Publication date Feb 6, 2003
- Robert Kaiser
- G01 - MEASURING TESTING
Information Patent Application
Integrated semiconductor circuit with an increased operating voltage
- Publication number 20020171469
- Publication date Nov 21, 2002
- Infineon Technologies AG
- Robert Kaiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for supplying current to a semiconductor memor...
- Publication number 20020170023
- Publication date Nov 14, 2002
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Method for testing semiconductor memory modules
- Publication number 20020157049
- Publication date Oct 24, 2002
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Method for identifying an integrated circuit and integrated circuit
- Publication number 20020149979
- Publication date Oct 17, 2002
- Robert Kaiser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and memory system for writing in data
- Publication number 20020136061
- Publication date Sep 26, 2002
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor module
- Publication number 20020135411
- Publication date Sep 26, 2002
- Heinrich Hemmert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor component for connection to a test system
- Publication number 20020097616
- Publication date Jul 25, 2002
- Helmut Schneider
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit having a data processing unit and a buffer memory
- Publication number 20020083380
- Publication date Jun 27, 2002
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Memory configuration with a central connection area
- Publication number 20020062430
- Publication date May 23, 2002
- Martin Brox
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit having a timing circuit, and method for adjustme...
- Publication number 20020027462
- Publication date Mar 7, 2002
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor circuit configuration
- Publication number 20010050416
- Publication date Dec 13, 2001
- Robert Kaiser
- G11 - INFORMATION STORAGE
Information Patent Application
Refresh drive circuit for a DRAM
- Publication number 20010036118
- Publication date Nov 1, 2001
- Bret Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Configuration for generating signal impulses of defined lengths in...
- Publication number 20010018754
- Publication date Aug 30, 2001
- Robert Kaiser
- G01 - MEASURING TESTING
Information Patent Application
Integrated semiconductor memory
- Publication number 20010015914
- Publication date Aug 23, 2001
- Bret Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit having a self-test device for carrying out a sel...
- Publication number 20010011904
- Publication date Aug 9, 2001
- Robert Kaiser
- G01 - MEASURING TESTING

Robert Kaiser

Person

Patents Grantslast 30 patents

Integrated circuit

Loop-back method for measuring the interface timing of semiconducto...

Method for testing semiconductor memory modules

Method for comparing the address of a memory access with an already...

System for testing an integrated circuit using multiple test modes

Integrated circuit having a data processing unit and a buffer memory

Integrated test circuit in an integrated circuit

Circuit configuration for driving a programmable link

Circuit configuration for driving a programmable link

Method and apparatus for operating a semiconductor memory at double...

Semiconductor component for connection to a test system

Circuit configuration for driving a programmable link

Integrated circuit having a self-test device for carrying out a sel...

Semiconductor module

Configuration for generating signal impulses of defined lengths in...

Integrated circuit having a timing circuit, and method for adjustme...

Memory configuration with a central connection area

Method of reading electrical fuses/antifuses

Integrated semiconductor circuit with an increased operating voltage

Semiconductor circuit configuration

Integrated semiconductor circuit with an increased operating voltage

Integrated circuit having a self-test device and method for produci...

Refresh drive circuit for a DRAM

Circuit configuration for programming an electrically programmable...

Controlling transistor threshold potentials using substrate potentials

Integrated semiconductor memory

Method for repairing defective memory cells of an integrated semico...

Circuit configuration for monitoring states of a memory device

Integrated semiconductor memory configuration with self-buffering o...

Integrated memory having a self-repair function

Patents Applicationslast 30 patents

Integrated circuit

Semi-conductor component, as well as a process for the reading of t...

Loop-back method for measuring the interface timing of semiconducto...

Integrated test circuit in an integrated circuit

Integrated circuit having a test circuit

Method for comparing the address of a memory access with an already...

Method and apparatus for operating a semiconductor memory at double...

Circuit configuration for driving a programmable link

Circuit configuration for driving a programmable link

Circuit configuration for driving a programmable link

System for testing an integrated circuit

Integrated semiconductor circuit with an increased operating voltage

Method and apparatus for supplying current to a semiconductor memor...

Method for testing semiconductor memory modules

Method for identifying an integrated circuit and integrated circuit

Method and memory system for writing in data

Semiconductor module

Semiconductor component for connection to a test system

Integrated circuit having a data processing unit and a buffer memory

Memory configuration with a central connection area

Integrated circuit having a timing circuit, and method for adjustme...

Semiconductor circuit configuration

Refresh drive circuit for a DRAM

Configuration for generating signal impulses of defined lengths in...

Integrated semiconductor memory

Integrated circuit having a self-test device for carrying out a sel...