Robert Kraft

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for manufacturing piezoelectric bulk layers with tilted c-ax...
- Patent number 11,824,511
- Issue date Nov 21, 2023
- Qorvo US, Inc.
- Derya Deniz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Piezoelectric bulk layers with tilted c-axis orientation and method...
- Patent number 11,381,212
- Issue date Jul 5, 2022
- Qorvo US, Inc.
- Derya Deniz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Wafer-level-packaged BAW devices with surface mount connection stru...
- Patent number 10,367,470
- Issue date Jul 30, 2019
- Qorvo US, Inc.
- Matthew L. Wasilik
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ferroelectric capacitor manufacturing process
- Patent number 7,985,603
- Issue date Jul 26, 2011
- Texas Instruments Incorporated
- Francis Gabriel Celii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods that selectively modify liner induced stress
- Patent number 7,939,400
- Issue date May 10, 2011
- Texas Instruments Incorporated
- Ting Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for cleaning post-etch noble metal residues
- Patent number 7,723,199
- Issue date May 25, 2010
- Texas Instruments Incorporated
- Yaw S. Obeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing line edge roughness for conductive features
- Patent number 7,687,407
- Issue date Mar 30, 2010
- Texas Instruments Incorporated
- David G. Farber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of a silicon oxide interface layer during silicon carbide...
- Patent number 7,682,989
- Issue date Mar 23, 2010
- Texas Instruments Incorporated
- Laura M. Matz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Energy beam treatment to improve packaging reliability
- Patent number 7,678,713
- Issue date Mar 16, 2010
- Texas Instruments Incorporated
- Ting Y. Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods that selectively modify liner induced stress
- Patent number 7,442,597
- Issue date Oct 28, 2008
- Texas Instruments Incorporated
- Ting Y. Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods to facilitate etch uniformity and selectivity
- Patent number 7,341,941
- Issue date Mar 11, 2008
- Texas Instruments Incorporated
- Ting Y. Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for patterning sub-lithographic features in semiconductor ma...
- Patent number 7,300,883
- Issue date Nov 27, 2007
- Texas Instruments Incorporated
- Francis G. Celii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma treatment for silicon-based dielectrics
- Patent number 7,282,436
- Issue date Oct 16, 2007
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming single damascene via or trench cavities and for...
- Patent number 7,214,609
- Issue date May 8, 2007
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via formation for damascene metal conductors in an integrated circuit
- Patent number 7,119,006
- Issue date Oct 10, 2006
- Texas Instruments Incorporated
- Robert Kraft
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of passivating and/or removing contaminants on a low-k diele...
- Patent number 7,087,518
- Issue date Aug 8, 2006
- Texas Instruments Incorporated
- David Gerald Farber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene pattern liner
- Patent number 6,984,580
- Issue date Jan 10, 2006
- Texas Instruments Incorporated
- William W. Dostalik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
BARC etch comprising a selective etch chemistry and a high polymeri...
- Patent number 6,900,123
- Issue date May 31, 2005
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process flow for dual damescene interconnect structures
- Patent number 6,872,665
- Issue date Mar 29, 2005
- Texas Instruments Incorporated
- Francis G. Celii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-situ plasma ash/treatment after via etch of low-k films for pois...
- Patent number 6,797,633
- Issue date Sep 28, 2004
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch back of interconnect dielectrics
- Patent number 6,780,756
- Issue date Aug 24, 2004
- Texas Instruments Incorporated
- David G. Farber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma treatment of low-k dielectric films to improve patterning
- Patent number 6,620,560
- Issue date Sep 16, 2003
- Texax Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate stack and etch process
- Patent number 6,607,985
- Issue date Aug 19, 2003
- Texas Instruments Incorporated
- Robert Kraft
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication technique for controlled incorporation of nitrogen in g...
- Patent number 6,399,445
- Issue date Jun 4, 2002
- Texas Instruments Incorporated
- Sunil V. Hattangady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tunable gate linewidth reduction process
- Patent number 6,362,111
- Issue date Mar 26, 2002
- Texas Instruments Incorporated
- Reima Laaksonen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dry etch process for small-geometry metal gates over thin gate diel...
- Patent number 6,261,934
- Issue date Jul 17, 2001
- Texas Instruments Incorporated
- Robert Kraft
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon processing method
- Patent number 6,214,736
- Issue date Apr 10, 2001
- Texas Instruments Incorporated
- Antonio L. P. Rotondaro
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming thin silicon nitride or silicon oxynitride gate d...
- Patent number 6,136,654
- Issue date Oct 24, 2000
- Texas Instruments Incorporated
- Robert Kraft
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor stack having a dielectric sidewall for prevention of...
- Patent number 5,796,151
- Issue date Aug 18, 1998
- Texas Instruments Incorporated
- Wei-Yung Hsu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PIEZOELECTRIC BULK LAYERS WITH TILTED C-AXIS ORIENTATION AND METHOD...
- Publication number 20220271726
- Publication date Aug 25, 2022
- Qorvo US, Inc.
- Derya Deniz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
PIEZOELECTRIC BULK LAYERS WITH TILTED C-AXIS ORIENTATION AND METHOD...
- Publication number 20190296707
- Publication date Sep 26, 2019
- Qorvo US, Inc.
- Derya Deniz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
PIEZOELECTRIC BULK LAYERS WITH TILTED C-AXIS ORIENTATION AND METHOD...
- Publication number 20190296710
- Publication date Sep 26, 2019
- Qorvo US, Inc.
- Derya Deniz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
WAFER-LEVEL-PACKAGED BAW DEVICES WITH SURFACE MOUNT CONNECTION STRU...
- Publication number 20180109237
- Publication date Apr 19, 2018
- Qorvo US, Inc.
- Matthew L. Wasilik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FERROELECTRIC CAPACITOR MANUFACTURING PROCESS
- Publication number 20090194801
- Publication date Aug 6, 2009
- Texas Instruments Inc.
- Francis Gabriel Celii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS THAT SELECTIVELY MODIFY LINER INDUCED STRESS
- Publication number 20090017588
- Publication date Jan 15, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Ting Y. Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF A SILICON OXIDE INTERFACE LAYER DURING SILICON CARBIDE...
- Publication number 20080283975
- Publication date Nov 20, 2008
- Laura M. Matz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for...
- Publication number 20080014739
- Publication date Jan 17, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Laura M. Matz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR CLEANING POST-ETCH NOBLE METAL RESIDUES
- Publication number 20070298521
- Publication date Dec 27, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Yaw S. Obeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTIVE DEVICE HAVING RESIST POISON ALUMINUM OXIDE BARRIER A...
- Publication number 20070290347
- Publication date Dec 20, 2007
- TEXAS INSTRUMENTS INCORPORATED
- William W. Dostalik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a microelectronic device using electron beam...
- Publication number 20070105368
- Publication date May 10, 2007
- Texas Instruments Inc.
- Ting Y. Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods to facilitate etch uniformity and selectivity
- Publication number 20070042599
- Publication date Feb 22, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Ting Y. Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Energy beam treatment to improve packaging reliability
- Publication number 20070032094
- Publication date Feb 8, 2007
- Texas Instruments, Incorporated
- Ting Y. Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect structure including a silicon oxycarbonitride layer
- Publication number 20060264042
- Publication date Nov 23, 2006
- Texas Instruments, Incorporated
- Laura M. Matz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Energy beam treatment to improve the hermeticity of a hermetic layer
- Publication number 20060264028
- Publication date Nov 23, 2006
- Texas Instruments, Incorporated
- Laura M. Matz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Systems and methods that selectively modify liner induced stress
- Publication number 20060172481
- Publication date Aug 3, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Ting Y. Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing line edge roughness for conductive features
- Publication number 20060121739
- Publication date Jun 8, 2006
- Texas Instruments, Inc.
- David G. Farber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for patterning sub-lithographic features in semiconductor ma...
- Publication number 20060046498
- Publication date Mar 2, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Francis G. Celii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Plasma treatment for silicon-based dielectrics
- Publication number 20050255687
- Publication date Nov 17, 2005
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
In-situ etch-stop etch and ashing in association with damascene pro...
- Publication number 20050245074
- Publication date Nov 3, 2005
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual damascene pattern liner
- Publication number 20040222529
- Publication date Nov 11, 2004
- William W. Dostalik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual damascene pattern liner
- Publication number 20040222527
- Publication date Nov 11, 2004
- William W. Dostalik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Barc etch comprising a selective etch chemistry and a high polymeri...
- Publication number 20040185655
- Publication date Sep 23, 2004
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Etch back of interconnect dielectrics
- Publication number 20040169279
- Publication date Sep 2, 2004
- David G. Farber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH BACK OF INTERCONNECT DIELECTRICS
- Publication number 20040169280
- Publication date Sep 2, 2004
- David G. Farber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for forming single damascene via or trench cavities and for...
- Publication number 20040110369
- Publication date Jun 10, 2004
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Via formation for damascene metal conductors in an integrated circuit
- Publication number 20040100779
- Publication date May 27, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Robert Kraft
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of passivating and/or removing contaminants on a low-k diele...
- Publication number 20030224585
- Publication date Dec 4, 2003
- David Gerald Farber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for forming vias and trenches with controlled SiC etch rate...
- Publication number 20030181034
- Publication date Sep 25, 2003
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of passivating and/or removing contaminants on a low-k diele...
- Publication number 20030170992
- Publication date Sep 11, 2003
- David Gerald Farber
- H01 - BASIC ELECTRIC ELEMENTS

Robert Kraft

Person

Patents Grantslast 30 patents

Method for manufacturing piezoelectric bulk layers with tilted c-ax...

Piezoelectric bulk layers with tilted c-axis orientation and method...

Wafer-level-packaged BAW devices with surface mount connection stru...

Ferroelectric capacitor manufacturing process

Systems and methods that selectively modify liner induced stress

Method for cleaning post-etch noble metal residues

Method for reducing line edge roughness for conductive features

Formation of a silicon oxide interface layer during silicon carbide...

Energy beam treatment to improve packaging reliability

Systems and methods that selectively modify liner induced stress

Methods to facilitate etch uniformity and selectivity

Method for patterning sub-lithographic features in semiconductor ma...

Plasma treatment for silicon-based dielectrics

Methods for forming single damascene via or trench cavities and for...

Via formation for damascene metal conductors in an integrated circuit

Method of passivating and/or removing contaminants on a low-k diele...

Dual damascene pattern liner

BARC etch comprising a selective etch chemistry and a high polymeri...

Process flow for dual damescene interconnect structures

In-situ plasma ash/treatment after via etch of low-k films for pois...

Etch back of interconnect dielectrics

Plasma treatment of low-k dielectric films to improve patterning

Gate stack and etch process

Fabrication technique for controlled incorporation of nitrogen in g...

Tunable gate linewidth reduction process

Dry etch process for small-geometry metal gates over thin gate diel...

Silicon processing method

Method of forming thin silicon nitride or silicon oxynitride gate d...

Semiconductor stack having a dielectric sidewall for prevention of...

Patents Applicationslast 30 patents

PIEZOELECTRIC BULK LAYERS WITH TILTED C-AXIS ORIENTATION AND METHOD...

PIEZOELECTRIC BULK LAYERS WITH TILTED C-AXIS ORIENTATION AND METHOD...

PIEZOELECTRIC BULK LAYERS WITH TILTED C-AXIS ORIENTATION AND METHOD...

WAFER-LEVEL-PACKAGED BAW DEVICES WITH SURFACE MOUNT CONNECTION STRU...

FERROELECTRIC CAPACITOR MANUFACTURING PROCESS

SYSTEMS AND METHODS THAT SELECTIVELY MODIFY LINER INDUCED STRESS

FORMATION OF A SILICON OXIDE INTERFACE LAYER DURING SILICON CARBIDE...

Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for...

METHOD FOR CLEANING POST-ETCH NOBLE METAL RESIDUES

SEMICONDUCTIVE DEVICE HAVING RESIST POISON ALUMINUM OXIDE BARRIER A...

Method of fabricating a microelectronic device using electron beam...

Methods to facilitate etch uniformity and selectivity

Energy beam treatment to improve packaging reliability

Interconnect structure including a silicon oxycarbonitride layer

Energy beam treatment to improve the hermeticity of a hermetic layer

Systems and methods that selectively modify liner induced stress

Method for reducing line edge roughness for conductive features

Method for patterning sub-lithographic features in semiconductor ma...

Plasma treatment for silicon-based dielectrics

In-situ etch-stop etch and ashing in association with damascene pro...

Dual damascene pattern liner

Dual damascene pattern liner

Barc etch comprising a selective etch chemistry and a high polymeri...

Etch back of interconnect dielectrics

ETCH BACK OF INTERCONNECT DIELECTRICS

Methods for forming single damascene via or trench cavities and for...

Via formation for damascene metal conductors in an integrated circuit

Method of passivating and/or removing contaminants on a low-k diele...

Methods for forming vias and trenches with controlled SiC etch rate...

Method of passivating and/or removing contaminants on a low-k diele...