For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The illustrated semiconductor device 100 further includes interlevel dielectric layers (IDL) 140 and 145. IDL 140 and 145 may be deposited as single layers, or they comprise stacked layers. To reduce capacitance, IDL 140 and 145 are comprised of a low-k dielectric material. These low-k materials are often used in dielectric layers past metal level one that is located on the PMD layer 135. The low-k materials typically may be conventional materials that have dielectric constants that are lower than silicon dioxide; that is less than 4.0 and more often 3.0 or in another embodiment about 2.8 or less. When used, low-k materials provide a device that has less parasitic capacitance associated with it, which reduces RC delay. As a result the operating speed of the device is increased. ILD 140 and 145 are representative of any level past metal level one.
Located within each of the ILD 140 and 145 are interconnects 150a 150b, and they may be of conventional design as well. IDL 140 and 145 may contain single damascene interconnects 150a and at least one dual damascene interconnect 150b. IDL 140 and 145 contain metal lines 152 that properly route electrical signals and power properly through the electronic device. IDL 145 also includes vias 153 that properly connect the metal lines of one layer (IDL 145) to the metal lines of another layer (IDL 140). The semiconductor device 100 may also include a conventional barrier layer 155 located on each of ILD 140 and 145. The barrier layer 155 may be a single layer or may comprise a stack of layers. A relatively thin aluminum oxide (AlxOy) barrier 160 is also included in the semiconductor device 100, and may be a single layer or have a stacked configuration. The advantages of using the AlxOy barrier 160 by itself or in combination with the barrier layer 155 are discussed below.
A barrier layer 220 is located on each of the IDL 205 and 210, and as explained below, it may have a number of purposes. The barrier layer 220 may comprise a conventional material, such as silicon, nitrogen, or carbon, and conventional processes, such as plasma enhanced chemical vapor deposition, may be used to deposit this layer to the appropriate thickness. It should be noted that the barrier layer 220 is deposited in a blanket fashion to be substantially laterally co-extensive with the IDLs 205 and 210. That is, the lateral extension of the barrier layer 220 is such that it extends over the entire wafer, excluding any wafer edge effects. The barrier layer 220 may comprise silicon carbide nitride (SiCN), silicon nitride (SiN), silicon carbide (SiC), or combinations thereof. In those instances where the barrier layer 220 contains nitrogen, they often can be poisoning agents in that they can serves as a source for nitrogen that can poison an overlying resist.
Often, low-k IDLs do not adhere well to the metal lines 215. The barrier layer 220 is used to help adhere IDL 205 and 210 to each other. However, the barrier layer 220 often does not adhere well to IDL 205 and 210. To circumvent this problem, the surfaces of IDL 205 and 210 are often treated with ammonia (NH3) prior to the deposition of the barrier layer 220. A conventional ammonia treatment may be used to treat the upper surfaces of IDL 205 and 210. In addition, the barrier layer 220 may also serve as an etch stop in forming the via of an interconnect.
Following the deposition of the barrier layer 220, in one embodiment, an AlxOy barrier 225 is deposited over the barrier layer 220. It has been found that the AlxOy barrier 225 is effective in reducing resist poisoning because it effectively blocks the migration of nitrogen or amines that emanate from the treated IDL or nitrogen that might emanate from the underlying barrier layer 220, both of which may be resist poisoning agents.
The AlxOy barrier 225 may be deposited using source gases comprising trimethylaluminum (TMA), flowed at rate ranging from about 50 sccm to about 500 sccm, with 250 sccm being used in one advantageous embodiment. Ozone may also be flowed at a rate ranging from about 200 sccm to about 10000 sccm, with 600 sccm being used in one advantageous embodiment, or alternatively, water may be flowed at a rate ranging from about 200 sccm to about 1000 sccm, and at a temperature ranging from about 275° C. to about 350° C. with 300° C. being used in one advantageous embodiment, and at a pressure ranging from about 1 Torr to about 10 Torr, with 3 Torr being used in one advantageous embodiment. The aluminum oxide can be deposited under physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD) with ALD being used in one advantageous embodiment. These above parameters ensures that the appropriate thickness is obtained because it is highly desirable to control the thickness of the aluminum oxide layer to reduce parasitic capacitance as much as possible.
In one embodiment, the AlxOy barrier 225 is Al2O3. To provide an effective barrier, the AlxOy barrier is deposited in a blanket fashion such that it is substantially, laterally co-extensive with the IDL over which it is deposited, excluding any wafer edge effects. Though the AlxOy barrier 225 is laterally co-extensive, it need not be a continuous layer. However, while a non-continuous AlxOy barrier 225 could provide an effective barrier to resist layer, in an advantageous embodiment, the AlxOy barrier 225 is a continuous layer.
One advantage in using the AlxOy barrier 225 of the invention is that a very thin film can be used to reduce resist poisoning as compared to much thicker layers that are presently used. The thickness of the AlxOy barrier 225 is relatively thin when compared to TEOS layers and barrier layers that are used in previous processes. For example, the thickness of the AlxOy barrier 225 may be less than about 10 nm and in another embodiment, it may range from about 2.0 nm to about 10 nm. These thicknesses can be as much as one-eighth the thickness of sacrificial TEOS layers or one-quarter the thickness of SiCO barrier layers that are currently used. In place of the AlxOy barrier 225, previous processes have used sacrificial dielectric layers deposited from tetraethyl orthosilicate (TEOS) gas to reduce resist poisoning in combination with the barrier layer 220. However, the thicknesses required to achieve this could range from 20 nm to 40 nm and to as much as 100 nm or more. These thicknesses increase the aspect ratio, which could result in filling problems as discussed above, and could also increase the overall keff of the semiconductive device.
With the use of the thinner AlxOy barrier 225, the aspect ratio of the overall stack is decreased, which reduces the risk of filling problems associated with using thicker layers as in previous processes. In addition, however, it may achieve the same or better keff as that provided by the thicker TEOS layers. For example, the keff of the overall dielectric stack containing the thicker TEOS layer may range from about 2.83 to about 2.90, whereas the keff of the much thinner AlxOy barrier 225 is less than about 3.0 and may range from about 2.81 to about 2.89 in other embodiments. Thus, an improvement in the keff can be achieved while using a much thinner material that addresses not only the parasitic capacitance but also the above-mentioned aspect ratio concerns. The use of the AlxOy barrier 225, however, does not preclude the use of the TEOS layers, particularly in those embodiments where the TEOS layers are sacrificial. Thus, both may be present in certain embodiments.
Another advantage stems from the fact that the AlxOy barrier 225 has good etch selectivity with respect to the low-k material that comprises IDL 205 and 210. It also has good etch selectivity to the barrier layer 220, which makes it useful as an etch stop or hard mask during the formation of the interconnects. For example, depending on the type of etch chemistry used, the selectivity of the AlxOy barrier 225 to IDL 205 and 210 may range from about 5 to about 20, and the selectivity of the AlxOy barrier 225 to the barrier layer 220 may range from about 10 to about 25. This allows the AlxOy barrier 225 to serve as an etch stop for the via that is formed to make contact with the underlying metal line 215 or serve has a sacrificial hard mask in forming the trench portion of a dual damascene interconnect.
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The dual damascene interconnect is completed by filling the trenches 610 and the vias 410 with a metal. Prior to the filling step, conventional metal liners, such as tantalum/tantalum nitride or titanium/titanium nitride liners (not shown), may be formed in the structures. A seed layer may also be then deposited to line the trenches 610 and vias 410. In one embodiment, the metal material may be copper, however, the use of other materials, such as aluminum or titanium, is also within the scope of the invention. Once the trenches 610 and vias 410 are filled with metal 810, the metal is then polished to remove the excess metal and remaining portions of the AlxOy barrier 225 and barrier layer 220 and expose the top surface of IDL 210, as seen in
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From the foregoing it is clear that the invention provides several advantages over conventional processes and devices. As the industry moves forward with copper interconnect structures, such as those found in damascene and dual damascene designs, it is highly desirable to make certain that parasitic capacitance is reduced as much as possible. To that end, the semiconductor industry will continue to use low-k, but highly porous, dielectric materials. However, with their use, resist poisoning will continue to occur when either the dielectric layers are treated with nitrogen or when a nitrogen-containing layer is located within the structure. Thus, the use of thin aluminum oxide barriers located between the dielectric layers will be very useful. They effectively inhibit the diffusion of nitrogen and thereby reduce the amount of nitrogen that reaches the resist. This, in turn, reduces the amount of resist poisoning. As a result, the effective product yields will remain high. Further, because a very thin layer can be used, the parasitic capacitance will be keep within acceptable levels.
Those skilled in the art to which the invention relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of the invention.