Robert Louis Hodges

Person

Lewisville, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-aligned gate and method
- Patent number 7,598,146
- Issue date Oct 6, 2009
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate and method
- Patent number 7,126,190
- Issue date Oct 24, 2006
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate and method
- Patent number 6,774,001
- Issue date Aug 10, 2004
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory masking for periphery salicidation of active regions
- Patent number 6,661,064
- Issue date Dec 9, 2003
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for memory masking for periphery salicidation of active regions
- Patent number 6,514,811
- Issue date Feb 4, 2003
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of masking for periphery salicidation of active regions
- Patent number 6,284,584
- Issue date Sep 4, 2001
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating an integrated circuit
- Patent number 6,107,194
- Issue date Aug 22, 2000
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an integrated circuit having spacer after shallow...
- Patent number 6,087,709
- Issue date Jul 11, 2000
- STMicroelectronics, Inc.
- Todd Gandy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory masking for periphery salicidation of active regions
- Patent number 6,051,864
- Issue date Apr 18, 2000
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a shallow trench isolation with thin nitride as ga...
- Patent number 6,040,233
- Issue date Mar 21, 2000
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an integrated circuit having spacer after shallow...
- Patent number 6,022,788
- Issue date Feb 8, 2000
- STMicroelectronics, Inc.
- Todd Gandy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM cell with p-channel pull-up sources connected to bit lines
- Patent number 6,011,711
- Issue date Jan 4, 2000
- STMicroelectronics, Inc.
- Robert Louis Hodges
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of forming isolated regions of oxide
- Patent number 5,977,607
- Issue date Nov 2, 1999
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation with thin nitride as gate dielectric
- Patent number 5,952,707
- Issue date Sep 14, 1999
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a dielectric in an integrated circuit
- Patent number 5,927,992
- Issue date Jul 27, 1999
- STMicroelectronics, Inc.
- Robert L. Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM memory cell design having complementary dual pass gates
- Patent number 5,831,897
- Issue date Nov 3, 1998
- STMicroelectronics, Inc.
- Robert Louis Hodges
- G11 - INFORMATION STORAGE
Information Patent Grant
Dielectric in an integrated circuit
- Patent number 5,811,865
- Issue date Sep 22, 1998
- STMicroelectronics, Inc.
- Robert L. Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned method for forming contact with zero offset to gate
- Patent number 5,793,114
- Issue date Aug 11, 1998
- SGS-Thomson Microelectronics, Inc.
- Loi N. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating planar regions in an integrated circuit
- Patent number 5,742,095
- Issue date Apr 21, 1998
- SGS-Thomson Microelectronics, Inc.
- Frank Randolph Bryant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit transistor having drain junction offset
- Patent number 5,729,036
- Issue date Mar 17, 1998
- SGS-Thomson Microelectronics, Inc.
- Frank Randolph Bryant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming isolated intra-polycrystalline silicon structure
- Patent number 5,682,052
- Issue date Oct 28, 1997
- SGS-Thomson Microelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method fabricating an integrated circuit
- Patent number 5,543,343
- Issue date Aug 6, 1996
- SGS-Thomson Microelectronics, Inc.
- Frank R. Bryant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming low resistance contacts at the junction between r...
- Patent number 5,541,455
- Issue date Jul 30, 1996
- SGS-Thomson Microelectronics, Inc.
- Robert L. Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly-buffered LOCOS process
- Patent number 5,506,440
- Issue date Apr 9, 1996
- SGS-Thomson Microelectronics, Inc.
- Che-Chia Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming isolated intra-polycrystalline silicon structures
- Patent number 5,460,983
- Issue date Oct 24, 1995
- SGS-Thomson Microelectronics, Inc.
- Robert L. Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned method for forming contact with zero offset to gate
- Patent number 5,439,846
- Issue date Aug 8, 1995
- SGS-Thomson Microelectronics, Inc.
- Loi Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming low resistance contacts at the junction between r...
- Patent number 5,432,129
- Issue date Jul 11, 1995
- SGS-Thomson Microelectronics, Inc.
- Robert L. Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Intermediate structure for forming isolated regions of oxide
- Patent number 5,420,453
- Issue date May 30, 1995
- SGS-Thomson Microelectronics, Inc.
- Robert L. Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Making integrated circuit transistor having drain junction offset
- Patent number 5,344,790
- Issue date Sep 6, 1994
- SGS-Thomson Microelectronics, Inc.
- Frank R. Bryant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming isolated regions of oxide
- Patent number 5,338,968
- Issue date Aug 16, 1994
- SGS-Thomson
- Robert Hodges
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELF-ALIGNED GATE AND METHOD
- Publication number 20060292842
- Publication date Dec 28, 2006
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned gate and method
- Publication number 20040197982
- Publication date Oct 7, 2004
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY MASKING FOR PERIPHERY SALICIDATION OF ACTIVE REGIONS
- Publication number 20030190781
- Publication date Oct 9, 2003
- SGS-Thomson Microelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with deposited oxide
- Publication number 20030136999
- Publication date Jul 24, 2003
- Robert L. Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory masking for periphery salicidation of active regions
- Publication number 20020020889
- Publication date Feb 21, 2002
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned gate and method
- Publication number 20010000920
- Publication date May 10, 2001
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS

Robert Louis Hodges

Person

Patents Grantslast 30 patents

Self-aligned gate and method

Self-aligned gate and method

Self-aligned gate and method

Memory masking for periphery salicidation of active regions

Method for memory masking for periphery salicidation of active regions

Method of masking for periphery salicidation of active regions

Method of fabricating an integrated circuit

Method of forming an integrated circuit having spacer after shallow...

Memory masking for periphery salicidation of active regions

Method of making a shallow trench isolation with thin nitride as ga...

Method of forming an integrated circuit having spacer after shallow...

SRAM cell with p-channel pull-up sources connected to bit lines

Method of forming isolated regions of oxide

Shallow trench isolation with thin nitride as gate dielectric

Method of forming a dielectric in an integrated circuit

SRAM memory cell design having complementary dual pass gates

Dielectric in an integrated circuit

Self-aligned method for forming contact with zero offset to gate

Method of fabricating planar regions in an integrated circuit

Integrated circuit transistor having drain junction offset

Method for forming isolated intra-polycrystalline silicon structure

Method fabricating an integrated circuit

Method of forming low resistance contacts at the junction between r...

Poly-buffered LOCOS process

Method for forming isolated intra-polycrystalline silicon structures

Self-aligned method for forming contact with zero offset to gate

Method of forming low resistance contacts at the junction between r...

Intermediate structure for forming isolated regions of oxide

Making integrated circuit transistor having drain junction offset

Method of forming isolated regions of oxide

Patents Applicationslast 30 patents

SELF-ALIGNED GATE AND METHOD

Self-aligned gate and method

MEMORY MASKING FOR PERIPHERY SALICIDATION OF ACTIVE REGIONS

Semiconductor device with deposited oxide

Memory masking for periphery salicidation of active regions

Self-aligned gate and method