Russell B. Segal

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Path-based floorplan analysis
- Patent number 9,754,070
- Issue date Sep 5, 2017
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shaping integrated with power network synthesis (PNS) for power gri...
- Patent number 9,460,258
- Issue date Oct 4, 2016
- Synopsys, Inc.
- David L. Peart
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Determining a set of timing paths for creating a circuit abstraction
- Patent number 9,390,222
- Issue date Jul 12, 2016
- Synopsys, Inc.
- Russell Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Path-based floorplan analysis
- Patent number 9,189,591
- Issue date Nov 17, 2015
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit partitioning and timing
- Patent number 9,026,974
- Issue date May 5, 2015
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Abstract creation
- Patent number 8,914,759
- Issue date Dec 16, 2014
- Synopsys, Inc.
- Russell Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Displaying a congestion indicator for a channel in a circuit design...
- Patent number 8,893,073
- Issue date Nov 18, 2014
- Synopsys, Inc.
- Balkrishna R. Rashingkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing locations of pins for blocks in a hierarchical physical...
- Patent number 7,114,142
- Issue date Sep 26, 2006
- Magam Design Automoation, Inc.
- Russell Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit models having associated timing exception inform...
- Patent number 6,678,644
- Issue date Jan 13, 2004
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for circuit design top level and block optimization
- Patent number 6,496,972
- Issue date Dec 17, 2002
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit models having associated timing exception inform...
- Patent number 6,438,731
- Issue date Aug 20, 2002
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for irregular datapath placement in a datapath...
- Patent number 6,317,863
- Issue date Nov 13, 2001
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extracting accurate and efficient timing models of latch-based designs
- Patent number 6,023,568
- Issue date Feb 8, 2000
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for processing a hardware independent user description to ge...
- Patent number 5,953,235
- Issue date Sep 14, 1999
- Synopsys, Inc.
- Brent L. Gregory
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extracting accurate and efficient timing models of latch-based designs
- Patent number 5,790,830
- Issue date Aug 4, 1998
- Synopsys, Incorporated
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating a logic circuit from a hardware independent u...
- Patent number 5,748,488
- Issue date May 5, 1998
- Synopsys, Inc.
- Brent L. Gregory
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating a logic circuit from a hardware independent u...
- Patent number 5,737,574
- Issue date Apr 7, 1998
- Synopsys, Inc.
- Brent L. Gregory
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for pre-processing a hardware independent description of a l...
- Patent number 5,691,911
- Issue date Nov 25, 1997
- Synopsys, Inc.
- Brent L. Gregory
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesizer for generating a logic network using a hardware indepen...
- Patent number 5,680,318
- Issue date Oct 21, 1997
- Synopsys Inc.
- Brent L. Gregory
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for processing a hardware independent user description to ge...
- Patent number 5,661,661
- Issue date Aug 26, 1997
- Synopsys, Inc.
- Brent L. Gregory
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesizer for generating a logic network using a hardware indepen...
- Patent number 5,581,781
- Issue date Dec 3, 1996
- Synopsys, Inc.
- Brent L. Gregory
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for converting a hardware independent user description of a...
- Patent number 5,530,841
- Issue date Jun 25, 1996
- Synopsys, Inc.
- Brent L. Gregory
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PATH-BASED FLOORPLAN ANALYSIS
- Publication number 20160042115
- Publication date Feb 11, 2016
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PATH-BASED FLOORPLAN ANALYSIS
- Publication number 20150121328
- Publication date Apr 30, 2015
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING A SET OF TIMING PATHS FOR CREATING A CIRCUIT ABSTRACTION
- Publication number 20150026655
- Publication date Jan 22, 2015
- Synopsys, Inc.
- Russell Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ABSTRACT CREATION
- Publication number 20140189624
- Publication date Jul 3, 2014
- Synopsys, Inc.
- Russell Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISPLAYING A CONGESTION INDICATOR FOR A CHANNEL IN A CIRCUIT DESIGN...
- Publication number 20140189617
- Publication date Jul 3, 2014
- Synopsys, Inc.
- Balkrishna R. Rashingkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WHAT-IF PARTITIONING AND TIMING
- Publication number 20140181776
- Publication date Jun 26, 2014
- Synopsys, Inc.
- Russell B. Segal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHAPING INTEGRATED WITH POWER NETWORK SYNTHESIS (PNS) FOR POWER GRI...
- Publication number 20140181773
- Publication date Jun 26, 2014
- Synopsys, Inc.
- David L. Peart
- G06 - COMPUTING CALCULATING COUNTING

Russell B. Segal

Person

Patents Grantslast 30 patents

Path-based floorplan analysis

Shaping integrated with power network synthesis (PNS) for power gri...

Determining a set of timing paths for creating a circuit abstraction

Path-based floorplan analysis

Semiconductor integrated circuit partitioning and timing

Abstract creation

Displaying a congestion indicator for a channel in a circuit design...

Optimizing locations of pins for blocks in a hierarchical physical...

Integrated circuit models having associated timing exception inform...

Method and system for circuit design top level and block optimization

Integrated circuit models having associated timing exception inform...

Method and apparatus for irregular datapath placement in a datapath...

Extracting accurate and efficient timing models of latch-based designs

Method for processing a hardware independent user description to ge...

Extracting accurate and efficient timing models of latch-based designs

Method for generating a logic circuit from a hardware independent u...

Method for generating a logic circuit from a hardware independent u...

Method for pre-processing a hardware independent description of a l...

Synthesizer for generating a logic network using a hardware indepen...

Method for processing a hardware independent user description to ge...

Synthesizer for generating a logic network using a hardware indepen...

Method for converting a hardware independent user description of a...

Patents Applicationslast 30 patents

PATH-BASED FLOORPLAN ANALYSIS

PATH-BASED FLOORPLAN ANALYSIS

DETERMINING A SET OF TIMING PATHS FOR CREATING A CIRCUIT ABSTRACTION

ABSTRACT CREATION

DISPLAYING A CONGESTION INDICATOR FOR A CHANNEL IN A CIRCUIT DESIGN...

WHAT-IF PARTITIONING AND TIMING

SHAPING INTEGRATED WITH POWER NETWORK SYNTHESIS (PNS) FOR POWER GRI...