Shye Lin Wu

Person

Hsinchu County, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming an N channel and P channel finfet device on the s...
- Patent number 7,187,046
- Issue date Mar 6, 2007
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chung-Cheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an N channel and P channel FINFET device on the s...
- Patent number 6,770,516
- Issue date Aug 3, 2004
- Taiwan Semiconductor Manufacturing Company
- Chung Cheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-short channel NMOSFETS with self-aligned silicide contact
- Patent number 6,649,308
- Issue date Nov 18, 2003
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating three dimensional CMOSFET devices for an embe...
- Patent number 6,569,729
- Issue date May 27, 2003
- Taiwan Semiconductor Manufacturing Company
- Chung-Cheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating MOSFETs with a recessed self-aligned silicid...
- Patent number 6,555,438
- Issue date Apr 29, 2003
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming MOSFET with buried contact and air-gap gate struc...
- Patent number 6,548,362
- Issue date Apr 15, 2003
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating ultra short channel PMOSFET with buried sour...
- Patent number 6,432,785
- Issue date Aug 13, 2002
- Texas Instruments-Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming trench isolation regions
- Patent number 6,358,818
- Issue date Mar 19, 2002
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress-free shallow trench isolation
- Patent number 6,355,540
- Issue date Mar 12, 2002
- Acer Semicondutor Manufacturing Inc.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating MOSFETS with a recessed self-aligned silicid...
- Patent number 6,348,390
- Issue date Feb 19, 2002
- Acer Semiconductor Manufacturing Corp.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming MOSFET with an elevated source/drain
- Patent number 6,342,422
- Issue date Jan 29, 2002
- TSMC-Acer Semiconductor Manufacturing Company
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fipos method of forming SOI CMOS structure
- Patent number 6,331,456
- Issue date Dec 18, 2001
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a ragged polysilcon crown-shaped capacitor for a...
- Patent number 6,329,264
- Issue date Dec 11, 2001
- TSMC Acer Semiconductor Manufacturing Inc.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate deep sub-μm CMOSFETs
- Patent number 6,323,094
- Issue date Nov 27, 2001
- TSMC Acer Semiconductor Manufacturing Inc.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming high density and low power flash memories with a...
- Patent number 6,316,316
- Issue date Nov 13, 2001
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming self-aligned planarization twin-well by using few...
- Patent number 6,303,417
- Issue date Oct 16, 2001
- TSMC-Acer Semiconductor Manufacturing Corp.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET with an elevated source/drain
- Patent number 6,294,797
- Issue date Sep 25, 2001
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating CMOS transistors with self-aligned planarizat...
- Patent number 6,294,416
- Issue date Sep 25, 2001
- Texas Instruments-Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process to fabricate ultra-short channel MOSFETs with self-aligned...
- Patent number 6,284,612
- Issue date Sep 4, 2001
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flower-like capacitor structure for a memory cell
- Patent number 6,281,542
- Issue date Aug 28, 2001
- TSMC-Acer Semiconductor Manufacturing Corp.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a ragged polysilicon crown-shaped capacitor for...
- Patent number 6,274,428
- Issue date Aug 14, 2001
- Acer Semiconductor Manufacturing Inc.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a DRAM cell with a ragged polysilicon crown-shap...
- Patent number 6,268,245
- Issue date Jul 31, 2001
- Acer Semiconductor Manufacturing Inc.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a DRAM capacitor with porous storage node and ru...
- Patent number 6,265,263
- Issue date Jul 24, 2001
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate deep sub-μm CMOSFETs
- Patent number 6,265,259
- Issue date Jul 24, 2001
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density flash memories with high capacitive-couping ratio and...
- Patent number 6,259,130
- Issue date Jul 10, 2001
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming high density buried bit line flash EEPROM memory...
- Patent number 6,255,167
- Issue date Jul 3, 2001
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench DRAM cells with self-aligned field plate
- Patent number 6,255,682
- Issue date Jul 3, 2001
- Acer Inc.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating high-density and high-speed nand-type mask roms
- Patent number 6,251,731
- Issue date Jun 26, 2001
- Acer Semiconductor Manufacturing, Inc.
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating deep-shallow trench isolation
- Patent number 6,214,696
- Issue date Apr 10, 2001
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS process for forming planarized twin wells
- Patent number 6,211,002
- Issue date Apr 3, 2001
- Texas Instruments - Acer Incorporated
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method of forming an N channel and P channel finfet device on the s...
- Publication number 20040195628
- Publication date Oct 7, 2004
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Chung-Cheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming an N channel and P channel FINFET device on the s...
- Publication number 20040048424
- Publication date Mar 11, 2004
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Chung Cheng Wu
- H01 - BASIC ELECTRIC ELEMENTS

Shye Lin Wu

Person

Patents Grantslast 30 patents

Method of forming an N channel and P channel finfet device on the s...

Method of forming an N channel and P channel FINFET device on the s...

Ultra-short channel NMOSFETS with self-aligned silicide contact

Method of fabricating three dimensional CMOSFET devices for an embe...

Method for fabricating MOSFETs with a recessed self-aligned silicid...

Method of forming MOSFET with buried contact and air-gap gate struc...

Method for fabricating ultra short channel PMOSFET with buried sour...

Method for forming trench isolation regions

Stress-free shallow trench isolation

Method for fabricating MOSFETS with a recessed self-aligned silicid...

Method for forming MOSFET with an elevated source/drain

Fipos method of forming SOI CMOS structure

Method for forming a ragged polysilcon crown-shaped capacitor for a...

Method to fabricate deep sub-&#x03BC;m CMOSFETs

Method of forming high density and low power flash memories with a...

Method of forming self-aligned planarization twin-well by using few...

MOSFET with an elevated source/drain

Method of fabricating CMOS transistors with self-aligned planarizat...

Process to fabricate ultra-short channel MOSFETs with self-aligned...

Flower-like capacitor structure for a memory cell

Method for forming a ragged polysilicon crown-shaped capacitor for...

Method for forming a DRAM cell with a ragged polysilicon crown-shap...

Method for forming a DRAM capacitor with porous storage node and ru...

Method to fabricate deep sub-&#x03BC;m CMOSFETs

High density flash memories with high capacitive-couping ratio and...

Method of forming high density buried bit line flash EEPROM memory...

Trench DRAM cells with self-aligned field plate

Method for fabricating high-density and high-speed nand-type mask roms

Method of fabricating deep-shallow trench isolation

CMOS process for forming planarized twin wells

Patents Applicationslast 30 patents

Method of forming an N channel and P channel finfet device on the s...

Method of forming an N channel and P channel FINFET device on the s...

Method to fabricate deep sub-μm CMOSFETs

Method to fabricate deep sub-μm CMOSFETs