Theo J. Powell

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Built-in self-test arrangement for integrated circuit memory devices
- Patent number 7,328,388
- Issue date Feb 5, 2008
- Texas Instruments Incorporated
- Kuong Hua Hii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test arrangement for integrated circuit memory devices
- Patent number 7,278,078
- Issue date Oct 2, 2007
- Texas Instruments Incorporated
- Kuong Hua Hii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Array fault testing approach for TCAMs
- Patent number 7,274,581
- Issue date Sep 25, 2007
- Texas Instruments Incorporated
- Theo Jay Powell
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-test arrangement for integrated circuit memory devices
- Patent number 6,801,461
- Issue date Oct 5, 2004
- Texas Instruments Incorporated
- Kuong Hua Hii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test arrangement for integrated circuit memory devices
- Patent number 6,353,563
- Issue date Mar 5, 2002
- Texas Instruments Incorporated
- Kuong Hua Hii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test enable control for built-in self-test
- Patent number 6,014,336
- Issue date Jan 11, 2000
- Texas Instruments Incorporated
- Theo J. Powell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ROM embedded mask release number for built-in self-test
- Patent number 5,959,912
- Issue date Sep 28, 1999
- Texas Instruments Incorporated
- Theo J. Powell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data invert jump instruction test for built-in self-test
- Patent number 5,953,272
- Issue date Sep 14, 1999
- Texas Instruments Incorporated
- Theo J. Powell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit memory device having built-in self test circuit...
- Patent number 5,936,900
- Issue date Aug 10, 1999
- Texas Instruments Incorporated
- Kuong Hua Hii
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for subarray testing in dynamic random access...
- Patent number 5,923,599
- Issue date Jul 13, 1999
- Texas Instruments Incorporated
- Kuong H. Hii
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-test arrangement for integrated circuit memory devices
- Patent number 5,883,843
- Issue date Mar 16, 1999
- Texas Instruments Incorporated
- Kuong Hua Hii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Internal/external clock option for built-in self test
- Patent number 5,875,153
- Issue date Feb 23, 1999
- Texas Instruments Incorporated
- Kuong Hua Hii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for structurally testing integrated circuit devices
- Patent number 5,694,402
- Issue date Dec 2, 1997
- Texas Instruments Incorporated
- Kenneth M. Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test circuit and scan tested logic device with isolated data lines...
- Patent number 5,032,783
- Issue date Jul 16, 1991
- Texas Instruments Incorporated
- Yin-Chao Hwang
- G01 - MEASURING TESTING
Information Patent Grant
Value-strength based test pattern generator and process
- Patent number 5,012,471
- Issue date Apr 30, 1991
- Texas Instruments Incorporated
- Theo J. Powell
- G01 - MEASURING TESTING
Information Patent Grant
Distributed pseudo random sequence control with universal polynomia...
- Patent number 4,870,346
- Issue date Sep 26, 1989
- Texas Instruments Incorporated
- Marc R. Mydill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioned scan-testing system
- Patent number 4,710,931
- Issue date Dec 1, 1987
- Texas Instruments Incorporated
- Jeffrey D. Bellay
- G01 - MEASURING TESTING
Information Patent Grant
Parallel/serial scan system for testing logic circuits
- Patent number 4,710,933
- Issue date Dec 1, 1987
- Texas Instruments Incorporated
- Theo J. Powell
- G01 - MEASURING TESTING
Information Patent Grant
Modularized scan path for serially tested logic circuit
- Patent number 4,701,921
- Issue date Oct 20, 1987
- Texas Instruments Incorporated
- Theo J. Powell
- G01 - MEASURING TESTING
Information Patent Grant
Transparent shift register latch for isolating peripheral ports dur...
- Patent number 4,698,588
- Issue date Oct 6, 1987
- Texas Instruments Incorporated
- Yin-Chao Hwang
- G01 - MEASURING TESTING
Information Patent Grant
Architecture and method for testing VLSI processors
- Patent number 4,597,080
- Issue date Jun 24, 1986
- Texas Instruments Incorporated
- Satish M. Thatte
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Built-in self-test arrangement for integrated circuit memory devices
- Publication number 20060242521
- Publication date Oct 26, 2006
- Kuong Hua Hii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method to test memories that operate at twice their nominal bandwidth
- Publication number 20050144525
- Publication date Jun 30, 2005
- Keerthinarayan Heragu
- G11 - INFORMATION STORAGE
Information Patent Application
Built-in self-test arrangement for integrated circuit memory devices
- Publication number 20050022084
- Publication date Jan 27, 2005
- Kuong Hua Hii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Built-in self-test arrangement for integrated circuit memory devices
- Publication number 20020089887
- Publication date Jul 11, 2002
- Kuong Hua Hii
- G01 - MEASURING TESTING
Information Patent Application
Built-in self-test arrangement for integrated circuit memory devices
- Publication number 20020071325
- Publication date Jun 13, 2002
- Kuong Hua Hii
- G01 - MEASURING TESTING

Theo J. Powell

Person

Patents Grantslast 30 patents

Built-in self-test arrangement for integrated circuit memory devices

Built-in self-test arrangement for integrated circuit memory devices

Array fault testing approach for TCAMs

Built-in self-test arrangement for integrated circuit memory devices

Built-in self-test arrangement for integrated circuit memory devices

Test enable control for built-in self-test

ROM embedded mask release number for built-in self-test

Data invert jump instruction test for built-in self-test

Integrated circuit memory device having built-in self test circuit...

Apparatus and method for subarray testing in dynamic random access...

Built-in self-test arrangement for integrated circuit memory devices

Internal/external clock option for built-in self test

System and method for structurally testing integrated circuit devices

Test circuit and scan tested logic device with isolated data lines...

Value-strength based test pattern generator and process

Distributed pseudo random sequence control with universal polynomia...

Partitioned scan-testing system

Parallel/serial scan system for testing logic circuits

Modularized scan path for serially tested logic circuit

Transparent shift register latch for isolating peripheral ports dur...

Architecture and method for testing VLSI processors

Patents Applicationslast 30 patents

Built-in self-test arrangement for integrated circuit memory devices

Method to test memories that operate at twice their nominal bandwidth

Built-in self-test arrangement for integrated circuit memory devices

Built-in self-test arrangement for integrated circuit memory devices

Built-in self-test arrangement for integrated circuit memory devices