Ulrike Gruening

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Field-shield-trench isolation for gigabit DRAMs
- Patent number 6,762,447
- Issue date Jul 13, 2004
- Infineon Technologies North America Corp.
- Jack A. Mandelman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structures and manufacturing methods
- Patent number 6,740,555
- Issue date May 25, 2004
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structures and manufacturing methods
- Patent number 6,605,860
- Issue date Aug 12, 2003
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned buried strap for vertical transistors
- Patent number 6,555,862
- Issue date Apr 29, 2003
- Infineon Technologies AG
- Jack A. Mandelman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for buried-strap self-aligned to deep storage trench
- Patent number 6,451,648
- Issue date Sep 17, 2002
- International Business Machines Corporation
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing a crystal axis-aligned vertical side wall...
- Patent number 6,426,251
- Issue date Jul 30, 2002
- International Business Machines Corporation
- Gary Bronner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of 5F2 cell with partially vertical transistor and gate c...
- Patent number 6,399,978
- Issue date Jun 4, 2002
- International Business Machines Corp.
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a uniform gate oxide of a vertical transistor
- Patent number 6,348,388
- Issue date Feb 19, 2002
- International Business Machines Corporation
- Johnathan E. Faltermeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of dummy poly spacers and divot fill techniques for DT-aligned...
- Patent number 6,331,459
- Issue date Dec 18, 2001
- Infineon Technologies AG
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing impact of coupling noise in multi-level bitline architecture
- Patent number 6,327,170
- Issue date Dec 4, 2001
- Infineon Technologies AG
- Gerhard Mueller
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for fabricating transistors
- Patent number 6,323,103
- Issue date Nov 27, 2001
- Siemens Aktiengesellschaft
- Rajesh Rengarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Crystal-axis-aligned vertical side wall device
- Patent number 6,320,215
- Issue date Nov 20, 2001
- International Business Machines Corporation
- Gary Bronner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced impact from coupling noise in diagonal bitline architectures
- Patent number 6,320,780
- Issue date Nov 20, 2001
- Infineon Technologies North America Corp.
- Gerhard Mueller
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor structure and manufacturing methods
- Patent number 6,319,788
- Issue date Nov 20, 2001
- Infineon Technologies North America Corp.
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Locally folded split level bitline wiring
- Patent number 6,291,335
- Issue date Sep 18, 2001
- Infineon Technologies AG
- Rainer Florian Schnabel
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for manufacture of trench DRAM capacitor buried plates
- Patent number 6,271,142
- Issue date Aug 7, 2001
- International Business Machines Corporation
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell structure and fabrication
- Patent number 6,265,742
- Issue date Jul 24, 2001
- Siemens Aktiengesellschaft
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memory
- Patent number 6,255,683
- Issue date Jul 3, 2001
- Infineon Technologies AG
- Carl Radens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of manufacturing a vertical dynamic random access memory de...
- Patent number 6,255,158
- Issue date Jul 3, 2001
- International Business Machines Corporation
- Toshiharu Furukawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid 5F2 cell layout for buried surface strap aligned to vertical...
- Patent number 6,229,173
- Issue date May 8, 2001
- International Business Machines Corporation
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memory
- Patent number 6,204,140
- Issue date Mar 20, 2001
- Infineon Technologies North America Corp.
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sensing of memory cell via a plateline
- Patent number 6,201,730
- Issue date Mar 13, 2001
- Infineon Technologies North America Corp.
- Johann Alsmeier
- G11 - INFORMATION STORAGE
Information Patent Grant
Quantum conductive recrystallization barrier layers
- Patent number 6,194,736
- Issue date Feb 27, 2001
- International Business Machines Corporation
- Susan E. Chaloux
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-resistance salicide fill for trench capacitors
- Patent number 6,194,755
- Issue date Feb 27, 2001
- International Business Machines Corporation
- Jeffrey P. Gambino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of 5F2 cell with partially vertical transistor and gate c...
- Patent number 6,190,971
- Issue date Feb 20, 2001
- International Business Machines Corporation
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing impact of coupling noise
- Patent number 6,188,598
- Issue date Feb 13, 2001
- Infineon Technologies North America Corp.
- Gerhard Mueller
- G11 - INFORMATION STORAGE
Information Patent Grant
Capacitor trench-top dielectric for self-aligned device isolation
- Patent number 6,184,107
- Issue date Feb 6, 2001
- International Business Machines Corp.
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of controlled trench top isolation layers for vertical tr...
- Patent number 6,184,091
- Issue date Feb 6, 2001
- Infineon Technologies North America Corp.
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of controlled trench top isolation layers for vertical tr...
- Patent number 6,177,698
- Issue date Jan 23, 2001
- Infineon Technologies North America Corp.
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical DRAM cell with wordline self-aligned to storage trench
- Patent number 6,153,902
- Issue date Nov 28, 2000
- International Business Machines Corporation
- Toshiharu Furukawa
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor structures and manufacturing methods
- Publication number 20040209474
- Publication date Oct 21, 2004
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of 5F2 cell with partially vertical transistor and gate c...
- Publication number 20020004290
- Publication date Jan 10, 2002
- Ulrike Gruening
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for manufacturing a crystal axis-aligned vertical side wall...
- Publication number 20010038113
- Publication date Nov 8, 2001
- Gary Bronner
- H01 - BASIC ELECTRIC ELEMENTS

Ulrike Gruening

Person

Patents Grantslast 30 patents

Field-shield-trench isolation for gigabit DRAMs

Semiconductor structures and manufacturing methods

Semiconductor structures and manufacturing methods

Self-aligned buried strap for vertical transistors

Process for buried-strap self-aligned to deep storage trench

Process for manufacturing a crystal axis-aligned vertical side wall...

Formation of 5F2 cell with partially vertical transistor and gate c...

Process for fabricating a uniform gate oxide of a vertical transistor

Use of dummy poly spacers and divot fill techniques for DT-aligned...

Reducing impact of coupling noise in multi-level bitline architecture

Method for fabricating transistors

Crystal-axis-aligned vertical side wall device

Reduced impact from coupling noise in diagonal bitline architectures

Semiconductor structure and manufacturing methods

Locally folded split level bitline wiring

Process for manufacture of trench DRAM capacitor buried plates

Memory cell structure and fabrication

Dynamic random access memory

Process of manufacturing a vertical dynamic random access memory de...

Hybrid 5F2 cell layout for buried surface strap aligned to vertical...

Dynamic random access memory

Sensing of memory cell via a plateline

Quantum conductive recrystallization barrier layers

Low-resistance salicide fill for trench capacitors

Formation of 5F2 cell with partially vertical transistor and gate c...

Reducing impact of coupling noise

Capacitor trench-top dielectric for self-aligned device isolation

Formation of controlled trench top isolation layers for vertical tr...

Formation of controlled trench top isolation layers for vertical tr...

Vertical DRAM cell with wordline self-aligned to storage trench

Patents Applicationslast 30 patents

Semiconductor structures and manufacturing methods

Formation of 5F2 cell with partially vertical transistor and gate c...

Process for manufacturing a crystal axis-aligned vertical side wall...