Valerie L. Lines

Person

Ottawa, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Pre-charge voltage generation and power saving modes
- Patent number 9,196,319
- Issue date Nov 24, 2015
- Conversant Intellectual Property Management Inc.
- Valerie Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-charge voltage generation and power saving modes
- Patent number 8,699,288
- Issue date Apr 15, 2014
- Mosaid Technologies Incorporated
- Valerie Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-charge voltage generation and power saving modes
- Patent number 8,279,685
- Issue date Oct 2, 2012
- Mosaid Technologies Incorporated
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power memory architecture
- Patent number 8,149,634
- Issue date Apr 3, 2012
- MOSAID Technologies Incorporated
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic memory word line driver scheme
- Patent number 8,023,314
- Issue date Sep 20, 2011
- MOSAID Technologies Incorporated
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-charge voltage generation and power saving modes
- Patent number 7,903,477
- Issue date Mar 8, 2011
- Mosaid Technologies Incorporated
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power memory architecture
- Patent number 7,555,659
- Issue date Jun 30, 2009
- Mosaid Technologies Incorporated
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage level shifter circuit
- Patent number 7,541,837
- Issue date Jun 2, 2009
- MOSAID Technologies Incorporated
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic memory word line driver scheme
- Patent number 7,535,749
- Issue date May 19, 2009
- Mosaid Technologies, Inc.
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Matchline sense circuit and method
- Patent number 7,382,638
- Issue date Jun 3, 2008
- Mosaid Technologies Incorporated
- Stanley Jeh-Chun Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage level shifter circuit
- Patent number 7,312,636
- Issue date Dec 25, 2007
- Mosaid Technologies Incorporated
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Matchline sense circuit and method
- Patent number 7,251,148
- Issue date Jul 31, 2007
- MOSAID Technologies Incorporated
- Stanley Jeh-Chun Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Priority encoder circuit and method
- Patent number 7,043,601
- Issue date May 9, 2006
- Mosaid Technologies Incorporated
- Robert McKenzie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic memory word line driver scheme
- Patent number 7,038,937
- Issue date May 2, 2006
- Mosaid Technologies, Inc.
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Matchline sense circuit and method
- Patent number 6,987,682
- Issue date Jan 17, 2006
- Mosaid Technologies Incorporated
- Stanley Jeh-Chun Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM boosted voltage supply
- Patent number 6,980,448
- Issue date Dec 27, 2005
- Mosaid Technologies, Inc.
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Priority encoder circuit and method
- Patent number 6,693,814
- Issue date Feb 17, 2004
- Mosaid Technologies Incorporated
- Robert McKenzie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for multiple match detection in content addressa...
- Patent number 6,667,924
- Issue date Dec 23, 2003
- Mosaid Technologies Incorporated
- Abdullah Ahmed
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic random access memory boosted voltage supply
- Patent number 6,614,705
- Issue date Sep 2, 2003
- Mosaid Technologies, Inc.
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline precharge
- Patent number 6,608,788
- Issue date Aug 19, 2003
- Mosaid Technologies Incorporated
- Peter P Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic memory word line driver scheme
- Patent number 6,603,703
- Issue date Aug 5, 2003
- Mosaid Technologies, Inc.
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Boosted voltage supply
- Patent number 6,580,654
- Issue date Jun 17, 2003
- Mosaid Technologies, Inc.
- Richard C. Foss
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for multiple match detection in content addressable memories
- Patent number 6,538,947
- Issue date Mar 25, 2003
- Mosaid Technologies Incorporated
- Abdullah Ahmed
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline precharge
- Patent number 6,504,775
- Issue date Jan 7, 2003
- Mosaid Technologies Incorporated Kanata
- Peter P Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic content addressable memory cell
- Patent number 6,483,733
- Issue date Nov 19, 2002
- Mosaid Technologies Incorporated
- Valerie Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic content addressable memory cell
- Patent number 6,320,777
- Issue date Nov 20, 2001
- Mosaid Technologies Incorporated
- Valerie Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for multiple match detection in content addressa...
- Patent number 6,307,798
- Issue date Oct 23, 2001
- Mosaid Technologies Incorporated
- Abdullah Ahmed
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic memory word line driver scheme
- Patent number 6,278,640
- Issue date Aug 21, 2001
- Mosaid Technologies Incorporated
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage boosted word line supply charge pump and regulator for...
- Patent number 6,236,581
- Issue date May 22, 2001
- Mosaid Technologies Incorporated
- Richard C. Foss
- G05 - CONTROLLING REGULATING
Information Patent Grant
Bi-directional data bus scheme with optimized read and write charac...
- Patent number 6,134,153
- Issue date Oct 17, 2000
- Mosaid Technologies Incorporated
- Valerie Lines
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES
- Publication number 20140198587
- Publication date Jul 17, 2014
- Mosaid Technlogies Incorporated
- Valerie Lines
- G11 - INFORMATION STORAGE
Information Patent Application
Pre-Charge Voltage Generation and Power Saving Modes
- Publication number 20120320695
- Publication date Dec 20, 2012
- MOSAID TECHNOLOGIES INCORPORATED
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Application
PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES
- Publication number 20110122719
- Publication date May 26, 2011
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC MEMORY WORD LINE DRIVER SCHEME
- Publication number 20090237981
- Publication date Sep 24, 2009
- MOSAID Technologies, Inc.
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER MEMORY ARCHITECTURE
- Publication number 20090231931
- Publication date Sep 17, 2009
- MOSAID TECHNOLOGIES INCORPORATED
- Valerie L. LINES
- G11 - INFORMATION STORAGE
Information Patent Application
PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES
- Publication number 20090219767
- Publication date Sep 3, 2009
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Application
VOLTAGE LEVEL SHIFTER CIRCUIT
- Publication number 20080054941
- Publication date Mar 6, 2008
- MOSAID Technologies Incorporated
- Valerie L. Lines
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MATCHLINE SENSE CIRCUIT AND METHOD
- Publication number 20070258277
- Publication date Nov 8, 2007
- Mosaid Technologies Incorporated
- Stanley Jeh-Chun Ma
- G11 - INFORMATION STORAGE
Information Patent Application
Low power memory architecture
- Publication number 20070201295
- Publication date Aug 30, 2007
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM boosted voltage supply
- Publication number 20070200611
- Publication date Aug 30, 2007
- Richard C. Foss
- G05 - CONTROLLING REGULATING
Information Patent Application
Voltage level shifter circuit
- Publication number 20070182450
- Publication date Aug 9, 2007
- Mosaid Technologies Incorporated
- Valerie L. Lines
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dynamic memory word line driver scheme
- Publication number 20070025137
- Publication date Feb 1, 2007
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Application
Matchline sense circuit and method
- Publication number 20060083041
- Publication date Apr 20, 2006
- Stanley Jeh-Chun Ma
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM boosted voltage supply
- Publication number 20060028899
- Publication date Feb 9, 2006
- MOSAID Technologies Incorporated
- Richard C. Foss
- G05 - CONTROLLING REGULATING
Information Patent Application
Dynamic memory word line driver scheme
- Publication number 20050018523
- Publication date Jan 27, 2005
- MOSAID Technologies, Incorporated
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Application
Priority encoder circuit and method
- Publication number 20040139275
- Publication date Jul 15, 2004
- Robert McKenzie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic memory word line driver scheme
- Publication number 20040037155
- Publication date Feb 26, 2004
- MOSAID Technologies, Incorporated
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Application
Boosted voltage supply
- Publication number 20040036456
- Publication date Feb 26, 2004
- MOSAID Technologies Incorporated
- Richard C. Foss
- G05 - CONTROLLING REGULATING
Information Patent Application
Matchline sense circuit and method
- Publication number 20030161194
- Publication date Aug 28, 2003
- Stanley Jeh-Chun Ma
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit and method for multiple match detection in content addressa...
- Publication number 20030081474
- Publication date May 1, 2003
- Abdullah Ahmed
- G11 - INFORMATION STORAGE
Information Patent Application
Bitline precharge
- Publication number 20030072205
- Publication date Apr 17, 2003
- Peter P. Ma
- G11 - INFORMATION STORAGE
Information Patent Application
BITLINE PRECHARGE
- Publication number 20030016580
- Publication date Jan 23, 2003
- Peter P. Ma
- G11 - INFORMATION STORAGE
Information Patent Application
Boosted voltage supply
- Publication number 20020075706
- Publication date Jun 20, 2002
- MOSAID Technologies Incorporated
- Richard C. Foss
- G05 - CONTROLLING REGULATING
Information Patent Application
Dynamic content addressable memory cell
- Publication number 20020044475
- Publication date Apr 18, 2002
- Valerie Lines
- G11 - INFORMATION STORAGE
Information Patent Application
Priority encoder circuit and method
- Publication number 20020042865
- Publication date Apr 11, 2002
- Robert N. McKenzie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for multiple match detection in content addressable memories
- Publication number 20020009009
- Publication date Jan 24, 2002
- Abdullah Ahmed
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic memory word line driver scheme
- Publication number 20010046162
- Publication date Nov 29, 2001
- MOSAID Technologies Incorporated Kanata
- Valerie L. Lines
- G11 - INFORMATION STORAGE
Information Patent Application
High voltage boosted word line supply charge pump and regulator for...
- Publication number 20010009518
- Publication date Jul 26, 2001
- MOSAID Technologies Incorporated
- Richard C. Foss
- G05 - CONTROLLING REGULATING

Valerie L. Lines

Person

Patents Grantslast 30 patents

Pre-charge voltage generation and power saving modes

Pre-charge voltage generation and power saving modes

Pre-charge voltage generation and power saving modes

Low power memory architecture

Dynamic memory word line driver scheme

Pre-charge voltage generation and power saving modes

Low power memory architecture

Voltage level shifter circuit

Dynamic memory word line driver scheme

Matchline sense circuit and method

Voltage level shifter circuit

Matchline sense circuit and method

Priority encoder circuit and method

Dynamic memory word line driver scheme

Matchline sense circuit and method

DRAM boosted voltage supply

Priority encoder circuit and method

Circuit and method for multiple match detection in content addressa...

Dynamic random access memory boosted voltage supply

Bitline precharge

Dynamic memory word line driver scheme

Boosted voltage supply

Method for multiple match detection in content addressable memories

Bitline precharge

Dynamic content addressable memory cell

Dynamic content addressable memory cell

Circuit and method for multiple match detection in content addressa...

Dynamic memory word line driver scheme

High voltage boosted word line supply charge pump and regulator for...

Bi-directional data bus scheme with optimized read and write charac...

Patents Applicationslast 30 patents

PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES

Pre-Charge Voltage Generation and Power Saving Modes

PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES

DYNAMIC MEMORY WORD LINE DRIVER SCHEME

LOW POWER MEMORY ARCHITECTURE

PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES

VOLTAGE LEVEL SHIFTER CIRCUIT

MATCHLINE SENSE CIRCUIT AND METHOD

Low power memory architecture

DRAM boosted voltage supply

Voltage level shifter circuit

Dynamic memory word line driver scheme

Matchline sense circuit and method

DRAM boosted voltage supply

Dynamic memory word line driver scheme

Priority encoder circuit and method

Dynamic memory word line driver scheme

Boosted voltage supply

Matchline sense circuit and method

Circuit and method for multiple match detection in content addressa...

Bitline precharge

BITLINE PRECHARGE

Boosted voltage supply

Dynamic content addressable memory cell

Priority encoder circuit and method

Method for multiple match detection in content addressable memories

Dynamic memory word line driver scheme

High voltage boosted word line supply charge pump and regulator for...