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Arrangements for synchronising receiver with transmitter
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H04L7/00
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Parent Industries
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ELECTRICITY
H04
Electric communication
H04L
TRANSMISSION OF DIGITAL INFORMATION
Current Industry
H04L7/00
Arrangements for synchronising receiver with transmitter
Sub Industries
H04L7/0004
Initialisation of the receiver
H04L7/0008
Synchronisation information channels
H04L7/0012
by comparing receiver clock with transmitter clock
H04L7/0016
correction of synchronization errors
H04L7/002
correction by interpolation
H04L7/0025
interpolation of clock signal
H04L7/0029
interpolation of received data signal
H04L7/0033
Correction by delay
H04L7/0037
Delay of clock signal
H04L7/0041
Delay of data signal
H04L7/0045
Correction by a latch cascade
H04L7/005
Correction by an elastic buffer
H04L7/0054
Detection of the synchronisation error by features other than the received signal transition
H04L7/0058
detection of error based on equalizer tap values
H04L7/0062
detection of error based on data decision error
H04L7/0066
detection of error based on transmission code rule
H04L7/007
detection of error based on maximum signal power
H04L7/0075
with photonic or optical means
H04L7/0079
Receiver details
H04L7/0083
taking measures against momentary loss of synchronisation
H04L7/0087
Preprocessing of received signal for synchronisation
H04L7/0091
Transmitter details
H04L7/0095
with mechanical means
H04L7/02
Speed or phase control by the received code signals, the signals containing no special synchronisation information
H04L7/027
extracting the synchronising or clock signal from the received signal spectrum
H04L7/0272
with squaring loop
H04L7/0274
with Costas loop
H04L7/0276
Self-sustaining
H04L7/0278
Band edge detection
H04L7/033
using the transitions of the received signal to control the phase of the synchronising-signal-generating means
H04L7/0331
with a digital phase-locked loop [PLL] processing binay samples
H04L7/0332
with an integrator-detector
H04L7/0334
Processing of samples having at least three levels
H04L7/0335
Gardner detector
H04L7/0337
Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
H04L7/0338
the correction of the phase error being performed by a feed forward loop
H04L7/04
Speed or phase control by synchronisation signals
H04L7/041
using special codes as synchronising signal
H04L7/042
Detectors therefor
H04L7/043
Pseudo-noise [PN] codes variable during transmission
H04L7/044
using a single bit
H04L7/046
using a dotting sequence
H04L7/048
using the properties of error detecting or error correcting codes
H04L7/06
the synchronisation signals differing from the information signals in amplitude, polarity, or frequency or length
H04L7/065
and superimposed by modulation
H04L7/08
the synchronisation signals recurring cyclically
H04L7/10
Arrangements for initial synchronisation
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