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H01L2224/06156

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/06156Covering only the central area of the surface to be connected

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Stacked chip-on-board module with edge connector
- Patent number 10,622,289
- Issue date Apr 14, 2020
- Tessera, Inc.
- Wael Zohni
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 9,911,706
- Issue date Mar 6, 2018
- Samsung Electronics Co., Ltd.
- Chang-hyun Cho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices with redistribution pads
- Patent number 9,859,204
- Issue date Jan 2, 2018
- Samsung Electronics Co., Ltd.
- Myeong Soon Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip package having a stacked plurality of different sized se...
- Patent number 9,761,563
- Issue date Sep 12, 2017
- Samsung Electronics Co., Ltd.
- Hyung-Lae Eun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package
- Patent number 9,735,132
- Issue date Aug 15, 2017
- ChipMOS Technologies Inc.
- Cheng-Yu Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked chip-on-board module with edge connector
- Patent number 9,735,093
- Issue date Aug 15, 2017
- Tessera, Inc.
- Wael Zohni
- G11 - INFORMATION STORAGE
Information Patent Grant
Stub minimization for assemblies without wirebonds to package subst...
- Patent number 9,679,838
- Issue date Jun 13, 2017
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple die stacking for two or more die
- Patent number 9,640,515
- Issue date May 2, 2017
- Tessera, Inc.
- Wael Zohni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die wirebond packages with elongated windows
- Patent number 9,633,975
- Issue date Apr 25, 2017
- Invensas Corporation
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple die in a face down package
- Patent number 9,466,587
- Issue date Oct 11, 2016
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple die face-down stacking for two or more die
- Patent number 9,437,579
- Issue date Sep 6, 2016
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stub minimization for multi-die wirebond assemblies with parallel w...
- Patent number 9,423,824
- Issue date Aug 23, 2016
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-chip package having a stacked plurality of different sized se...
- Patent number 9,397,034
- Issue date Jul 19, 2016
- Samsung Electronics Co., Ltd.
- Hyung-Iae Eun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stub minimization for assemblies without wirebonds to package subst...
- Patent number 9,373,565
- Issue date Jun 21, 2016
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method of manufacturing the same
- Patent number 9,373,593
- Issue date Jun 21, 2016
- Renesas Electronics Corporation
- Sadao Nakayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die wirebond packages with elongated windows
- Patent number 9,318,467
- Issue date Apr 19, 2016
- Invensas Corporation
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple die stacking for two or more die
- Patent number 9,312,244
- Issue date Apr 12, 2016
- Tessera, Inc.
- Wael Zohni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked chip-on-board module with edge connector
- Patent number 9,281,266
- Issue date Mar 8, 2016
- Tessera, Inc.
- Wael Zohni
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor assemblies with multi-level substrates and associated...
- Patent number 9,271,403
- Issue date Feb 23, 2016
- Micron Technology, Inc.
- Chin Hui Chong
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stub minimization with terminal grids offset from center of package
- Patent number 9,214,455
- Issue date Dec 15, 2015
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device with respective electrode pad rows and respect...
- Patent number 9,159,663
- Issue date Oct 13, 2015
- PS4 Luxco S.A.R.L.
- Satoshi Isa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of manufacturing the same
- Patent number 9,159,681
- Issue date Oct 13, 2015
- Renesas Electronics Corporation
- Sadao Nakayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Impedence controlled packages with metal sheet or 2-layer RDL
- Patent number 9,136,197
- Issue date Sep 15, 2015
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Expanded semiconductor chip and semiconductor device
- Patent number 9,136,219
- Issue date Sep 15, 2015
- Panasonic Corporation
- Teppei Iwase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and arrangements relating to semiconductor packages includi...
- Patent number 9,105,610
- Issue date Aug 11, 2015
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method for producing the same
- Patent number 9,093,393
- Issue date Jul 28, 2015
- J-Devices Corporation
- Toru Suda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple die face-down stacking for two or more die
- Patent number 9,013,033
- Issue date Apr 21, 2015
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple die in a face down package
- Patent number 9,000,583
- Issue date Apr 7, 2015
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple die stacking for two or more die
- Patent number 8,952,516
- Issue date Feb 10, 2015
- Tessera, Inc.
- Wael Zohni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stub minimization with terminal grids offset from center of package
- Patent number 8,917,532
- Issue date Dec 23, 2014
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR
- Publication number 20170263540
- Publication date Sep 14, 2017
- Tessera, Inc.
- Wael Zohni
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20170098628
- Publication date Apr 6, 2017
- MEDIATEK INC.
- Nai-Wei LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL W...
- Publication number 20140328016
- Publication date Nov 6, 2014
- Invensas Corporation
- Richard Dewitt Crisp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20140252613
- Publication date Sep 11, 2014
- Yoshinori IWAMOTO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIE WIREBOND PACKAGES WITH ELONGATED WINDOWS
- Publication number 20140217617
- Publication date Aug 7, 2014
- Invensas Corporation
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDI...
- Publication number 20140206141
- Publication date Jul 24, 2014
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR ASSEMBLIES WITH MULTI-LEVEL SUBSTRATES AND ASSOCIATED...
- Publication number 20140141572
- Publication date May 22, 2014
- Micron Technology, Inc.
- Chin Hui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
- Publication number 20140138852
- Publication date May 22, 2014
- J-DEVICES CORPORATION
- Toru SUDA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR
- Publication number 20140131849
- Publication date May 15, 2014
- Tessera, Inc.
- Wael Zohni
- G11 - INFORMATION STORAGE
Information Patent Application
EXPANDED SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE
- Publication number 20140124957
- Publication date May 8, 2014
- PANASONIC CORPORATION
- TEPPEI IWASE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE DIE IN A FACE DOWN PACKAGE
- Publication number 20140117516
- Publication date May 1, 2014
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20140103536
- Publication date Apr 17, 2014
- PANASONIC CORPORATION
- Kenji Yokoyama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...
- Publication number 20140103535
- Publication date Apr 17, 2014
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20140027919
- Publication date Jan 30, 2014
- RENESAS ELECTRONICS CORPORATION
- Sadao Nakayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SEMICONDUCTOR PACKAGE
- Publication number 20130292842
- Publication date Nov 7, 2013
- SK HYNIX INC.
- Seong Cheol KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR CHIP HAVING THE SAME, AND ST...
- Publication number 20130264689
- Publication date Oct 10, 2013
- SK HYNIX INC.
- Hyun Joo KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGE HAVING A STACKED PLURALITY OF DIFFERENT SIZED SE...
- Publication number 20130147044
- Publication date Jun 13, 2013
- Hyung-lae EUN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE
- Publication number 20130127062
- Publication date May 23, 2013
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE DIE STACKING FOR TWO OR MORE DIE
- Publication number 20130100616
- Publication date Apr 25, 2013
- Tessera, Inc.
- Wael Zohni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...
- Publication number 20130082375
- Publication date Apr 4, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Application
STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL W...
- Publication number 20130083583
- Publication date Apr 4, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...
- Publication number 20130082389
- Publication date Apr 4, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Application
STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...
- Publication number 20130083582
- Publication date Apr 4, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Application
STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE
- Publication number 20130083584
- Publication date Apr 4, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE DIE IN A FACE DOWN PACKAGE
- Publication number 20130043582
- Publication date Feb 21, 2013
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR ASSEMBLIES WITH MULTI-LEVEL SUBSTRATES AND ASSOCIATED...
- Publication number 20130037949
- Publication date Feb 14, 2013
- Micron Technology, Inc.
- Chin Hui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDI...
- Publication number 20120326282
- Publication date Dec 27, 2012
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPEDENCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL
- Publication number 20120313228
- Publication date Dec 13, 2012
- Tessera, Inc.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20120273971
- Publication date Nov 1, 2012
- ELPIDA MEMORY, INC.
- Sensho USAMI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR
- Publication number 20120267771
- Publication date Oct 25, 2012
- Tessera, Inc.
- Wael Zohni
- G11 - INFORMATION STORAGE

Covering only the central area of the surface to be connected

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Stacked chip-on-board module with edge connector

Semiconductor device

Semiconductor devices with redistribution pads

Multi-chip package having a stacked plurality of different sized se...

Semiconductor package

Stacked chip-on-board module with edge connector

Stub minimization for assemblies without wirebonds to package subst...

Multiple die stacking for two or more die

Multi-die wirebond packages with elongated windows

Multiple die in a face down package

Multiple die face-down stacking for two or more die

Stub minimization for multi-die wirebond assemblies with parallel w...

Multi-chip package having a stacked plurality of different sized se...

Stub minimization for assemblies without wirebonds to package subst...

Semiconductor device and method of manufacturing the same

Multi-die wirebond packages with elongated windows

Multiple die stacking for two or more die

Stacked chip-on-board module with edge connector

Semiconductor assemblies with multi-level substrates and associated...

Stub minimization with terminal grids offset from center of package

Semiconductor device with respective electrode pad rows and respect...

Semiconductor device and method of manufacturing the same

Impedence controlled packages with metal sheet or 2-layer RDL

Expanded semiconductor chip and semiconductor device

Methods and arrangements relating to semiconductor packages includi...

Semiconductor device and method for producing the same

Multiple die face-down stacking for two or more die

Multiple die in a face down package

Multiple die stacking for two or more die

Stub minimization with terminal grids offset from center of package

Patents Applicationslast 30 patents

STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL W...

SEMICONDUCTOR DEVICE

MULTI-DIE WIREBOND PACKAGES WITH ELONGATED WINDOWS

METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDI...

SEMICONDUCTOR ASSEMBLIES WITH MULTI-LEVEL SUBSTRATES AND ASSOCIATED...

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR

EXPANDED SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE

MULTIPLE DIE IN A FACE DOWN PACKAGE

SEMICONDUCTOR DEVICE

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

STACKED SEMICONDUCTOR PACKAGE

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR CHIP HAVING THE SAME, AND ST...

MULTI-CHIP PACKAGE HAVING A STACKED PLURALITY OF DIFFERENT SIZED SE...

MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE

MULTIPLE DIE STACKING FOR TWO OR MORE DIE

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...

STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL W...

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...

STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE

MULTIPLE DIE IN A FACE DOWN PACKAGE

SEMICONDUCTOR ASSEMBLIES WITH MULTI-LEVEL SUBSTRATES AND ASSOCIATED...

METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDI...

IMPEDENCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR