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H01L2224/0333

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/0333in solid form

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Multiple plated via arrays of different wire heights on a same subs...
- Patent number RE49987
- Issue date May 28, 2024
- Invensas LLC
- Cyprian Emeka Uzoh
Information Patent Grant
Semiconductor device package including embedded conductive elements
- Patent number 11,282,817
- Issue date Mar 22, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yu-Feng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Through-substrate conductor support
- Patent number 11,084,717
- Issue date Aug 10, 2021
- Texas Instruments Incorporated
- Virgil Cotoco Ararao
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Wafer level package (WLP) and method for forming the same
- Patent number 10,861,801
- Issue date Dec 8, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing multi-chip package
- Patent number 10,679,972
- Issue date Jun 9, 2020
- Samsung Electronics Co., Ltd.
- Won-Gil Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple plated via arrays of different wire heights on same substrate
- Patent number 10,629,567
- Issue date Apr 21, 2020
- Invensas Corporation
- Cyprian Emeka Uzoh
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Semiconductor device and method of fabricating 3D package with shor...
- Patent number 10,629,531
- Issue date Apr 21, 2020
- STATS ChipPAC Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of producing optoelectronic component with integrated protec...
- Patent number 10,586,788
- Issue date Mar 10, 2020
- OSRAM OLED GmbH
- Jürgen Moosburger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mechanisms of forming connectors for package on package
- Patent number 10,553,561
- Issue date Feb 4, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yu-Feng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level package (WLP) and method for forming the same
- Patent number 10,510,690
- Issue date Dec 17, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level packaging for enhanced performance
- Patent number 10,490,471
- Issue date Nov 26, 2019
- Qorvo US, Inc.
- Julio C. Costa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level packaging for enhanced performance
- Patent number 10,453,765
- Issue date Oct 22, 2019
- Qorvo US, Inc.
- Julio C. Costa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level packaging for enhanced performance
- Patent number 10,418,297
- Issue date Sep 17, 2019
- Qorvo US, Inc.
- Julio C. Costa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of processing a porous conductive structure in connection to...
- Patent number 10,373,868
- Issue date Aug 6, 2019
- Infineon Technologies Austria AG
- Martin Mischitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and manufacturing method thereof
- Patent number 10,319,692
- Issue date Jun 11, 2019
- Taiwan Semiconductor Manufacturing Company Ltd.
- Yung-Ping Chiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple bond via arrays of different wire heights on a same substrate
- Patent number 10,290,613
- Issue date May 14, 2019
- Invensas Corporation
- Cyprian Emeka Uzoh
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Transfer substrate for forming metal wiring and method for forming...
- Patent number 10,256,113
- Issue date Apr 9, 2019
- Tanaka Kikinzoku Kogyo K.K.
- Toshinori Ogashiwa
- B22 - CASTING POWDER METALLURGY
Information Patent Grant
Conductive connections, structures with such connections, and metho...
- Patent number 10,090,231
- Issue date Oct 2, 2018
- Invensas Corporation
- Cyprian Emeka Uzoh
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Wafer level package (WLP) and method for forming the same
- Patent number 10,074,617
- Issue date Sep 11, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive compositions and methods of using them
- Patent number 10,059,827
- Issue date Aug 28, 2018
- Rajan Hariharan
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Grant
Conductive connections, structures with such connections, and metho...
- Patent number 10,049,998
- Issue date Aug 14, 2018
- Invensas Corporation
- Rajesh Katkar
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor device and method of fabricating 3D package with shor...
- Patent number 9,941,207
- Issue date Apr 10, 2018
- STATS ChipPAC Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device with periphery contact pads surrounding central c...
- Patent number 9,859,196
- Issue date Jan 2, 2018
- STMicroelectronics (Shenzhen) R&D Co., Ltd.
- Jing-En Luan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced board level reliability for wafer level packages
- Patent number 9,837,368
- Issue date Dec 5, 2017
- Maxim Integrated Products, Inc.
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive connections, structures with such connections, and metho...
- Patent number 9,793,198
- Issue date Oct 17, 2017
- Invensas Corporation
- Cyprian Emeka Uzoh
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multiple bond via arrays of different wire heights on a same substrate
- Patent number 9,728,527
- Issue date Aug 8, 2017
- Invensas Corporation
- Cyprian Emeka Uzoh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Environmental hardened packaged integrated circuit
- Patent number 9,711,480
- Issue date Jul 18, 2017
- Global Circuit Innovations Incorporated
- Erick Merle Spory
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip package structure and fabrication process thereof
- Patent number 9,653,355
- Issue date May 16, 2017
- Silergy Semiconductor Technology (Hangzhou) Ltd.
- Xiaochun Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optoelectronic component with integrated protection diode and metho...
- Patent number 9,653,440
- Issue date May 16, 2017
- Osram Opto Semiconductors GmbH
- Jürgen Moosburger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple bond via arrays of different wire heights on a same substrate
- Patent number 9,583,456
- Issue date Feb 28, 2017
- Invensas Corporation
- Cyprian Emeka Uzoh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE, POWER CONVERSION DEVICE, AND METHOD OF MANUFA...
- Publication number 20240234348
- Publication date Jul 11, 2024
- Mitsubishi Electric Corporation
- Yasunari HINO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE, POWER CONVERSION DEVICE, AND METHOD OF MANUFA...
- Publication number 20240136309
- Publication date Apr 25, 2024
- Mitsubishi Electric Corporation
- Yasunari HINO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR ASSEMBLY INCLUDING MULTIPLE SOLDER MASKS
- Publication number 20240038703
- Publication date Feb 1, 2024
- ATI Technologies ULC
- JIANGUO LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THROUGH-SUBSTRATE CONDUCTOR SUPPORT
- Publication number 20210323816
- Publication date Oct 21, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Virgil Cotoco Ararao
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Wafer Level Package (WLP) and Method for Forming the Same
- Publication number 20200098705
- Publication date Mar 26, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE PLATED VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON SAME SUBSTRATE
- Publication number 20190148344
- Publication date May 16, 2019
- Invensas Corporation
- Cyprian Emeka UZOH
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD OF MANUFACTURING MULTI-CHIP PACKAGE
- Publication number 20190103381
- Publication date Apr 4, 2019
- Samsung Electronics Co., Ltd.
- Won-Gil HAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level Package (WLP) and Method for Forming the Same
- Publication number 20180374801
- Publication date Dec 27, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multiple bond via arrays of different wire heights on a same substrate
- Publication number 20180301436
- Publication date Oct 18, 2018
- Invensas Corporation
- Cyprian Emeka UZOH
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Semiconductor Device and Method of Fabricating 3D Package with Shor...
- Publication number 20180190581
- Publication date Jul 5, 2018
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHO...
- Publication number 20180019191
- Publication date Jan 18, 2018
- Invensas Corporation
- Cyprian Emeka UZOH
- B32 - LAYERED PRODUCTS
Information Patent Application
METHOD FOR PROCESSING A SUBSTRATE AND AN ELECTRONIC DEVICE
- Publication number 20170207123
- Publication date Jul 20, 2017
- Infineon Technologies Austria AG
- Martin MISCHITZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND PROCESS FOR EMIB CHIP INTERCONNECTIONS
- Publication number 20170018525
- Publication date Jan 19, 2017
- Intel Corporation
- Rajendra C. Dias
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conductive Compositions and Methods of Using Them
- Publication number 20160251495
- Publication date Sep 1, 2016
- ALPHA METALS, INC.
- Rajan Hariharan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20150048510
- Publication date Feb 19, 2015
- Denso Corporation
- Manabu Tomisaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GRAPHENE-BASED METAL DIFFUSION BARRIER
- Publication number 20140339700
- Publication date Nov 20, 2014
- Fan Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING CHIP PACKAGE STRUCTURE
- Publication number 20140322869
- Publication date Oct 30, 2014
- CHIPMOS TECHNOLOGIES INC.
- Chien-Hao Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSFER SUBSTRATE FOR FORMING METAL WIRING LINE AND METHOD FOR FOR...
- Publication number 20140262003
- Publication date Sep 18, 2014
- Tanaka Kikinzoku Kogyo K.K.
- Toshinori Ogashiwa
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SEMICONDUCTOR MODULE SYSTEM HAVING ENCAPSULATED THROUGH WIRE INTERC...
- Publication number 20140225259
- Publication date Aug 14, 2014
- Micron Technology, Inc.
- David R. Hembree
- G01 - MEASURING TESTING
Information Patent Application
LOW-K CHIP PACKAGING STRUCTURE
- Publication number 20140191379
- Publication date Jul 10, 2014
- JIANGYIN CHANGDIAN ADVANCED PACKAGING CO., LTD
- Li Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF
- Publication number 20140167256
- Publication date Jun 19, 2014
- SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
- Xiaochun Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PACKAGING LOW-K CHIP
- Publication number 20140162404
- Publication date Jun 12, 2014
- JIANGYIN CHANGDIAN ADVANCED PACKAGING CO., LTD
- Li Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE COMPOSITIONS AND METHODS OF USING THEM
- Publication number 20140153167
- Publication date Jun 5, 2014
- ALPHA METALS, INC.
- Rajan Hariharan
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20140145343
- Publication date May 29, 2014
- SK HYNIX INC.
- Jong Hoon KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A THROUGH WIRE INTERCONNECT (TWI) ON A SEMIC...
- Publication number 20140038406
- Publication date Feb 6, 2014
- Micron Technology, Inc.
- David R. Hembree
- G01 - MEASURING TESTING
Information Patent Application
ELECTRONIC DEVICE PACKAGES HAVING BUMPS AND METHODS OF MANUFACTURIN...
- Publication number 20130334683
- Publication date Dec 19, 2013
- SK HYNIX INC.
- Seung Jee KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA AND ME...
- Publication number 20130334697
- Publication date Dec 19, 2013
- HanGil Shin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wire-Based Methodology of Widening the Pitch of Semiconductor Chip...
- Publication number 20130307141
- Publication date Nov 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Charles Anthony Odegard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MECHANISMS OF FORMING CONNECTORS FOR PACKAGE ON PACKAGE
- Publication number 20130221522
- Publication date Aug 29, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Feng CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSFER SUBSTRATE FOR FORMING METAL WIRING AND METHOD FOR FORMING...
- Publication number 20130196504
- Publication date Aug 1, 2013
- Tanaka Kikinzoku Kogyo K.K.
- Toshinori Ogashiwa
- B81 - MICRO-STRUCTURAL TECHNOLOGY

in solid form

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Multiple plated via arrays of different wire heights on a same subs...

Semiconductor device package including embedded conductive elements

Through-substrate conductor support

Wafer level package (WLP) and method for forming the same

Method of manufacturing multi-chip package

Multiple plated via arrays of different wire heights on same substrate

Semiconductor device and method of fabricating 3D package with shor...

Method of producing optoelectronic component with integrated protec...

Mechanisms of forming connectors for package on package

Wafer level package (WLP) and method for forming the same

Wafer-level packaging for enhanced performance

Wafer-level packaging for enhanced performance

Wafer-level packaging for enhanced performance

Method of processing a porous conductive structure in connection to...

Semiconductor structure and manufacturing method thereof

Multiple bond via arrays of different wire heights on a same substrate

Transfer substrate for forming metal wiring and method for forming...

Conductive connections, structures with such connections, and metho...

Wafer level package (WLP) and method for forming the same

Conductive compositions and methods of using them

Conductive connections, structures with such connections, and metho...

Semiconductor device and method of fabricating 3D package with shor...

Electronic device with periphery contact pads surrounding central c...

Enhanced board level reliability for wafer level packages

Conductive connections, structures with such connections, and metho...

Multiple bond via arrays of different wire heights on a same substrate

Environmental hardened packaged integrated circuit

Flip chip package structure and fabrication process thereof

Optoelectronic component with integrated protection diode and metho...

Multiple bond via arrays of different wire heights on a same substrate

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE, POWER CONVERSION DEVICE, AND METHOD OF MANUFA...

SEMICONDUCTOR DEVICE, POWER CONVERSION DEVICE, AND METHOD OF MANUFA...

SEMICONDUCTOR ASSEMBLY INCLUDING MULTIPLE SOLDER MASKS

THROUGH-SUBSTRATE CONDUCTOR SUPPORT

Wafer Level Package (WLP) and Method for Forming the Same

MULTIPLE PLATED VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON SAME SUBSTRATE

METHOD OF MANUFACTURING MULTI-CHIP PACKAGE

Wafer Level Package (WLP) and Method for Forming the Same

Multiple bond via arrays of different wire heights on a same substrate

Semiconductor Device and Method of Fabricating 3D Package with Shor...

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHO...

METHOD FOR PROCESSING A SUBSTRATE AND AN ELECTRONIC DEVICE

METHOD AND PROCESS FOR EMIB CHIP INTERCONNECTIONS

Conductive Compositions and Methods of Using Them

SEMICONDUCTOR DEVICE

GRAPHENE-BASED METAL DIFFUSION BARRIER

METHOD FOR MANUFACTURING CHIP PACKAGE STRUCTURE

TRANSFER SUBSTRATE FOR FORMING METAL WIRING LINE AND METHOD FOR FOR...

SEMICONDUCTOR MODULE SYSTEM HAVING ENCAPSULATED THROUGH WIRE INTERC...

LOW-K CHIP PACKAGING STRUCTURE

FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF

METHOD FOR PACKAGING LOW-K CHIP

CONDUCTIVE COMPOSITIONS AND METHODS OF USING THEM

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

METHOD FOR FABRICATING A THROUGH WIRE INTERCONNECT (TWI) ON A SEMIC...

ELECTRONIC DEVICE PACKAGES HAVING BUMPS AND METHODS OF MANUFACTURIN...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA AND ME...

Wire-Based Methodology of Widening the Pitch of Semiconductor Chip...

MECHANISMS OF FORMING CONNECTORS FOR PACKAGE ON PACKAGE

TRANSFER SUBSTRATE FOR FORMING METAL WIRING AND METHOD FOR FORMING...