Wafer-level packaging for enhanced performance

Abstract

The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.

Description

FIELD OF THE DISCLOSURE

The present disclosure relates to a mold module and a process for making the same, and more particularly to a mold module with enhanced thermal and electrical performance, and a wafer-level packaging process to provide the mold module with enhanced performance.

BACKGROUND

The wide utilization of cellular and wireless devices drives the rapid development of radio frequency (RF) technologies. The substrates on which RF devices are fabricated play an important role in achieving high level performance in the RF technologies. Fabrications of the RF devices on conventional silicon substrates may benefit from low cost of silicon materials, a large scale capacity of wafer production, well-established semiconductor design tools, and well-established semiconductor manufacturing techniques.

Despite the benefits of using conventional silicon substrates for the RF device fabrications, it is well known in the industry that the conventional silicon substrates may have two undesirable properties for the RF devices: harmonic distortion and low resistivity values. The harmonic distortion is a critical impediment to achieve high level linearity in the RF devices built over silicon substrates. In addition, the low resistivity encountered in the silicon substrates may degrade quality factors (Q) at high frequencies of microelectromechanical systems (MEMS) or other passive components.

In addition, high speed and high performance transistors are more densely integrated in RF devices. Consequently, the amount of heat generated by the RF devices will increase significantly due to the large number of transistors integrated in the RF devices, the large amount of power passing through the transistors, and the high operation speed of the transistors. Accordingly, it is desirable to package the RF devices in a configuration for better heat dissipation.

To accommodate the increased heat generation of the RF devices and to reduce deleterious harmonic distortion of the RF devices, it is therefore an object of the present disclosure to provide an improved packaging process for enhanced thermal and electrical performance. Further, there is also a need to enhance the performance of the RF devices without increasing the package size.

SUMMARY

The present disclosure relates to a wafer-level packaging process to provide mold modules with enhanced performance. According to an exemplary wafer-level packaging process, a precursor wafer that includes a device layer, a number of first bump structures, a stop layer, and a silicon handle layer is provided. Herein, the device layer has a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is over the top surface of the device layer and electronically coupled to a corresponding I/O contact. The stop layer resides underneath the device layer, and a silicon handle layer resides underneath the stop layer, such that the stop layer separates the device layer from the silicon handle layer. A first mold compound is then applied over the device layer to encapsulate each first bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to provide a mold wafer. A portion of each first bump structure is exposed through the first mold compound.

In one embodiment of the wafer-level packaging process, removing substantially the silicon handle layer is provided by one of chemical mechanical grinding, wet etching, and dry etching.

In one embodiment of the wafer-level packaging process, applying the first mold compound is provided by one of compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation.

In one embodiment of the wafer-level packaging process, applying the second mold compound is provided by one of compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation.

In one embodiment of the wafer-level packaging process, thinning down the first mold compound is provided by mechanical grinding.

According to another embodiment, the wafer-level packaging process further includes forming a number of second bump structures over the first mold compound after the first mold compound is thinned down. Herein, each second bump structure is in contact with a corresponding first bump structure.

According to another embodiment, the wafer-level packaging process further includes singulating the mold wafer into individual mold modules.

In one embodiment of the wafer-level packaging process, the silicon handle layer, the stop layer, and the device layer are formed from a silicon-on-insulator (SOI) structure. Herein, the silicon handle layer is a silicon substrate of the SOI structure, the stop layer is a buried oxide (BOX) layer of the SOI structure, and the device layer is formed from a silicon epitaxy layer of the SOI structure.

In one embodiment of the wafer-level packaging process, the device layer provides one of a microelectromechanical systems (MEMS) device, an integrated passive device, and an active device.

In one embodiment of the wafer-level packaging process, the precursor wafer further includes a passivation layer formed over the device layer. Herein, a portion of each I/O contact is exposed through the passivation layer and each first bump structure protrudes from a top surface of the passivation layer and is coupled to the exposed portion of a corresponding I/O contact through the passivation layer.

According to another embodiment, the wafer-level packaging process further includes patterning the passivation layer to form a number of discrete passivation pads before applying the first mold compound over the device layer. Herein, each discrete passivation pad is aligned over a corresponding I/O contact. A portion of each I/O contact is exposed through a corresponding discrete passivation pad. Each first bump structure protrudes from a top surface of the corresponding discrete passivation pad and is coupled to the exposed portion of a corresponding I/O contact through the corresponding discrete passivation pad. Each discrete passivation pad is encapsulated by the first mold compound.

In one embodiment of the wafer-level packaging process, patterning the passivation layer is provided by photo masking or stencil screening.

In one embodiment of the wafer-level packaging process, the passivation layer is formed of benzocyclobutene (BCB) or polyimide.

According to another embodiment, the wafer-level packaging process further includes forming at least one window component over the device layer before applying the first mold compound over the device layer. The at least one window component is not in contact with the first bump structures. The at least one window component has a height greater than each first bump structure. The window component is encapsulated by the first mold compound.

In one embodiment of the wafer-level packaging process, a portion of the at least one window component is exposed after thinning down the first mold compound.

In one embodiment of the wafer-level packaging process, the at least one window component is transparent.

According to another embodiment, the wafer-level packaging process further includes removing the at least one window component to expose a portion of the top surface of the device layer after the first mold compound is thinned down.

In one embodiment of the wafer-level packaging process, the precursor wafer further includes a redistribution structure formed over the device layer. Herein, each first bump structure protrudes from a top surface of the redistribution structure. The redistribution structure includes redistribution interconnects that connect the I/O contacts to certain ones of the first bump structures. The first mold compound resides over the redistribution structure.

In one embodiment of the wafer-level packaging process, the first mold compound is formed from a same material as the second mold compound.

In one embodiment of the wafer-level packaging process, the first mold compound and the second mold compound have a thermal conductivity greater than 1 W/m·K. The first mold compound and the second mold compound have a dielectric constant between 3 and 5.

In one embodiment of the wafer-level packaging process, the first mold compound and the second mold compound have a thermal conductivity greater than 1 W/m·K. The first mold compound and the second mold compound have a dielectric constant less than 7.

In one embodiment of the wafer-level packaging process, the first mold compound and the second mold compound are formed from different materials.

In one embodiment of the wafer-level packaging process, the first mold compound is transparent.

In one embodiment of the wafer-level packaging process, the stop layer is formed of at least one of silicon oxide or silicon nitride.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIGS. 1A-1C show exemplary mold modules with enhanced thermal and electrical performance according to one embodiment of the present disclosure.

FIGS. 2A-2B show alternative exemplary mold modules with enhanced thermal and electrical performance according to one embodiment of the present disclosure.

FIG. 3 shows an alternative mold module with enhanced thermal and electrical performance according to one embodiment of the present disclosure.

FIGS. 4-11 provide an exemplary wafer-level packaging process that illustrates steps to fabricate the exemplary mold module shown in FIG. 2B.

It will be understood that for clear illustrations, FIGS. 1A-11 may not be drawn to scale.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The present disclosure relates to a mold module with enhanced thermal and electrical performance, and a wafer-level packaging process to provide the mold module with enhanced performance. FIG. 1A shows an exemplary mold module 10 according to one embodiment of the present disclosure. For the purpose of this illustration, the exemplary mold module 10 includes a device layer 12 with a number of input/output (I/O) contacts 14, a number of first bump structures 16, a first mold compound 18, a stop layer 20, and a second mold compound 22.

In detail, the I/O contacts 14 are located at a top surface of the device layer 12. The device layer 12 may include at least one of a microelectromechanical systems (MEMS) device, an integrated passive device, and an active device (not shown), which may generate heat in the device layer 12. Each first bump structure 16 is formed over the device layer 12 and in contact with a corresponding I/O contact 14. The first mold compound 18 resides over the device layer 12 and partially encapsulates each first bump structure 16, such that a portion of each first bump structure 16 is exposed through the first mold compound 18. The stop layer 20 is formed underneath the device layer 12 and the second mold compound 22 resides underneath the stop layer 20, such that the stop layer 20 separates the device layer 12 from the second mold compound 22.

The I/O contacts 14 at the top surface of the device layer 12 may be formed of copper, silver, gold or other conductive metals, and the first bump structures 16 are solder balls. As such, each first bump structure 16 and the corresponding I/O contact 14 are electronically coupled. The stop layer 20 may be formed of at least one of silicon oxide or silicon nitride. The heat generated in the device layer 12 may travel through path A and/or path B. For the path A, the heat will travel downward to a top portion of the second mold compound 22, then will pass upward through the stop layer 20, the device layer 12, and the first bump structures 16, which will dissipate the heat. For the path B, the heat will travel directly through the first mold compound 18 to be conducted. It is therefore highly desirable to have high thermal conductivities of both the first and second mold compounds 18 and 22. The first mold compound 18 and the second mold compound 22 may have a thermal conductivity greater than 1 W/m·K, or greater than 10 W/m·K. In addition, the first mold compound 18 and the second mold compound 22 may have a low dielectric constant less than 7, or between 3 and 5 to yield low radio frequency (RF) coupling between devices (not shown) within the device layer 12. The first mold compound 18 may be formed of a same or different material as the second mold compound 22. The first mold compound 18 may be transparent. In one embodiment, both the first mold compound 18 and the second mold compound 22 may be formed of thermoplastics or thermoset polymer materials, such as PPS (poly phenyl sulfide), overmold epoxies doped with boron nitride or alumina thermal additives, or the like. The device layer has a thickness between 0.1 μm and 50 μm, the stop layer has a thickness between 10 nm and 1000 nm, the first mold compound has a thickness between 10 μm and 1000 μm, and the second mold compound has a thickness between 200 μm and 500 μm.

Herein, the mold module 10 has a planar top surface, where the first bump structures 16 do not protrude from the top surface of the first mold compound 18. In some applications, it would be desirable to have protruding structures at the top surface of the mold module 10 to facilitate and improve the reliability of die attaching (to the printed circuit board) operations. As shown in FIG. 1B, the mold module 10 may further include a number of second bump structures 24. Each second bump structure 24 is in contact with a corresponding first bump structure 16, and protrudes from the top surface of the first mold compound 18. The second bump structures 24 may be formed from solder paste, such that one I/O contact 14, the corresponding first bump structure 16, and the corresponding second bump structure 24 are electronically coupled. In some applications, the mold module 10 utilizes copper pillars instead of solder balls for first bump structures 16A as illustrated in FIG. 1C. Further, second bump structures 24A may be formed from conductive epoxy or reflowable metals: such as gold, silver, and alloy. Each I/O contact 14, the corresponding first bump structure 16, and the corresponding second bump structure 24 are electronically coupled.

In another embodiment, the mold module 10 may further include a passivation layer 26 as illustrated in FIG. 2A. The passivation layer 26 is formed over the device layer 12 and a portion of each I/O contact 14 is exposed through the passivation layer 12. Each first bump structure 16 protrudes from a top surface of the passivation layer 26 and is coupled to the exposed portion of the corresponding I/O contact 14 through the passivation layer 26. The first mold compound 18 resides over the passivation layer 26, partially encapsulates each first bump structure 16, and is not in contact with the first mold compound 18. The passivation layer 26 may be formed of benzocyclobutene (BCB) or polyimide, and has a thickness between 5 nm and 5000 nm.

It is clear to those skilled in the art, this passivation layer 26 may help to mitigate the stresses associated with the module attaching process. However, the passivation layer 26 may have poor thermal conductivity, so as to obstruct the heat generated in the device layer 12 conducting through the first mold compound 18 (no path B). Alternatively, the mold module 10 may include a number of discrete passivation pads 26A instead of the continuous passivation layer 26 formed between the device layer 12 and the first mold compound 18, as illustrated in FIG. 2B. Herein, the discrete passivation pads 26A do not fully cover the device layer 12 and portions of the device layer 12 are in contact with the first mold compound 18. Each I/O contact 14 is aligned underneath a corresponding discrete passivation pad 26A, a portion of each I/O contact 14 is exposed through the corresponding discrete passivation pad 26A, and no I/O contact 14 is in contact with the first mold compound 18. Each first bump structure 16 protrudes from a top surface of the corresponding discrete passivation pad 26A and is coupled to the exposed portion of the corresponding I/O contact 14 through the corresponding discrete passivation pad 26A. The discrete passivation pads 26A may be formed of BCB or polyimide, and each discrete passivation pad 26A has a thickness between 5 nm and 5000 nm.

Herein, the discrete passivation pads 26A do not separate the device layer 12 from the first mold compound 18. As such, the heat generated in the device layer 12 may travel through path A (from the device layer 12 downward to the top portion of the second mold compound 22, then upward through the stop layer 20, the device layer 12, and the first bump structures 16) and/or path B (from the device layer 12 directly through the first mold compound 18).

In some applications, the mold module 10 may further include a redistribution structure 28 formed between the device layer 12 and the first mold compound 18, as illustrated in FIG. 3. The redistribution structure 28 includes a first dielectric layer 30, a number of redistribution interconnects 32, and a second dielectric layer 34. The first dielectric layer 30 resides over the device layer 12 and a portion of each I/O contact 14 is exposed through the first dielectric layer 30. Each redistribution interconnect 32 is connected to certain one(s) of the I/O contacts 14 and extends over the first dielectric layer 30. The second dielectric layer 34 resides over the first dielectric layer 30 to partially encapsulate each redistribution interconnect 32, such that a portion of each redistribution interconnect 32 is exposed through the second dielectric layer 34. Each first bump structure 16 protrudes from a top surface of the redistribution structure 28 and is electronically coupled to certain one(s) of the I/O contacts 14 via the redistribution interconnects 32. The first and second dielectric layers 30 and 34 may be formed of BCB or polyimide, and the redistribution interconnects 32 may be formed of copper or other suitable metals. The redistribution structure 28 has a thickness between 2 μm and 300 μm.

FIGS. 4-11 provide an exemplary wafer-level packaging process that illustrates steps to fabricate the exemplary mold module 10 shown in FIG. 2B. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 4-11.

Initially, a precursor wafer 36 is provided as illustrated in FIG. 4. The precursor wafer 36 includes a silicon handle layer 38, the stop layer 20, the device layer 12 with the I/O contacts 14 at the top surface of the device layer 12, the first bump structures 16, and the passivation layer 26. The passivation layer 26 is formed over the device layer 12 and a portion of each I/O contact 14 is exposed through the passivation layer 12. Each first bump structure 16 protrudes from the top surface of the passivation layer 26 and is coupled to the exposed portion of the corresponding I/O contact 14 through the passivation layer 26. The stop layer 20 is formed underneath the device layer 12 and the silicon handle layer 38 resides underneath the stop layer 20, such that the stop layer 20 separates the device layer 12 from the silicon handle layer 38. Herein, the silicon handle layer 38 may have a thickness between 200 μm and 500 μm and a relatively high dielectric constant greater than 7. In some applications, the silicon handle layer 38, the stop layer 20, and the device layer 12 may be formed from a silicon-on-insulator (SOI) structure, which refers to a structure including a silicon substrate, a silicon epitaxy layer, and a buried oxide (BOX) layer sandwiched between the silicon substrate and the silicon epitaxy layer. The silicon handle layer 38 is the silicon substrate of the SOI structure, the stop layer 20 is the BOX layer of the SOI structure, and the device layer 12 is formed from the silicon epitaxy layer of the SOI structure. In some applications, the precursor wafer 36 may not include the passivation layer 26. As such, each first bump structure 16 is formed over the device layer 12 and in contact with a corresponding I/O contact 14.

The passivation layer 26 is then patterned to form the discrete passivation pads 26A as illustrated in FIG. 5. Herein, the discrete passivation pads 26A do not fully cover the device layer 12. Portions of the device layer 12 are exposed through the discrete passivation pads 26A. Each discrete passivation pad 26A is aligned over a corresponding I/O contact 14, and a portion of each I/O contact 14 is exposed through a corresponding discrete passivation pad 26A. Each first bump structure 16 protrudes from a top surface of the corresponding discrete passivation pad 26A and is coupled to the exposed portion of the corresponding I/O contact 14 through the corresponding discrete passivation pad 26A. Patterning the passivation layer 26 may be provided by a lithography procedure, such as photo masking or stencil screening. If there is no passivation layer 26 included in the precursor wafer 36, the patterning process will be omitted.

Next, at least one window component 40 may be formed over the device layer 12 at where the wafer mark(s) (not shown) is/are located as illustrated in FIG. 6. Herein, the wafer mark indicates the key location(s) of a wafer, which will be utilized for alignment in a following singulation and/or an assembly process. In one embodiment, the at least one window component 40 is located at the periphery of the device layer 12. The at least one window component 40 may be formed of a transparent material (for instance: transparent silicone material), such that the wafer mark will be seen through the at least one window component 40. In addition, at least one window component 40 may be formed of an easily removable material (for instance: acrylic polymer), such that the wafer mark will be seen after the easy removal of the at least one window component 40 (more details in following discussion). The at least one window component 40 has a height greater than each first bump structure 16 and is not connected to any first bump structure 16. Notice that the at least one window component 40 is optional. In some applications, forming the at least one window component 40 over the device layer 12 may be omitted.

The first mold compound 18 is applied over the device layer 12 to encapsulate each first bump structure 16 and the at least one window component 40, as illustrated in FIG. 7. The first mold compound 18 may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, or screen print encapsulation. The first mold compound 18 may have a superior thermal conductivity greater than 1 W/m·K, or greater than 10 W/m·K, and may have a dielectric constant less than 7, or between 3 and 5. The first mold compound 18 may resist etching chemistries such as potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH). In some applications, the first mold compound 18 may be formed of a transparent material. As such, there is no need to form the at least one window component 40 over the device layer 12, because all locations of a wafer may be seen through the first mold compound 18. A curing process (not shown) is then used to harden the first mold compound 18. The curing temperature is between 100° C. and 320° C. depending on which material is used as the first mold compound 18.

After the first mold compound 18 is formed, the silicon handle layer 38 is removed substantially as illustrated in FIG. 8. Herein, removing substantially the silicon handle layer 38 refers to removing at least 95% of the entire silicon handle layer 38 and remaining at most 2 μm of the silicon handle layer 38. In desired cases, the silicon handle layer 38 is removed completely, such that the stop layer 20 is exposed. Removing substantially the silicon handle layer 38 may be provided by an chemical mechanical grinding process or an etching process with a wet/dry etchant chemistry, which may be TMAH, KOH, ACH, NaOH, or the like. During the removal process, the first mold compound 18 protects the top surface of the device layer 12, while the stop layer 20 protects a bottom surface of the device layer 12.

The second mold compound 22 is then applied to an exposed surface from which the silicon handle layer 38 was removed, as illustrated in FIG. 9. If the silicon handle layer 38 is removed completely, the second mold compound 22 is in contact with the stop layer 20. The second mold compound 22 may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation. A curing process (not shown) is followed to harden the second mold compound 22. The curing temperature is between 100° C. and 320° C. depending on which material is used as the second mold compound 22. After the curing process, a bottom surface of the second mold compound 22 may be planarized (not shown).

Next, the first mold compound 18 is thinned down to provide a mold wafer 42 as illustrated in FIG. 10A. Herein, a portion of each first bump structure 16 is exposed. Since the at least one window component 40 has a height greater than each first bump structure 16, a portion of the at least one window component 40 is also exposed through the first mold compound 18. The thinning procedure may be done with a mechanical grinding process. In one embodiment, the at least one window component 40 may be formed of a transparent material, such that the wafer mark indicating the key location(s) of a wafer will be seen through the at least one window component 40. In another embodiment, the at least one window component 40 may be formed of an opaque material, such that the wafer mark indicating the key location(s) of a wafer will not be seen through the at least one window component 40. An extra step to remove the at least one window component 40 is needed, as illustrated in FIG. 10B. After the removal step, at least one portion of the top surface of the device layer 12 is exposed. As such, the wafer mark indicating the key location(s) of a wafer will be seen. Further, in some applications, the second bump structures 24 may be formed after the first mold compound 18 is thinned down, as illustrated in FIG. 10C. Each second bump structure 24 is formed over a corresponding first bump structure 16, and electronically coupled to a corresponding I/O contact 14 via the corresponding first bump structure 16.

Finally, the mold wafer 42 is singulated into individual mold modules 10, as illustrated in FIG. 11. The singulating step may be provided by a probing and dicing process. The individual mold module 10 may be assembled on the PCB using a number of die attaching methods.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A method comprising: providing a precursor wafer that includes a silicon handle layer, a stop layer, a device layer, and a plurality of first bump structures, wherein: the device layer has a plurality of input/output (I/O) contacts at a top surface of the device layer;the plurality of first bump structures are formed over the device layer, wherein each of the plurality of first bump structures is electronically coupled to a corresponding I/O contact;the stop layer resides underneath the device layer; andthe silicon handle layer resides underneath the stop layer, such that the stop layer separates the device layer from the silicon handle layer;applying a first mold compound over the device layer to encapsulate each of the plurality of first bump structures;removing substantially the silicon handle layer;applying a second mold compound to an exposed surface from which the silicon handle layer was removed; andthinning down the first mold compound to provide a mold wafer, wherein a portion of each of the plurality of first bump structures is exposed.

2. The method of claim 1 wherein removing substantially the silicon handle layer is provided by one of a group consisting of chemical mechanical grinding, wet etching, and dry etching.

3. The method of claim 1 wherein applying the first mold compound is provided by one of a group consisting of compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation.

4. The method of claim 1 wherein applying the second mold compound is provided by one of a group consisting of compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation.

5. The method of claim 1 wherein thinning down the first mold compound is provided by mechanical grinding.

6. The method of claim 1 further comprising forming a plurality of second bump structures over the first mold compound after the first mold compound is thinned down, wherein each of the plurality of second bump structures is in contact with a corresponding first bump structure.

7. The method of claim 1 further comprising singulating the mold wafer into individual mold modules.

8. The method of claim 1, wherein the silicon handle layer, the stop layer, and the device layer are formed from a silicon-on-insulator (SOI) structure, wherein the silicon handle layer is a silicon substrate of the SOI structure, the stop layer is a buried oxide (BOX) layer of the SOI structure, and the device layer is formed from a silicon epitaxy layer of the SOI structure.

9. The method of claim 1, wherein the device layer provides one of a group consisting of a microelectromechanical systems (MEMS) device, an integrated passive device, and an active device.

10. The method of claim 1, wherein the precursor wafer further comprises a passivation layer formed over the device layer, wherein a portion of each of the plurality of I/O contacts is exposed through the passivation layer and each of the plurality of first bump structures protrudes from a top surface of the passivation layer and is coupled to the exposed portion of a corresponding I/O contact through the passivation layer.

11. The method of claim 10 further comprising patterning the passivation layer to form a plurality of discrete passivation pads before applying the first mold compound over the device layer, wherein: each of plurality of discrete passivation pads is aligned over a corresponding I/O contact;a portion of each of the plurality of I/O contacts is exposed through a corresponding discrete passivation pad;each of the plurality of first bump structures protrudes from a top surface of the corresponding discrete passivation pad and is coupled to the exposed portion of a corresponding I/O contact through the corresponding discrete passivation pad; andeach of plurality of discrete passivation pads is encapsulated by the first mold compound.

12. The method of claim 10 wherein the passivation layer is formed of benzocyclobutene (BCB) or polyimide.

13. The method of claim 1 further comprising forming at least one window component over the device layer before applying the first mold compound over the device layer, wherein: the at least one window component has a height greater than each of the plurality of first bump structures and is not in contact with the plurality of first bump structures; andthe at least one window component is encapsulated by the first mold compound.

14. The method of claim 13 wherein a portion of the at least one window component is exposed after thinning down the first mold compound.

15. The method of claim 14 further comprising removing the at least one window component to expose a portion of the top surface of the device layer.

16. The method of claim 13 wherein the at least one window component is transparent.

17. The method of claim 1, wherein the precursor wafer further comprises a redistribution structure formed over the device layer, wherein: each of the plurality of first bump structures protrudes from a top surface of the redistribution structure;the redistribution structure includes redistribution interconnects that connect the plurality of I/O contacts to certain ones of the plurality of first bump structures; andthe first mold compound resides over the redistribution structure.

18. The method of claim 1, wherein the first mold compound is formed from a same material as the second mold compound.

19. The method of claim 18, wherein: the first mold compound and the second mold compound have a thermal conductivity greater than 1 W/m·K; andthe first mold compound and the second mold compound have a dielectric constant less than 7.

20. The method of claim 1, wherein the first mold compound and the second mold compound are formed from different materials.

21. The method of claim 1, wherein the first mold compound is transparent.

22. The method of claim 1, wherein the stop layer is formed of at least one of silicon oxide or silicon nitride.