Patent Application
20240136309
The present disclosure relates to a semiconductor device, a power conversion device, and a method of manufacturing the semiconductor device.
Structures in each of which a copper (Cu) electrode made of Cu is formed on a top electrode of a semiconductor element and a wire made of a metal such as Al is bonded to the Cu electrode are known as example structures of semiconductor devices for power control. Japanese Patent Application Laid-Open No. 2006-86378 discloses a technology on a Cu electrode on a top electrode of a semiconductor element for reducing the resistance of the top electrode and enhancing the heat dissipation.
Recent years have seen an increased range of uses for the semiconductor devices for power control, and an increase in the currents of the semiconductor devices. Since the semiconductor devices for power control are used worldwide, support for the semiconductor devices under severe environments is sought. Here, the significant challenges are to pursue higher reliability and longer life of the semiconductor devices.
The structures in each of which a metal wire is directly bonded to a top electrode of a semiconductor element often have breaks caused by lift-off (peels) of wires. This creates a problem in pursuing higher reliability and longer life of the semiconductor devices.
As disclosed in Japanese Patent Application Laid-Open No. 2006-86378, the Cu electrode on the top electrode of the semiconductor element addresses the problem. However, forming Cu electrodes thick enough to endure the wire bonding requires Cu plating for enormous amounts of time. This leads to a problem of productivity. Plating technologies also require a great many processes including cleaning, drying, and resist processing. This poses other challenges such as a capital investment and reserving areas for installing facilities. Moreover, the plating technologies still have problems of non-uniform thicknesses and variations in appearance of plated films. Thus, the processes and the quality on the plated films need to be managed in detail. These incur an increase in the production costs.
The object of the present disclosure is to provide a semiconductor device with higher reliability and longer life which can suppress an increase in production costs.
The semiconductor device according to the present disclosure includes: a semiconductor element; a top electrode on an upper surface of the semiconductor element; and a conductive metal plate containing copper as a main component and solid-phase diffusion bonded to the top electrode of the semiconductor element.
The present disclosure can provide a semiconductor device with higher reliability and longer life which can suppress an increase in production costs.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
The semiconductor device 100 includes at least one semiconductor element 41 mounted on an insulating substrate 43. The number of the semiconductor elements 41 may be any. The semiconductor elements 41 should be mounted as many as required to correspond to a specification of the semiconductor device 100. In Embodiment 1, the semiconductor element 41 is made of silicon (Si), and is what is called a power semiconductor element for controlling the power. Representative examples of the power semiconductor element include an insulated-gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), and a freewheeling diode (FWD). One side of the semiconductor element 41 is approximately 1 mm to 20 mm long.
The semiconductor element 41 may contain a wide-bandgap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN), besides Si. The semiconductor device 100 including the semiconductor element 41 containing a wide-bandgap semiconductor is superior to a semiconductor device including a semiconductor element containing Si in operating with a high voltage, with a large current, and at a high temperature.
The insulating substrate 43 has a laminated structure obtained by laminating abase plate 43c, an insulating layer 43b, and a circuit pattern 43a in this order from the bottom. The semiconductor element 41 is mounted on the circuit pattern 43a of the insulating substrate 43 through a bonding material 42. The bonding material 42 is a conductive metal containing Sn, that is, solder. Since the semiconductor element 41 generates heat, the bonding material 42 may be a sintered material higher in thermal conductivity and heat dissipation than solder, for example, a sintered material containing Ag or Cu particles.
The circuit pattern 43a is made of a conductive metal containing copper (Cu) or aluminum (Al). The thickness of the circuit pattern 43a is set according to a current density or an exotherm temperature when the semiconductor device 100 is energized, for example, approximately 0.2 mm to 0.5 mm. The insulating layer 43b is made of an epoxy resin to which fillers having a higher thermal conductivity and made of, for example, BN and Al2O3 have been added. The insulating layer 43b is approximately 0.2 mm to 1.0 mm thick. The base plate 43c is made of a metal having a higher thermal conductivity and containing Cu or Al. The base plate 43c is approximately 1.0 mm to 5.0 mm thick. The insulating substrate 43 requires a thermal conductivity higher than or equal to several tens of W/(m·K). Thus, a material of each of the circuit pattern 43a, the insulating layer 43b, and the base plate 43c is selected so that the insulating substrate 43 obtains an appropriate thermal conductivity corresponding to a thermal dissipation specification required for the semiconductor element 41.
Furthermore, the circuit pattern 43a and the insulating layer 43b of the insulating substrate 43 may form what is called a direct bonded copper (DBC) substrate. In other words, the insulating layer 43b may be made of ceramic such as Al2O3, AlN, or Si3N4. The insulating substrate 43 may have a structure in which the circuit pattern 43a and the insulating layer 43b are integrated and a metal plate (not illustrated) is bonded to a lower surface of the insulating layer 43b. Here, the metal plate on the lower surface of the insulating layer 43b is bonded to the base plate 43c through a bonding material such as solder.
A casing 44 for housing the semiconductor element 41 is bonded to the periphery of the insulating layer 43b of the insulating substrate 43 through an adhesive 45, and is secured. The casing 44 is made of, for example, a polyphenylene sulfide (PPS) resin or a polybutylene terephthalate (PBT) resin.
The casing 44 includes electrode terminals 46. The electrode terminals 46 are insert molded together with the casing 44, and embedded in the casing 44. As illustrated in
The semiconductor element 41, the circuit pattern 43a, and the electrode terminals 46 are electrically connected to each other through metal wires 47 in the casing 44. As illustrated in
A sealant 48 fills the space inside the casing 44, that is, the space defined by the casing 44 and the insulating substrate 43, and seals the semiconductor element 41 and the metal wires 47. The sealant 48 is, for example, a gel-like silicone resin, or a thermosetting epoxy resin to which fillers containing SiO2 have been added. The material of the sealant 48 is not limited to these, and may be any plastic having a modulus of elasticity, a thermal conductivity, heat resistance, insulating properties, and adhesiveness that are required, for example, phenol resin or polyimide resin.
The adhesive 45 is a silicone-based adhesive. Alternatively, the adhesive 45 may be made of a material identical to that of the sealant 48. The adherence of the insulating layer 43b to the casing 44 through the adhesive 45 can prevent the sealant 48 from leaking from the casing 44.
The semiconductor element 41 includes a semiconductor substrate 30 having a first principal surface 31 and a second principal surface 32. The semiconductor substrate 30 includes a drift layer 1 of the first conductivity type, between the first principal surface 31 and the second principal surface 32. The semiconductor substrate 30 may contain typical silicon (Si), or a wide-bandgap semiconductor, for example, silicon carbide (SiC).
The cell region includes a carrier storage layer 2 of the first conductivity type which is formed closer to the first principal surface 31 with respect to the drift layer 1 and which is higher in peak impurity concentration than the drift layer 1. The cell region further includes a base layer 3 of the second conductivity type in a surface layer of the semiconductor substrate 30 on the first principal surface 31 side. In a surface layer of the base layer 3, emitter layers 5 of the first conductivity type, and contact layers 6 of the second conductivity type which are higher in peak impurity concentration than the base layer 3 are selectively formed.
Active trenches 10 each reaching the drift layer 1 through the emitter layer 5, the base layer 3, and the carrier storage layer 2, and dummy trenches 13 each reaching the drift layer 1 through the base layer 3 and the carrier storage layer 2 in a region without the emitter layer 5 are formed from the first principal surface 31 of the semiconductor substrate 30. The dummy trenches 13 are formed to surround the active trenches 10. In each of the active trenches 10 and the dummy trenches 13, a gate electrode 12 is embedded through a gate insulating film 11. The gate electrode 12 in each of the dummy trenches 13 is a dummy electrode that does not contribute to switching between ON and OFF of the IGBT.
An interlayer insulating film 4 covering the active trenches 10 and the dummy trenches 13 is formed on the first principal surface 31 of the semiconductor substrate 30. A barrier metal 23 is formed on the interlayer insulating film 4, and an emitter electrode 14 that is a metal electrode made of a metal, for example, aluminum (Al) or AlSi is formed on the barrier metal 23. The emitter electrode 14 is connected to the emitter layers 5 and the contact layers 6 through the barrier metal 23 and contact holes formed in the interlayer insulating film 4.
The barrier metal 23 is a Ti layer or a W layer. The barrier metal 23 is approximately 10 nm to 300 nm thick. The barrier metal 23 may have a two-layer structure of a Ti layer and a W layer, or may be made of TiW. The barrier metal 23 may be made of Ta, TaN, or TiN.
A buffer layer 7 of the first conductivity type which is higher in peak impurity concentration than the drift layer 1 is formed on the second principal surface 32 with respect to the drift layer 1. Furthermore, a collector layer 8 of the second conductivity type is formed in a surface layer of the second principal surface 32 on the semiconductor substrate 30 side. A collector electrode 9 connected to the collector layer 8 is formed closer to the second principal surface 32 of the semiconductor substrate 30. These buffer layer 7, collector layer 8, and collector electrode 9 are formed not only in the cell region but also in the terminal region.
The terminal region includes, on the first principal surface 31 in the surface layer of the semiconductor substrate 30, a well layer 15 of the second conductivity type which is deeper than the active trenches 10 and the dummy trenches 13, and resurf layers 16 of the second conductivity type which are formed more outside than the well layer 15. A field oxide film 17 is formed on the first principal surface 31 of the semiconductor substrate 30 to cover the well layer 15 and the resurf layers 16. A gate line 18 is formed on the field oxide film 17 above the well layer 15.
The gate line 18 is covered with the interlayer insulating film 4 extending from the cell region, and a gate runner 19 is formed through the barrier metal 23 on the interlayer insulating film 4 covering the gate line 18. The gate runner 19 is connected to the gate line 18 through the barrier metal 23 and contact holes formed in the interlayer insulating film 4.
A first passivation film 20 made of a material other than an organic resin is formed to cover the gate runner 19 and a part of the emitter electrode 14 that is a metal electrode. Furthermore, a second passivation film 21 made of an organic resin is formed on the first passivation film 20 to cover a part of the emitter electrode 14 through the first passivation film 20. The first passivation film 20 is made of a material with which copper is less likely to diffuse. A silicon nitride (SiN) film is used as the material of the first passivation film 20 in Embodiment 1. Examples of the material of the first passivation film 20 may include a semi-insulating film containing nitrogen (N) and an oxidized film containing silicon (Si), besides the SiN film.
An Ni layer 24 made of nickel (Ni) is formed on the emitter electrode 14. The Ni layer 24 is connected to a portion of the emitter electrode 14 that is not covered with the first passivation film 20. An end of the Ni layer 24 sits on the first passivation film 20. The second passivation film 21 is separated from the Ni layer 24. Furthermore, an Au layer 25 made of gold (Au) is formed on the Ni layer 24. In Embodiment 1, a laminated structure of the emitter electrode 14, the Ni layer 24, and the Au layer 25 forms a top electrode of the semiconductor element 41. In other words, the top electrode according to Embodiment 1 includes the laminated structure obtained by laminating, in this order, the Au layer 25, the Ni layer 24, and the emitter electrode 14 that is an Al layer or an AlSi layer from its upper surface (a surface to which a conductive metal plate 22 to be described later is to be bonded).
The Ni layer 24 is approximately 2 μm to 15 μm thick (a vertical dimension on the plane of the paper in
Although
The conductive metal plate 22 is solid-phase diffusion bonded to the Au layer 25 as the top layer of the top electrode. The conductive metal plate 22 is plate-shaped, and contains Cu or a conductive metal containing Cu as a main component, such as a copper slab, a copper alloy, or a copper composite (with a copper/invar/copper (CIC) structure). The conductive metal plate 22 is approximately 0.01 mm to 1.0 mm thick. The surface (sheath) of the conductive metal plate 22 is not plated but is made of copper or a copper alloy. Thus, the surface of the conductive metal plate 22 does not contain a metal, except copper or a copper alloy. The surface of the conductive metal plate 22 may be covered with an anti-corrosive material through an anti-corrosive process.
The metal wire 47b is wire bonded to the upper surface of the conductive metal plate 22. The metal wire 47b preferably contains a material identical to that of the conductive metal plate 22 in view of higher reliability and longer life.
The conductive metal plate 22 is smaller in plane size (area) than the top electrode. Here, the conductive metal plate 22 is smaller in plane size than the Au layer 25 as the top layer of the top electrode (a layer to which the conductive metal plate 22 is bonded). In other words, the conductive metal plate 22 is positioned without extending beyond the top electrode. This facilitates the positioning of the conductive metal plate 22 with respect to the Au layer 25 when the conductive metal plate 22 is solid-phase diffusion bonded to the Au layer 25, and prevents a contact (conduction) of the conductive metal plate 22 with the other electrodes on the semiconductor element 41.
Upon receipt of the loads and the ultrasonic vibrations from the ultrasonic tool, the upper surfaces of the conductive metal plates 22 receive ultrasonic energy to the extent that traces of the ultrasonic tool remain. Thus, atoms of the conductive metal plates 22 and the Au layers 25 diffuse to give the bonded portions 33 between the conductive metal plates 22 and the Au layers 25 sufficient bonding strength. This produces the bonded portions 33 with higher reliability. The metal wires 47 may be bonded in the same method.
The size of each of the bonded portions 33 between the conductive metal plates 22 and the Au layers 25 varies, depending on the size of the ultrasonic tool.
The vibration direction of the ultrasonic vibrations of the ultrasonic tool is a horizontal direction with respect to the contact surface between the conductive metal plate 22 and the Au layer 25. The ultrasonic tool can apply the ultrasonic vibrations in the horizontal direction (X direction) or the vertical direction (Y direction) on the plane of the paper in each of
In the semiconductor device 100 according to Embodiment 1, the top electrode of the semiconductor element 41 is not Cu plated, but the conductive metal plate 22 is solid-phase diffusion bonded to the top electrode. This can suppress an increase in the production costs. The metal wires 47 are bonded to the conductive metal plate 22. This causes fewer breaks from lift-off (peels) of wires than those in directly bonding a metal wire to a top electrode, and can contribute to higher reliability and longer life of semiconductor devices. Furthermore, the conductive metal plate 22 is a plate component whose thickness can be easily managed. Thus, the conductive metal plate 22 never suffers from non-uniform thicknesses or variations in appearance as seen in Cu plating.
Next, a method of manufacturing the semiconductor device 100 according to Embodiment 1, particularly, a step for solid-phase diffusion bonding the conductive metal plates 22 to the semiconductor element 41 will be described with reference to the flowchart in
First, an ultrasonic tool is attached to an ultrasonic bonding apparatus. Then, a semifinished product obtained by bonding the semiconductor element 41 to the insulating substrate 43, and the conductive metal plates 22 are prepared (Step S101). Here, the conductive metal plates 22 corresponding to the number of the top electrodes of the semiconductor element 41 are prepared.
The insulating substrate 43 on which the semiconductor element 41 is mounted is secured to a stage of the ultrasonic bonding apparatus by adsorption or using a pressure jig, so that the conductive metal plates 22 are mounted on the top electrodes of the semiconductor element 41. Then, the ultrasonic tool is moved downward in a direction vertical to the conductive metal plates 22 (Z direction) to press the ultrasonic tool to the conductive metal plates 22 and apply loads on the conductive metal plates 22. Thereby, the conductive metal plates 22 are fixedly held on the top electrodes of the semiconductor element 41 (Step S102). If the ultrasonic bonding apparatus includes a camera and an image recognition function and can monitor and automatically control the ultrasonic tool or operations on the stage using the camera and the image recognition function, Step S102 can be automatically performed.
Then, with application of ultrasonic vibrations and loads on the conductive metal plates 22 using the ultrasonic tool, the conductive metal plates 22 are solid-phase diffusion bonded to the top electrodes of the semiconductor element 41 (Step S103). Step S103 may be performed while the conductive metal plates 22 are heated. This increases the bonding energy given to the conductive metal plates 22 to produce the tighter bonded portions 33. However, heating is a main factor of enhancing the oxidation. Thus, when Step S103 is performed with the conductive metal plates 22 being heated, it is preferred to perform Step S103 with an inert gas such as nitrogen being injected or to perform Step S103 in an inert gas atmosphere.
As illustrated in
After the solid-phase diffusion bonding is completed, the ultrasonic tool is moved upward and separated from the conductive metal plates 22. Then, air is blown to remove metal cuttings scattered on the insulating substrate 43, the semiconductor element 41, and the conductive metal plates 22 (Step S104). The metal cuttings are minute ones produced by application of the ultrasonic vibrations and the loads on the conductive metal plates 22 using the ultrasonic tool. For example, when the conductive metal plates 22 are made of Cu, minute Cu cuttings are produced.
The loads and the ultrasonic vibrations may be applied to the conductive metal plates 22 in two steps as stepped waveforms. For example, the ultrasonic vibrations may be applied with a smaller load in the first half of the solid-phase diffusion bonding step, and the ultrasonic vibrations may be applied with a larger load in the latter half.
After completion of blowing air, a visual inspection is conducted to confirm the presence of a split in the semiconductor element 41 and the presence of remaining metal cuttings (Step S105). If the ultrasonic bonding apparatus includes a camera and an image recognition function and can conduct the visual inspection using the camera and the image recognition function, Step S105 can be automatically performed. Furthermore, an automatic visual inspection apparatus separate from the ultrasonic bonding apparatus may be used.
If a plurality of semiconductor elements 41 are mounted on the insulating substrate 43 and any one of the semiconductor elements 41 is damaged in the solid-phase diffusion bonding step (Step S103) and becomes a defective part in the procedure of
After completion of the procedure of
Since no bonding material or plating is interposed between the top electrode of the semiconductor element 41 and the conductive metal plate 22 in Embodiment 1, the conductive metal plate 22 is disposed parallel to the top electrode of the semiconductor element 41. This facilitates the bonding of the metal wire 47b, and thereby produces advantages of reducing damages to the semiconductor element 41 and peels of wires.
Although
As illustrated in
As illustrated in
The structures in
Although
Depending on use conditions of the semiconductor device 100, it is probable that an operating temperature of the semiconductor element 41 exceeds a rated value, the switching performance of the semiconductor element 41 decreases, and the semiconductor element 41 thermally runs away and is destroyed at worst. The insulating substrate 43 having a higher thermal conductivity is preferably used for preventing the operating temperature of the semiconductor element 41 from exceeding the rated value. As illustrated in
The insulating substrate 43 and the cooler 50 may be integrated. The integration can omit the heat radiation material 49, and reduce the thermal resistance between the insulating substrate 43 and the cooler 50. This further improves the cooling performance of the semiconductor element 41.
The structure in
When the conductive metal plate 22 is solid-phase diffusion bonded to the emitter electrode 14 in the structure in
Embodiment 2 can reduce the number of manufacturing processes, the number of materials, and the manufacturing cost of the semiconductor device 100 by omitting the Ni layer 24 and the Au layer 25.
The whole structure and the manufacturing method of the semiconductor device 100 according to Embodiment 2 may be basically identical to those according to Embodiment 1.
In Embodiment 3, the metal wire 47b for connecting the top electrode of the semiconductor element 41 and the electrode terminals 46 shown in
As illustrated in
The whole structure and the manufacturing method of the semiconductor device 100 according to Embodiment 3 may be basically identical to those according to Embodiment 1.
Embodiment 4 will describe a power conversion device to which the semiconductor devices according to Embodiments 1 to 3 are applied. Although the power conversion device according to Embodiment 4 is not limited to a specific power conversion device, Embodiment 4 will describe application of the semiconductor devices according to Embodiments 1 to 3 to a three-phase inverter.
The power conversion device 220, which is a three-phase inverter connected between the power supply 210 and the load 230, converts the DC power supplied from the power supply 210 into the AC power to supply the AC power to the load 230. As illustrated in
The load 230 is a three-phase electrical motor driven by the AC power supplied from the power conversion device 220. The load 230 is not limited to specific use but is an electrical motor mounted on various types of electrical devices. Thus, the load 230 is used as an electrical motor for, for example, a hybrid car, an electrical car, a rail vehicle, an elevator, or air-conditioning equipment.
The power conversion device 220 will be described in detail hereinafter. The main conversion circuit 221 includes switching elements and free-wheeling diodes (not illustrated). Switching of the switching element causes the DC power supplied from the power supply 210 to be converted into the AC power. The main conversion circuit 221 then supplies the AC power to the load 230. The specific circuit configuration of the main conversion circuit 221 is of various types. The main conversion circuit 221 according to Embodiment 4 is a three-phase full-bridge circuit having two levels, and includes six switching elements and six free-wheeling diodes anti-parallel connected to the respective switching elements. The semiconductor device 100 according to any one of Embodiments 1 to 3 is applied to each of the switching elements of the main conversion circuit 221. Embodiment 4 will describe the switching elements of the main conversion circuit 221 to each of which the semiconductor device 100 according to Embodiment 1 has been applied. The six switching elements form three pairs of upper and lower arms in each pair of which the two switching elements are serially connected to each other. The three pairs of upper and lower arms form the respective phases (U-phase, V-phase, and W-phase) of the full-bridge circuit. Output terminals of the respective pairs of upper and lower arms, i.e., three output terminals of the main conversion circuit 221 are connected to the load 230.
The drive circuit 222 generates drive signals for driving the switching elements of the main conversion circuit 221, and supplies the drive signals to control electrodes of the switching elements of the main conversion circuit 221. Specifically, the drive circuit 222 outputs the drive signal for switching each of the switching elements to an ON state and the drive signal for switching the switching element to an OFF state, to the control electrode of the switching element in accordance with the control signal from the control circuit 223 to be described later. When the switching element is kept in the ON state, the drive signal is a voltage signal (ON signal) higher than or equal to a threshold voltage of the switching element. When the switching element is kept in the OFF state, the drive signal is a voltage signal (OFF signal) lower than or equal to the threshold voltage of the switching element.
The control circuit 223 controls the switching elements of the main conversion circuit 221 to supply a desired power to the load 230. Specifically, the control circuit 223 calculates a time (ON time) when each of the switching elements of the main conversion circuit 221 needs to enter the ON state, based on the power which needs to be supplied to the load 230. For example, the control circuit 223 can control the main conversion circuit 221 by performing PWN control for modulating the ON time of the switching elements in accordance with the voltage which needs to be output. Then, the control circuit 223 outputs a control instruction (control signal) to the drive circuit 222 so that the drive circuit 222 outputs the ON signal to the switching element which needs to enter the ON state and outputs the OFF signal to the switching element which needs to enter the OFF state at each time. The drive circuit 222 outputs the ON signal or the OFF signal as the drive signal to the control electrode of each of the switching elements in accordance with this control signal.
Since the power semiconductor devices according to Embodiments 1 to 3 are applied as the switching elements of the main conversion circuit 221 in the power conversion device 220 according to Embodiment 4, the reliability can be enhanced.
Although Embodiment 4 describes the power conversion device 220 having the two levels, Embodiment 4 is not limited to this but can be applied to various power conversion devices 220. Although Embodiment 4 describes the power conversion device 220 having the two levels, the power conversion device 220 may have three or multiple levels. Embodiments 1 to 3 may be applied to a single-phase inverter when the power is supplied to the single-phase load 230. Embodiments 1 to 3 are also applicable to a DC/DC converter or an AC/DC converter when the power is supplied to, for example, the DC load 230.
The load 230 for the power conversion device 220 to which the semiconductor devices 100 according to Embodiments 1 to 3 are applied is not limited to an electrical motor. The power conversion device 220 is also applicable as a power-supply device of an electrical discharge machine, a laser beam machine, an induction heat cooking device, or a non-contact power feeding system, and is further applicable as a power conditioner of, for example, a solar power system or an electricity storage system.
Embodiments can be freely combined, and appropriately modified or omitted.
The following will describe a summary of various aspects of the present disclosure as appendixes.
A semiconductor device, comprising:
The semiconductor device according to appendix 1,
The semiconductor device according to appendix 2,
The semiconductor device according to appendix 3,
The semiconductor device according to appendix 1,
The semiconductor device according to appendix 5,
The semiconductor device according to one of appendixes 1 to 6,
The semiconductor device according to one of appendixes 1 to 7,
The semiconductor device according to one of appendixes 1 to 8, comprising
The semiconductor device according to one of appendixes 1 to 9,
The semiconductor device according to one of appendixes 1 to 10, comprising
The semiconductor device according to one of appendixes 1 to 10,
The semiconductor device according to one of appendixes 1 to 12,
The semiconductor device according to one of appendixes 1 to 13,
A power conversion device, comprising:
A method of manufacturing a semiconductor device, the method comprising:
The method according to appendix 16,
While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-169074 | Oct 2022 | JP | national |
