Isolated zones

Industry

CPC
Y10S148/086

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10USPC classification Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10S148/00Metal treatment

Current Industry

Y10S148/086Isolated zones

Industries

Patents Grantslast 30 patents

Information Patent Grant
Method for manufacturing dielectrics dividing wafer with isolated r...
- Patent number 5,496,760
- Issue date Mar 5, 1996
- Fuji Electric Company, Ltd.
- Kazuo Matsuzaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a bipolar transistor having a high ion concen...
- Patent number 5,389,563
- Issue date Feb 14, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Takashi Kuroi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectrics dividing wafer
- Patent number 5,381,033
- Issue date Jan 10, 1995
- Fuji Electric Company, Ltd.
- Kazuo Matsuzaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bipolar transistor having a high ion concentration buried floating...
- Patent number 5,341,022
- Issue date Aug 23, 1994
- Mitsubishi Denki Kabushiki Kaisha
- Takashi Kuroi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming late isolation with polishing
- Patent number 5,225,358
- Issue date Jul 6, 1993
- LSI Logic Corporation
- Nicholas F. Pasch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making integrated circuit with high current transistor an...
- Patent number 5,045,492
- Issue date Sep 3, 1991
- Allegro Microsystems, Inc.
- Wing K. Huie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Maximum areal density recessed oxide isolation (MADROX) process
- Patent number 5,039,625
- Issue date Aug 13, 1991
- MCNC
- Arnold Reisman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming SOI film
- Patent number 4,874,718
- Issue date Oct 17, 1989
- Mitsubishi Denki Kabushiki Kaisha
- Yasuo Inoue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for forming planarized gate structure
- Patent number 4,818,725
- Issue date Apr 4, 1989
- Harris Corp.
- Richard L. Lichtel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for elimination of polysilicon stringers in direct moat f...
- Patent number 4,702,000
- Issue date Oct 27, 1987
- Harris Corporation
- Dyer A. Matlock
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for reducing substrate warpage springback using a polysil...
- Patent number 4,631,804
- Issue date Dec 30, 1986
- AT&T Bell Laboratories
- Pradip K. Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Monolithic integrated circuit structure and method of fabrication
- Patent number 4,593,459
- Issue date Jun 10, 1986
- GTE Laboratories Incorporated
- Paul E. Poppert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal silicide channel stoppers for integrated circuits and method...
- Patent number 4,589,193
- Issue date May 20, 1986
- International Business Machines Corporation
- George R. Goth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making an integrated circuit
- Patent number 4,583,281
- Issue date Apr 22, 1986
- General Electric Company
- Mario Ghezzo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating dielectrically isolated devices utilizing h...
- Patent number 4,581,814
- Issue date Apr 15, 1986
- AT&T Bell Laboratories
- George K. Celler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduction of field oxide encroachment in MOS fabrication
- Patent number 4,577,394
- Issue date Mar 25, 1986
- National Semiconductor Corporation
- John L. Peel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for self-aligned buried layer, channel-stop, and isolation
- Patent number 4,574,469
- Issue date Mar 11, 1986
- Motorola, Inc.
- Sal Mastroianni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit fabrication method utilizing selective etching a...
- Patent number 4,561,172
- Issue date Dec 31, 1985
- Texas Instruments Incorporated
- Christopher Slawinski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor structures having an oxidized...
- Patent number 4,532,700
- Issue date Aug 6, 1985
- International Business Machines Corporation
- Wayne I. Kinney
- H01 - BASIC ELECTRIC ELEMENTS

Isolated zones

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method for manufacturing dielectrics dividing wafer with isolated r...

Method of fabricating a bipolar transistor having a high ion concen...

Dielectrics dividing wafer

Bipolar transistor having a high ion concentration buried floating...

Method of forming late isolation with polishing

Method of making integrated circuit with high current transistor an...

Maximum areal density recessed oxide isolation (MADROX) process

Method for forming SOI film

Technique for forming planarized gate structure

Technique for elimination of polysilicon stringers in direct moat f...

Technique for reducing substrate warpage springback using a polysil...

Monolithic integrated circuit structure and method of fabrication

Metal silicide channel stoppers for integrated circuits and method...

Method of making an integrated circuit

Process for fabricating dielectrically isolated devices utilizing h...

Reduction of field oxide encroachment in MOS fabrication

Process for self-aligned buried layer, channel-stop, and isolation

Integrated circuit fabrication method utilizing selective etching a...

Method of manufacturing semiconductor structures having an oxidized...