Simultaneous diffusion

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CPC
Y10S148/151

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YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10USPC classification Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10S148/00Metal treatment

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Y10S148/151Simultaneous diffusion

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Patents Grantslast 30 patents

Information Patent Grant
Lateral trench MISFET and method of manufacturing the same
- Patent number 5,885,878
- Issue date Mar 23, 1999
- Fuji Electric Co., Ltd.
- Naoto Fujishima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral trench MISFET
- Patent number 5,701,026
- Issue date Dec 23, 1997
- Fuji Electric Co., Ltd.
- Naoto Fujishima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDMOS transistor with self-aligned source/backgate and photo-aligne...
- Patent number 5,491,105
- Issue date Feb 13, 1996
- Texas Instruments Incorporated
- Michael C. Smayling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for controlling electrical breakdown in semiconductor power...
- Patent number 5,434,095
- Issue date Jul 18, 1995
- Sundstrand Corporation
- Theodore G. Hollinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDMOS transistor with self-aligned source/backgate and photo-aligne...
- Patent number 5,348,895
- Issue date Sep 20, 1994
- Texas Instruments Incorporated
- Michael C. Smayling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming doped regions within a semiconductor substrate
- Patent number 5,300,454
- Issue date Apr 5, 1994
- Motorola, Inc.
- Robert C. Taft
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making LDMOS transistor with self-aligned source/backgate...
- Patent number 5,242,841
- Issue date Sep 7, 1993
- Texas Instruments Incorporated
- Michael C. Smayling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with doped electrical breakdown control region
- Patent number 5,231,474
- Issue date Jul 27, 1993
- Advanced Power Technology, Inc.
- Theodore G. Hollinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench isolation process
- Patent number 5,206,182
- Issue date Apr 27, 1993
- United Technologies Corporation
- Guy R. Freeman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making semiconductor IC including polar transistors
- Patent number 5,066,602
- Issue date Nov 19, 1991
- Matsushita Electric Industrial Co., Ltd.
- Toyoki Takemoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming emitters in a BiCMOS process
- Patent number 5,047,357
- Issue date Sep 10, 1991
- Texas Instruments Incorporated
- Robert H. Eklund
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of producing a semiconductor laser
- Patent number 4,980,313
- Issue date Dec 25, 1990
- Mitsubishi Denki Kabushiki Kaisha
- Shogo Takahashi
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method of manufacturing semiconductor device isolation
- Patent number 4,897,363
- Issue date Jan 30, 1990
- Mitsubishi Denki Kabushiki Kaisha
- Kakutaro Suda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of isolating a semiconductor device using local oxidation
- Patent number 4,840,920
- Issue date Jun 20, 1989
- Mitsubishi Denki Kabushiki Kaisha
- Kakutaro Suda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making bipolar transistors
- Patent number 4,826,780
- Issue date May 2, 1989
- Matsushita Electric Industrial Co., Ltd.
- Toyoki Takemoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing semiconductor BICMOS device
- Patent number 4,824,796
- Issue date Apr 25, 1989
- American Telephone and Telegraph Company
- Tzu-Yin Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing semiconductor BICMOS device
- Patent number 4,784,971
- Issue date Nov 15, 1988
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- Tzu-Yin Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making bipolar transistor having a graft-base configuration
- Patent number 4,662,062
- Issue date May 5, 1987
- Matsushita Electronics Corporation
- Tetsuo Toyooka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of manufacturing a high frequency bipolar transistor utiliz...
- Patent number 4,586,968
- Issue date May 6, 1986
- Le Silicium Semiconducteur SSC
- Augustin Coello-Vera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device utilizing simultaneo...
- Patent number 4,569,123
- Issue date Feb 11, 1986
- Kabushiki Kaisha Toshiba
- Tetsuo Ishii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
I.sup.2 L Structure and fabrication process compatible with high vo...
- Patent number 4,546,539
- Issue date Oct 15, 1985
- Harris Corporation
- James D. Beasom
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for aligning diffusion masks with respect to isolating wall...
- Patent number 4,369,561
- Issue date Jan 25, 1983
- Thomson-CSF
- Eugene Tonnel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Negative-resistance semiconductor device
- Patent number 4,064,525
- Issue date Dec 20, 1977
- Matsushita Electric Industrial Co., Ltd.
- Gota Kano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of forming silicon solar energy cell having improved back co...
- Patent number 4,056,879
- Issue date Nov 8, 1977
- Solarex Corporation
- Joseph Lindmayer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor integrated circuit device h...
- Patent number 4,053,336
- Issue date Oct 11, 1977
- Ferranti Limited
- David Latham Grundy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Capacitance circuit
- Patent number 4,025,802
- Issue date May 24, 1977
- Hitachi, Ltd.
- Fumihito Inoue
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for fabricating semiconductor devices utilizing oxide protec...
- Patent number 4,018,627
- Issue date Apr 19, 1977
- Signetics Corporation
- Bohumil Polata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming a low resistance interconnect in MOS N-channel...
- Patent number 4,013,489
- Issue date Mar 22, 1977
- Intel Corporation
- William G. Oldham
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device
- Patent number 4,009,057
- Issue date Feb 22, 1977
- U.S. Philips Corporation
- Michel DE Brebisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of selective growth of microcrystalline silicon
- Patent number 4,004,954
- Issue date Jan 25, 1977
- RCA Corporation
- Donald Richard Tshudy
- H01 - BASIC ELECTRIC ELEMENTS

Simultaneous diffusion

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Lateral trench MISFET and method of manufacturing the same

Lateral trench MISFET

LDMOS transistor with self-aligned source/backgate and photo-aligne...

Method for controlling electrical breakdown in semiconductor power...

LDMOS transistor with self-aligned source/backgate and photo-aligne...

Method for forming doped regions within a semiconductor substrate

Method of making LDMOS transistor with self-aligned source/backgate...

Semiconductor device with doped electrical breakdown control region

Trench isolation process

Method of making semiconductor IC including polar transistors

Method for forming emitters in a BiCMOS process

Method of producing a semiconductor laser

Method of manufacturing semiconductor device isolation

Method of isolating a semiconductor device using local oxidation

Method of making bipolar transistors

Process for manufacturing semiconductor BICMOS device

Process for manufacturing semiconductor BICMOS device

Method for making bipolar transistor having a graft-base configuration

Process of manufacturing a high frequency bipolar transistor utiliz...

Method of manufacturing a semiconductor device utilizing simultaneo...

I.sup.2 L Structure and fabrication process compatible with high vo...

Process for aligning diffusion masks with respect to isolating wall...

Negative-resistance semiconductor device

Method of forming silicon solar energy cell having improved back co...

Method of manufacturing a semiconductor integrated circuit device h...

Capacitance circuit

Method for fabricating semiconductor devices utilizing oxide protec...

Process for forming a low resistance interconnect in MOS N-channel...

Method of manufacturing a semiconductor device

Method of selective growth of microcrystalline silicon

Patents Applicationslast 30 patents