the bonding area being disposed in a recess of the surface of the body

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/08111the bonding area being disposed in a recess of the surface of the body

Industries

Patents Grantslast 30 patents

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Information Patent Grant
Method of forming package structure
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- Issue date Nov 14, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
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Information Patent Grant
Packaging mechanisms for dies with different sizes of connectors
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- Issue date Nov 1, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chih-Hua Chen
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Information Patent Grant
Semiconductor packages and methods of forming same
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Dual-interface IC card module
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- Jing-Cheng Lin
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Information Patent Grant
Semiconductor device, manufacturing method, and solid-state imaging...
- Patent number 11,018,110
- Issue date May 25, 2021
- SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Akiko Hirata
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Information Patent Grant
Packaging mechanisms for dies with different sizes of connectors
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- Issue date Mar 30, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chih-Hua Chen
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Information Patent Grant
Method and structure of three-dimensional chip stacking
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Information Patent Grant
Semiconductor packages and methods of forming same
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Information Patent Grant
Increased contact alignment tolerance for direct bonding
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- Issue date Mar 31, 2020
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Information Patent Grant
Method and structure of three-dimensional chip stacking
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Information Patent Grant
Dual-interface IC card module
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Information Patent Grant
Package structure and method of forming thereof
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- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device having a redistribution area
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- Issue date Oct 24, 2017
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Information Patent Grant
Stacked dies with wire bonds and method
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- Issue date Nov 29, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package, fabrication method therefor, and package-on...
- Patent number 9,502,391
- Issue date Nov 22, 2016
- NEPES CO., LTD.
- Yong-Tae Kwon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and stacked semiconductor package having the...
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- Issue date Jun 30, 2015
- SK Hynix Inc.
- Jae Sung Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional integrated structure capable of detecting a tempe...
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- Issue date Nov 18, 2014
- STMicroelectronics (Crolles 2) SAS
- Laurent-Luc Chapelon
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Information Patent Grant
Semiconductor package and stacked semiconductor package having the...
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- SK Hynix Inc.
- Jae Sung Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and stacked semiconductor package having the...
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- Issue date Oct 30, 2012
- Hynix Semiconductor Inc.
- Jae Sung Oh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
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- Yongguo CHEN
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SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
- Publication number 20230411326
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LOW TEMPERATURE DIRECT BONDING
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- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
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- H01 - BASIC ELECTRIC ELEMENTS
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EXPANSION CONTROL FOR BONDING
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- Publication date Sep 21, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
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PACKAGE STRUCTURE WITH WETTABLE SIDE SURFACE AND MANUFACTURING METH...
- Publication number 20220392862
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- Zhuhai ACCESS Semiconductor Co., Ltd
- Xianming CHEN
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Semiconductor Packages and Methods of Forming Same
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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
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- Seungyeol Oh
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Packaging Mechanisms for Dies with Different Sizes of Connectors
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Method for Producing a Connection Between Component Parts, and Comp...
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- Publication date Sep 17, 2020
- OSRAM OLED GmbH
- Simeon Katz
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SEMICONDUCTOR DEVICE FOR BONDING CONDUCTIVE LAYERS EXPOSED FROM SUR...
- Publication number 20200126941
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- Toshiba Memory Corporation
- Atsuko KAWASAKI
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SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, AND SOLID-STATE IMAGING...
- Publication number 20200035643
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- Sony Semiconductor Solutions Corporation
- AKIKO HIRATA
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DUAL-INTERFACE IC CARD MODULE
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- NXP B.V.
- CHRISTIAN ZENZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKAGE STRUCTURE AND METHOD OF FORMING THEREOF
- Publication number 20180151546
- Publication date May 31, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jing-Cheng LIN
- H01 - BASIC ELECTRIC ELEMENTS
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DUAL-INTERFACE IC CARD MODULE
- Publication number 20170092612
- Publication date Mar 30, 2017
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- MEDIATEK INC.
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ELECTRONIC DEVICE HAVING A REDISTRIBUTION AREA
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- NEPES CO., LTD.
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PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME
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- SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
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SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...
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- Jae Sung OH
- H01 - BASIC ELECTRIC ELEMENTS
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THREE-DIMENSIONAL INTEGRATED STRUCTURE CAPABLE OF DETECTING A TEMPE...
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SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...
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- Hynix Semiconductor Inc.
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SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...
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- Publication date Mar 25, 2010
- Jae Sung OH
- H01 - BASIC ELECTRIC ELEMENTS

the bonding area being disposed in a recess of the surface of the body

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method for producing a connection between component parts, and comp...

Method of forming package structure

Packaging mechanisms for dies with different sizes of connectors

Semiconductor packages and methods of forming same

Dual-interface IC card module

Method of forming package structure

Semiconductor device, manufacturing method, and solid-state imaging...

Packaging mechanisms for dies with different sizes of connectors

Method and structure of three-dimensional chip stacking

Semiconductor device for bonding conductive layers exposed from sur...

Semiconductor packages and methods of forming same

Increased contact alignment tolerance for direct bonding

Method and structure of three-dimensional chip stacking

Dual-interface IC card module

Package structure and method of forming thereof

Electronic device having a redistribution area

Stacked dies with wire bonds and method

Semiconductor package, fabrication method therefor, and package-on...

Semiconductor package and stacked semiconductor package having the...

Three-dimensional integrated structure capable of detecting a tempe...

Semiconductor package and stacked semiconductor package having the...

Semiconductor package and stacked semiconductor package having the...

Patents Applicationslast 30 patents

POWER CONVERTER APPARATUS

BUFFER CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING THE BUFFER CHIP AN...

SEMICONDUCTOR STRUCTURE

HEATSINK FOR RING TYPE INTEGRATED CIRCUITS

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

LOW TEMPERATURE DIRECT BONDING

EXPANSION CONTROL FOR BONDING

PACKAGE STRUCTURE WITH WETTABLE SIDE SURFACE AND MANUFACTURING METH...

Semiconductor Packages and Methods of Forming Same

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Packaging Mechanisms for Dies with Different Sizes of Connectors

Semiconductor Packages and Methods of Forming Same

Method for Producing a Connection Between Component Parts, and Comp...

SEMICONDUCTOR DEVICE FOR BONDING CONDUCTIVE LAYERS EXPOSED FROM SUR...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, AND SOLID-STATE IMAGING...

DUAL-INTERFACE IC CARD MODULE

PACKAGE STRUCTURE AND METHOD OF FORMING THEREOF

DUAL-INTERFACE IC CARD MODULE

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

ELECTRONIC DEVICE HAVING A REDISTRIBUTION AREA

Method of Manufacturing Semiconductor Device and Semiconductor Device

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Stacked Dies With Wire Bonds and Method

SEMICONDUCTOR PACKAGE, FABRICATION METHOD THEREFOR, AND PACKAGE-ON...

ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHO...

PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...

THREE-DIMENSIONAL INTEGRATED STRUCTURE CAPABLE OF DETECTING A TEMPE...

SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...

SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...