the bonding area being disposed in a recess of the surface of the body

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

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H01L2224/08111the bonding area being disposed in a recess of the surface of the body

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Patents Grantslast 30 patents

Information Patent Grant
Method for producing a connection between component parts, and comp...
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Information Patent Grant
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Information Patent Grant
Packaging mechanisms for dies with different sizes of connectors
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Semiconductor packages and methods of forming same
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Semiconductor device, manufacturing method, and solid-state imaging...
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- SONY SEMICONDUCTOR SOLUTIONS CORPORATION
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Information Patent Grant
Packaging mechanisms for dies with different sizes of connectors
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Information Patent Grant
Method and structure of three-dimensional chip stacking
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Semiconductor device for bonding conductive layers exposed from sur...
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Information Patent Grant
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Information Patent Grant
Increased contact alignment tolerance for direct bonding
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Information Patent Grant
Method and structure of three-dimensional chip stacking
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Information Patent Grant
Dual-interface IC card module
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Information Patent Grant
Package structure and method of forming thereof
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
Semiconductor package, fabrication method therefor, and package-on...
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Information Patent Grant
Semiconductor package and stacked semiconductor package having the...
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Three-dimensional integrated structure capable of detecting a tempe...
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Semiconductor package and stacked semiconductor package having the...
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Information Patent Grant
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Patents Applicationslast 30 patents

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LOW TEMPERATURE DIRECT BONDING
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- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
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EXPANSION CONTROL FOR BONDING
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- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
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Packaging Mechanisms for Dies with Different Sizes of Connectors
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- Toshiba Memory Corporation
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SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, AND SOLID-STATE IMAGING...
- Publication number 20200035643
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- AKIKO HIRATA
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DUAL-INTERFACE IC CARD MODULE
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- NXP B.V.
- CHRISTIAN ZENZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKAGE STRUCTURE AND METHOD OF FORMING THEREOF
- Publication number 20180151546
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- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jing-Cheng LIN
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DUAL-INTERFACE IC CARD MODULE
- Publication number 20170092612
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SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
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- MEDIATEK INC.
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ELECTRONIC DEVICE HAVING A REDISTRIBUTION AREA
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Method of Manufacturing Semiconductor Device and Semiconductor Device
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- RENESAS ELECTRONICS CORPORATION
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Stacked Dies With Wire Bonds and Method
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ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHO...
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PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME
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- SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
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SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...
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- Jae Sung OH
- H01 - BASIC ELECTRIC ELEMENTS
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THREE-DIMENSIONAL INTEGRATED STRUCTURE CAPABLE OF DETECTING A TEMPE...
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- Laurent-Luc Chapelon
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Information Patent Application
SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...
- Publication number 20130026651
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- Hynix Semiconductor Inc.
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SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...
- Publication number 20100072598
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- Jae Sung OH
- H01 - BASIC ELECTRIC ELEMENTS

the bonding area being disposed in a recess of the surface of the body

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method for producing a connection between component parts, and comp...

Method of forming package structure

Packaging mechanisms for dies with different sizes of connectors

Semiconductor packages and methods of forming same

Dual-interface IC card module

Method of forming package structure

Semiconductor device, manufacturing method, and solid-state imaging...

Packaging mechanisms for dies with different sizes of connectors

Method and structure of three-dimensional chip stacking

Semiconductor device for bonding conductive layers exposed from sur...

Semiconductor packages and methods of forming same

Increased contact alignment tolerance for direct bonding

Method and structure of three-dimensional chip stacking

Dual-interface IC card module

Package structure and method of forming thereof

Electronic device having a redistribution area

Stacked dies with wire bonds and method

Semiconductor package, fabrication method therefor, and package-on...

Semiconductor package and stacked semiconductor package having the...

Three-dimensional integrated structure capable of detecting a tempe...

Semiconductor package and stacked semiconductor package having the...

Semiconductor package and stacked semiconductor package having the...

Patents Applicationslast 30 patents

POWER CONVERTER APPARATUS

BUFFER CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING THE BUFFER CHIP AN...

SEMICONDUCTOR STRUCTURE

HEATSINK FOR RING TYPE INTEGRATED CIRCUITS

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

LOW TEMPERATURE DIRECT BONDING

EXPANSION CONTROL FOR BONDING

PACKAGE STRUCTURE WITH WETTABLE SIDE SURFACE AND MANUFACTURING METH...

Semiconductor Packages and Methods of Forming Same

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Packaging Mechanisms for Dies with Different Sizes of Connectors

Semiconductor Packages and Methods of Forming Same

Method for Producing a Connection Between Component Parts, and Comp...

SEMICONDUCTOR DEVICE FOR BONDING CONDUCTIVE LAYERS EXPOSED FROM SUR...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, AND SOLID-STATE IMAGING...

DUAL-INTERFACE IC CARD MODULE

PACKAGE STRUCTURE AND METHOD OF FORMING THEREOF

DUAL-INTERFACE IC CARD MODULE

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SEMICONDUCTOR PACKAGE, FABRICATION METHOD THEREFOR, AND PACKAGE-ON...

ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHO...

PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...

THREE-DIMENSIONAL INTEGRATED STRUCTURE CAPABLE OF DETECTING A TEMPE...

SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...

SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE...