the devices having the same size and there being no auxiliary carrier between the devices

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H01L2225/06565

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups

Current Industry

H01L2225/06565the devices having the same size and there being no auxiliary carrier between the devices

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Thermocompression bonding with passivated silver-based contacting m...
- Patent number 12,363,878
- Issue date Jul 15, 2025
- SET North America, LLC
- Eric Frank Schulte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermocompression bonding with passivated gold contacting metal
- Patent number 12,363,877
- Issue date Jul 15, 2025
- SET North America, LLC
- Eric Frank Schulte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermocompression bonding with passivated tin-based contacting metal
- Patent number 12,356,553
- Issue date Jul 8, 2025
- SET North America, LLC
- Eric Frank Schulte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Signal routing between memory die and logic die for performing oper...
- Patent number 12,354,649
- Issue date Jul 8, 2025
- Micron Technology, Inc.
- Aliasger T. Zaidy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor package
- Patent number 12,354,980
- Issue date Jul 8, 2025
- Samsung Electronics Co., Ltd.
- Boin Noh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and method of fabricating the same
- Patent number 12,355,005
- Issue date Jul 8, 2025
- Samsung Electronics Co., Ltd.
- Jongho Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor circuit structure with direct die heat removal structure
- Patent number 12,341,077
- Issue date Jun 24, 2025
- INVENTION AND COLLABORATION LABORATORY, INC.
- Chao-Chun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing semiconductor device including resin layers
- Patent number 12,341,024
- Issue date Jun 24, 2025
- Kioxia Corporation
- Eiji Takano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor circuit structure with direct die heat removal structure
- Patent number 12,341,076
- Issue date Jun 24, 2025
- INVENTION AND COLLABORATION LABORATORY, INC.
- Chao-Chun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices and manufacturing methods of the same
- Patent number 12,334,471
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Hyun Mog Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked semiconductor device
- Patent number 12,327,818
- Issue date Jun 10, 2025
- TOHOKU-MICROTEC CO., LTD.
- Makoto Motoyoshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside contact for thermal displacement in a multi-wafer stacked...
- Patent number 12,300,669
- Issue date May 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ping-Tzu Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Configurable random-access memory (RAM) array including through-sil...
- Patent number 12,300,688
- Issue date May 13, 2025
- Jianwen Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for integrating batteries to maintain volatile...
- Patent number 12,287,687
- Issue date Apr 29, 2025
- Arbor Company, LLLP
- Darrel James Guzy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device
- Patent number 12,272,676
- Issue date Apr 8, 2025
- Kioxia Corporation
- Masayoshi Tagami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Redundancy scheme for activating circuitry on a base die of a 3D st...
- Patent number 12,271,332
- Issue date Apr 8, 2025
- Xilinx, Inc.
- Brian C. Gaide
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D stacked integrated circuits having functional blocks configured...
- Patent number 12,266,647
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arrangement and thermal management of 3D stacked dies
- Patent number 12,266,585
- Issue date Apr 1, 2025
- Advanced Micro Devices, Inc.
- John Wuu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional circuit implementing machine trained network
- Patent number 12,248,869
- Issue date Mar 11, 2025
- Adeia Semiconductor Inc.
- Steven L. Teig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated assemblies comprising vertically-stacked decks with inte...
- Patent number 12,249,598
- Issue date Mar 11, 2025
- Micron Technology, Inc.
- Werner Juengling
- G11 - INFORMATION STORAGE
Information Patent Grant
Thermocompression bonding using metastable gas atoms
- Patent number 12,245,379
- Issue date Mar 4, 2025
- SET North America, LLC
- Eric Frank Schulte
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Thermocompression bonding with passivated copper-based contacting m...
- Patent number 12,245,380
- Issue date Mar 4, 2025
- SET North America, LLC
- Eric Frank Schulte
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Thermocompression bonding with passivated nickel-based contacting m...
- Patent number 12,245,381
- Issue date Mar 4, 2025
- SET North America, LLC
- Eric Frank Schulte
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Devices, systems, and methods for stacked die packages
- Patent number 12,243,850
- Issue date Mar 4, 2025
- Flex Ltd.
- Cheng Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional stacking structure and manufacturing method thereof
- Patent number 12,224,265
- Issue date Feb 11, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ming-Fa Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
TSV check circuit with replica path
- Patent number 12,224,275
- Issue date Feb 11, 2025
- Micron Technology, Inc.
- Harutaka Makabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor package
- Patent number 12,218,102
- Issue date Feb 4, 2025
- Samsung Electronics Co., Ltd.
- Youngkun Jee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 12,211,821
- Issue date Jan 28, 2025
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable logic device with fine-grained disaggregation
- Patent number 12,206,410
- Issue date Jan 21, 2025
- Intel Corporation
- Dheeraj Subbareddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Facilitating alignment of stacked chiplets
- Patent number 12,191,297
- Issue date Jan 7, 2025
- Tokyo Electron Limited
- Robert Clark
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR PACKAGES AND MANUFACTURING METHODS THEREOF
- Publication number 20250218889
- Publication date Jul 3, 2025
- Samsung Electronics Co., Ltd.
- Min Ki Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE
- Publication number 20250210595
- Publication date Jun 26, 2025
- KIOXIA Corporation
- Masayoshi TAGAMI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20250210481
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- Eunsu Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH CAPACITANCE HYBRID BONDED CAPACITOR DEVICE
- Publication number 20250201775
- Publication date Jun 19, 2025
- International Business Machines Corporation
- Nicholas Alexander Polomoff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE, DIE STRUCTURE AND METHOD FOR FORMING THE PACKAGE...
- Publication number 20250201798
- Publication date Jun 19, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tsung-Chieh HSIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20250192083
- Publication date Jun 12, 2025
- Samsung Electronics Co., Ltd.
- Jongpa HONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20250183230
- Publication date Jun 5, 2025
- SK HYNIX INC.
- Nam Jae LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20250183195
- Publication date Jun 5, 2025
- Samsung Electronics Co., Ltd.
- Jing Cheng LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGES WITH CHIP STACK
- Publication number 20250183219
- Publication date Jun 5, 2025
- Samsung Electronics Co., Ltd.
- Hyunho Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE
- Publication number 20250174589
- Publication date May 29, 2025
- Innolux Corporation
- Ying-Jen Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Assemblies Comprising Vertically-Stacked Decks
- Publication number 20250174619
- Publication date May 29, 2025
- Micron Technology, Inc.
- Werner Juengling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20250174572
- Publication date May 29, 2025
- Samsung Electronics Co., Ltd.
- Hyun Ung Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20250167178
- Publication date May 22, 2025
- Samsung Electronics Co., Ltd.
- Youngkun JEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20250157960
- Publication date May 15, 2025
- Samsung Electronics Co., Ltd.
- Sangho CHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL CHIP STACK PREPARING METHOD AND THREE-DIMENSIONAL...
- Publication number 20250157971
- Publication date May 15, 2025
- Institute of Semiconductors, Guangdong Academy of Sciences
- Chuan HU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MANUFACTURING METHOD OF THREE-DIMENSIONAL STACKING STRUCTURE
- Publication number 20250157984
- Publication date May 15, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ming-Fa Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20250149490
- Publication date May 8, 2025
- Samsung Electronics Co., Ltd.
- Wonhee Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER PROCESS FOR PROBING BUMP PLACEMENT ON MULTIPLE SMALL POWER PA...
- Publication number 20250149390
- Publication date May 8, 2025
- Xilinx, Inc.
- Andy WIDJAJA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED...
- Publication number 20250149531
- Publication date May 8, 2025
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20250132275
- Publication date Apr 24, 2025
- Samsung Electronics Co., Ltd.
- Sangho Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
- Publication number 20250125298
- Publication date Apr 17, 2025
- Unimicron Technology Corp.
- John Hon-Shing Lau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CHIP, LOGIC CHIP, CHIP STACKED STRUCTURE, AND MEMORY
- Publication number 20250125254
- Publication date Apr 17, 2025
- CXMT CORPORATION
- Jiarui ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D CHIP PACKAGE BASED ON VERTICAL-THROUGH-VIA CONNECTOR
- Publication number 20250125241
- Publication date Apr 17, 2025
- iCometrue Company Ltd.
- Ping-Jung Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CHIP, LOGIC CHIP, CHIP STACK STRUCTURE, AND MEMORY
- Publication number 20250125264
- Publication date Apr 17, 2025
- CXMT CORPORATION
- Jiarui ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20250118705
- Publication date Apr 10, 2025
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE
- Publication number 20250104761
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- Sean S. Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY TILE WITH PROBE PAD ARRANGEMENT AND STACKED MEMORY DEVICE
- Publication number 20250105123
- Publication date Mar 27, 2025
- Powerchip Semiconductor Manufacturing Corporation
- Takeo Okamoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED VOLTAGE REGULATOR (IVR) PACKAGE INCLUDING INDUCTOR AND C...
- Publication number 20250096211
- Publication date Mar 20, 2025
- Samsung Electronics Co., Ltd.
- Sangnam JEONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED S...
- Publication number 20250087252
- Publication date Mar 13, 2025
- Rambus Inc.
- Yohan Frans
- G11 - INFORMATION STORAGE
Information Patent Application
PACKAGE SUBSTRATE EMPLOYING FILM SUBSTRATE AND AN OUTER PRE-IMPREGN...
- Publication number 20250079281
- Publication date Mar 6, 2025
- QUALCOMM Incorporated
- Hong Bok We
- H01 - BASIC ELECTRIC ELEMENTS

the devices having the same size and there being no auxiliary carrier between the devices

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Thermocompression bonding with passivated silver-based contacting m...

Thermocompression bonding with passivated gold contacting metal

Thermocompression bonding with passivated tin-based contacting metal

Signal routing between memory die and logic die for performing oper...

Semiconductor package

Semiconductor package and method of fabricating the same

Semiconductor circuit structure with direct die heat removal structure

Method for manufacturing semiconductor device including resin layers

Semiconductor circuit structure with direct die heat removal structure

Semiconductor devices and manufacturing methods of the same

Stacked semiconductor device

Backside contact for thermal displacement in a multi-wafer stacked...

Configurable random-access memory (RAM) array including through-sil...

Systems and methods for integrating batteries to maintain volatile...

Memory device

Redundancy scheme for activating circuitry on a base die of a 3D st...

3D stacked integrated circuits having functional blocks configured...

Arrangement and thermal management of 3D stacked dies

Three dimensional circuit implementing machine trained network

Integrated assemblies comprising vertically-stacked decks with inte...

Thermocompression bonding using metastable gas atoms

Thermocompression bonding with passivated copper-based contacting m...

Thermocompression bonding with passivated nickel-based contacting m...

Devices, systems, and methods for stacked die packages

Three-dimensional stacking structure and manufacturing method thereof

TSV check circuit with replica path

Semiconductor package

Package-on-package assembly with wire bond vias

Programmable logic device with fine-grained disaggregation

Facilitating alignment of stacked chiplets

Patents Applicationslast 30 patents

SEMICONDUCTOR PACKAGES AND MANUFACTURING METHODS THEREOF

MEMORY DEVICE

SEMICONDUCTOR PACKAGE

HIGH CAPACITANCE HYBRID BONDED CAPACITOR DEVICE

PACKAGE STRUCTURE, DIE STRUCTURE AND METHOD FOR FORMING THE PACKAGE...

SEMICONDUCTOR PACKAGE

CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR PACKAGE

SEMICONDUCTOR PACKAGES WITH CHIP STACK

PACKAGE STRUCTURE

Integrated Assemblies Comprising Vertically-Stacked Decks

SEMICONDUCTOR PACKAGE

SEMICONDUCTOR PACKAGE

SEMICONDUCTOR PACKAGE

THREE-DIMENSIONAL CHIP STACK PREPARING METHOD AND THREE-DIMENSIONAL...

MANUFACTURING METHOD OF THREE-DIMENSIONAL STACKING STRUCTURE

SEMICONDUCTOR PACKAGE

WAFER PROCESS FOR PROBING BUMP PLACEMENT ON MULTIPLE SMALL POWER PA...

3D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED...

SEMICONDUCTOR PACKAGE

CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

MEMORY CHIP, LOGIC CHIP, CHIP STACKED STRUCTURE, AND MEMORY

3D CHIP PACKAGE BASED ON VERTICAL-THROUGH-VIA CONNECTOR

MEMORY CHIP, LOGIC CHIP, CHIP STACK STRUCTURE, AND MEMORY

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE

MEMORY TILE WITH PROBE PAD ARRANGEMENT AND STACKED MEMORY DEVICE

INTEGRATED VOLTAGE REGULATOR (IVR) PACKAGE INCLUDING INDUCTOR AND C...

MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED S...

PACKAGE SUBSTRATE EMPLOYING FILM SUBSTRATE AND AN OUTER PRE-IMPREGN...