Patent Application
20250174589
The disclosure relates to a package structure.
Generally, a package stacking structure involves stacking a package (e.g., a memory package) on another package (e.g., a logic package) through connection components such as solder balls. For example, the package stacking structure may be a memory package with a memory element stacked on a logic package with a logic element. However, the wiring density, spacing, or size of the memory package may not match the wiring density, spacing, or size of the logic package in some circumstances. Thus, disposing one or more additional substrates between the memory package and the logic package is regarded as a solution for the issue.
In a package structure formed by stacking multiple substrates, the coefficient of thermal expansion (CTE) of the bonding layer coated entirely between two adjacent substrates does not match the materials used for the substrates. Consequently, during other subsequent packaging processes, the thermal stress generated in high-temperature processes such as the reflow process can cause cracks in the conductive material embedded in the bonding layer and used to connect the signals of the two substrates, resulting in challenges in meeting the current or future requirements for package structure reliability.
The disclosure provides a package structure, which facilitates the improvement in package structure reliability.
According to an embodiment of the disclosure, a package structure includes a first substrate, a second substrate, a bonding pad, a protective layer, and an air gap. The first substrate has a first surface and a second surface opposite to each other, and includes a first via extending from the first surface to the second surface. The second substrate is disposed on the first surface of the first substrate, has a third surface facing the first surface and a fourth surface opposite to the third surface, and includes a second via extending from the third surface to the fourth surface. The bonding pad is disposed between the first substrate and the second substrate and connected to the first via and the second via. The protective layer is disposed between the first substrate and the second substrate and surrounds the bonding pad. The air gap is disposed between the first substrate and the second substrate.
According to another embodiment of the disclosure, a package structure includes a first glass substrate, a second glass substrate, multiple bonding pads, and at least one protective layer.
The first glass substrate includes multiple first through vias. The second glass substrate includes multiple second through vias. The bonding pads are disposed between the first glass substrate and the second glass substrate. Each of the bonding pads is overlapped and connected to the corresponding first through via and the corresponding second through via. The at least one protective layer is disposed between the first glass substrate and the second glass substrate and surrounds at least one of the bonding pads. The at least one protective layer and the at least one surrounded bonding pad define at least one first air gap between the first glass substrate and the second glass substrate.
Based on the above, in the embodiments of the disclosure, the air gap is disposed between the first substrate and the second substrate. Thus, during other packaging processes, the problem of cracks of the bonding pad between the first substrate and the second substrate, which is a result of mismatched coefficients of thermal expansion (CTE) and the materials used for the substrates, can be avoided, thereby facilitating the improvement in package structure reliability.
To make the features and advantages of the disclosure more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
The disclosure can be understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding by readers and for the concision of the illustration, multiple drawings in the disclosure only depict a part of the package structure, and certain elements in the drawings are not drawn according to actual scale. In addition, the number and size of each element in the drawings are for illustration only, and are not intended to limit the scope of the disclosure. For example, the relative sizes, thicknesses and positions of various layers, regions and/or structures may be reduced or enlarged for clarity.
Certain terms may be used throughout the disclosure and the claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may refer to the same elements by different names. The disclosure does not intend to distinguish between elements that have the same function but have different names. In the following description and claims, the words including “having” and “including” are open-ended words, and thus should be interpreted as meaning “including but not limited to.”
Directional terms mentioned herein, such as “up,” “down,” “front,” “rear,” “left,” “right,” and the like refer only to the directions of the drawings. Accordingly, the directional terms used are for illustration, and are not intended to limit the disclosure. It should be understood that when an element or film layer is referred to as being “disposed on” or “connected to” another element or film layer, the element or the film layer may be directly on or connected to the another element or film layer, or intervening elements or film layers may also be present in between (non-direct circumstances). In contrast, when an element or film layer is referred to as being “directly on” or “directly connected to” another element or film layer, no intervening elements or film layers are present in between. In addition, when the element or film layer is referred to as overlapping another element, the element or film layer at least partially overlaps the another element or film layer.
In the text, the terms “about,” “approximately,” “essentially,” or “substantially” usually implies that a value is within 10% of a given value or range, or within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. In addition, the description “a given range from a first value to a second value” or “a given range between a first value and a second value” implies that the given range includes the first value, the second value, and other values in between.
In some embodiments of the disclosure, terms related to bonding and connection, such as “connection,” “interconnection,” and the like, unless otherwise specified, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, in which there are other structures provided between these two structures. The terms related to bonding and connection may also include the case where both structures are movable, or both structures are fixed. Furthermore, the terms “electrically connected” or “coupled” includes any direct and indirect means of electrical connection.
In the embodiments provided later, the same or similar reference numerals are used to refer to the same or similar elements, and the descriptions will not be repeated. In addition, as long as the features of the various embodiments do not depart from or conflict with the spirit of the disclosure, the embodiments may be mixed and matched as desired. It is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents. That is, in the following embodiments, technical features in several different embodiments may be replaced, reorganized, and mixed to complete other embodiments without departing from the spirit of the disclosure. Moreover, the terms such as “first” and “second” mentioned in the specification or the claims are only used to name different elements or to distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of the elements, nor are they intended to limit the manufacturing order or disposition order of the elements.
Referring to
The first substrate SUB1 has a first surface S1 and a second surface S2 opposite to each other and includes a first via VIA1 extending from the first surface S1 to the second surface S2. In some embodiments, the material of the first substrate SUB1 may include glass, quartz, sapphire, ceramic, plastic, BT substrate, steel plate, other suitable substrate materials, or combinations thereof, but the disclosure is not limited thereto. In the disclosure, the first substrate may be a glass substrate, and the first via VIA1 may be a through glass via (TGV). The first via VIA1 may include conductive materials such as metal. Moreover, the conductive material may be, for example, a single-layer structure with a single type of metal, or a composite layer structure with multiple sub-layers, formed with different metals, stacked on each other. For example, the first via VIA1 may include a titanium layer (not shown) and a copper layer (not shown) stacked on the titanium layer, forming a composite layer structure. In some embodiments, the first via VIA1 may be formed through the following steps. First, a via hole (not shown) is formed in the first substrate SUB1. Next, a seed layer (not shown) is formed on a surface of the via hole. Then, through an electroplating process, the seed layer grows to form the first via VIA1 that fills the via hole.
The second substrate SUB1 is disposed on the first surface S1 of the first substrate SUB1, has a third surface S3 facing the first surface S1 and a fourth surface S4 opposite to the third surface S3, and includes a second via VIA2 extending from the third surface to the fourth surface.
In some embodiments, the material of the second substrate SUB2 may include glass, quartz, sapphire, ceramic, plastic, BT substrate, steel plate, other suitable substrate materials, or combinations thereof, but the disclosure is not limited thereto. In the disclosure, the second substrate may be a glass substrate, and the second via VIA2 may be a through glass via (TGV). The second via VIA2 may include conductive materials such as metal. Moreover, the conductive material may be, for example, a single-layer structure with a single type of metal, or a composite layer structure with multiple sub-layers, formed with different metals, stacked on each other. For example, the second via VIA2 may include a titanium layer (not shown) and a copper layer (not shown) stacked on the titanium layer, forming a composite layer structure. In some embodiments, the second via VIA2 may be formed through the same or similar steps as the first via VIA1, and the disclosure is not limited thereto.
In some embodiments, the package structure 10 may include a first circuit structure CS1 formed on the second surface S2 of the first substrate SUB1 and a second circuit structure CS2 formed on the fourth surface S4 of the second substrate SUB2.
In some embodiments, the first circuit structure CS1 may include a conductive layer 102 formed on the second surface S2 of the first substrate SUB1, an insulating layer 103 covering the conductive layer 102 and the second surface S2 of the first substrate SUB1, a wiring layer 104 formed on the insulating layer 103 and connected to the conductive layer 102, a solder mask layer 110 covering the wiring layer 104 and the insulating layer 103, and a pad 112 formed in the solder mask layer 110.
In some embodiments, the second circuit structure CS2 may include a conductive layer 202 formed on the fourth surface S4 of the second substrate SUB2, an insulating layer 203 covering the conductive layer 202 and the fourth surface S4 of the second substrate SUB2, a wiring layer 204 formed on the insulating layer 203 and connected to the conductive layer 202, a solder mask layer 210 covering the wiring layer 204 and the insulating layer 203, and a pad 212 formed in the solder mask layer 210.
Each of the conductive layer 102 and the conductive layer 202 may include and/or be at least one metal selected from Al, Ti, Cr, Fe, Co, Ni, Cu, Zn, Pd, Pt, Au, and Ag. In some embodiments, the conductive layer 102 and the conductive layer 202 may be respectively integrated in the processes through which the first via VIA1 and the second via VIA2 are formed.
The insulating layer 103 and the insulating layer 203 each includes organic or inorganic materials. Organic materials include polyimide (PI), poly-p-xylylene (also referred to as Parylene), benzocyclobutene (BCB), epoxy, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), macromolecules, or other suitable organic materials, but the disclosure is not limited thereto. Inorganic materials include silicon dioxide, silicon nitride, silicon oxynitride, or other suitable inorganic materials, but the disclosure is not limited thereto. In some embodiments, the insulating layer 103 or the insulating layer 203 may be a single-layer structure or a multi-layer structure, but the disclosure is not limited thereto.
Each of the wiring layer 104 and the wiring layer 204 may include and/or be at least one metal selected from Al, Ti, Cr, Fe, Co, Ni, Cu, Zn, Pd, Pt, Au, and Ag. In some embodiments, the processes for forming the wiring layer 104 and the wiring layer 204 may include a damascene process. The damascene process includes the following steps. The insulating layer 103 and the insulating layer 203 is patterned to form openings therein. One or more conductive layers (e.g., a barrier layer and another conductive layer) are deposited (e.g., through CVD deposition) on the insulating layer 103 and the insulating layer 203. The one or more conductive layers are patterned to form the wiring layer 104 and the wiring layer 204.
The materials of the solder mask layer 110 and the solder mask layer 210 may include organic materials (e.g., polyimide-based resin, epoxy-based resin, or acrylic-based resin) or inorganic materials (e.g., silicon dioxide, silicon nitride, or silicon oxynitride). In some embodiments, each of the solder mask layer 110 and the solder mask layer 210 may be a single-layer structure or a multi-layer structure, but the disclosure is not limited thereto.
The pad 112 and the pad 212 may include and/or be at least one metal selected from Al, Ti, Cr, Fe, Co, Ni, Cu, Zn, Pd, Pt, Au, and Ag. In some embodiments, the pad 112 and the pad 212 may be formed through an electroless nickel immersion gold (ENIG) process. Based on this, the materials of the pad 112 and the pad 212 may include an alloy of gold and nickel, but the disclosure is not limited thereto.
In some embodiments, the package structure 10 includes a protective layer 120 formed on the first circuit structure CS1 and covering the pad 112. The package structure 10 also includes a protective layer 220 formed on the second circuit structure CS2 and covering the pad 212.
The materials of the protective layer 120 and the protective layer 220 may be, for example, suitable inorganic or organic materials, but the disclosure is not limited thereto. In some embodiments, the method of forming the protective layer 120 and the protective layer 220 may be performed through an attachment process, but the disclosure is not limited thereto.
The bonding pad 300 is disposed between the first substrate SUB1 and the second substrate SUB2 and connected to the first via VIA1 and the second via VIA2. The material of the bonding pad 300 may be, for example, a suitable conductive material (e.g., a conductive adhesive). In some embodiments, the bonding pad 300 directly contacts the first via VIA1 and the second via VIA2.
The protective layer 400 is disposed between the first substrate SUB1 and the second substrate SUB2 and surrounds the bonding pad 300. The material of the protective layer 400 may be a suitable insulating material, such as glass frit, optical adhesive, silicone, hot melt adhesive, AB adhesive, UV curing adhesive, polymer adhesive, resin, or combinations thereof, but the disclosure is not limited thereto.
In some embodiments, the air gap AG1 is disposed between the first substrate SUB1 and the second substrate SUB2. In some embodiments, the bonding pad 300 directly contacts the first via VIA1 and the second via VIA2, and defines the air gap AG1 with the protective layer 400. Since the air gap AG1 is disposed at a linking site between the first substrate SUB1 and the second substrate SUB2 (e.g., a location of the bonding pad 300 connected to the first via VIA1 and the second via VIA2), when other packaging processes are performed, the bonding pad 300 does not crack due to mismatched coefficients of thermal expansion (CTE) of the materials used for the first substrate SUB1 and the second substrate SUB2. Thus, a signal connection between the first substrate SUB1 and the second substrate SUB2 is not affected, thereby facilitating the improvement in the reliability of the package structure 10.
In some embodiments, as shown in
In some embodiments, as shown in
The bonding pads 300 shown in
In some embodiments, a horizontal area of the protective layer 400 is less than 50% of a horizontal area of the first substrate SUB1 or the second substrate SUB2.
In some embodiments, a package structure 10 includes a first glass substrate SUB1, a second glass substrate SUB2, multiple bonding pads 300, and at least one protective layer 400. The first glass substrate SUB1 includes multiple first through vias VIA1. The second glass substrate SUB2 includes multiple second through vias VIA2. The bonding pads 300 are disposed between the first glass substrate SUB1 and the second glass substrate SUB2. Each of the bonding pads 300 is overlapped and connected to the corresponding first through via VIA1 and the corresponding second through via VIA2. The at least one protective layer 400 is disposed between the first glass substrate SUB1 and the second glass substrate SUB2 and surrounds at least one of the bonding pads 300. The at least one protective layer 400 and the at least one surrounded bonding pad 300 define at least one first air gap AG1 between the first glass substrate SUB1 and the second glass substrate SUB2.
In some embodiments, the at least one protective layer 400 includes multiple protective layers 400, and a second air gap AG2 between the first glass substrate SUB1 and the second glass substrate SUB2 may be formed between the protective layers 400, wherein the second air gap AG2 does not communicate with the first air gap AG1. In some embodiments, the protective layer 400 surrounds at least some of the bonding pads 300 (as shown in
In summary, in the embodiments of the disclosure, since the air gap is disposed at the linking site between the first substrate and the second substrate (i.e., the location of the bonding pad connected to the first via and the second via), when other packaging processes are performed, the bonding pad does not crack due to mismatched coefficients of thermal expansion (CTE) of the materials used for the first substrate and the second substrate. Thus, the signal connection between the first substrate and the second substrate is not affected, thereby facilitating the improvement in package structure reliability. In some embodiments, the protective layer 400 surrounding the bonding pad 300 further prevent external moisture from intruding into the linking site between the first substrate and the second substrate, thereby facilitating the improvement in the connection reliability between the bonding pad and the first via and the second via.
The above embodiments are used to describe the technical solution of the disclosure and are not a limitation thereof. Although the disclosure has been described in detail with reference to each embodiment above, those having ordinary skill in the art should understand that the technical solution recited in each embodiment above may still be modified, or some or all of the technical features thereof may be equivalently replaced. These modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solution of each embodiment of the disclosure.
Although the embodiments of the disclosure and their advantages are disclosed as above, it should be understood that any person with ordinary skill in the art, without departing from the spirit and scope of the disclosure, may make changes, substitutions, and modifications, and features between the embodiments may be mixed and replaced at will to form other new embodiments. In addition, the scope of the disclosure is not limited to the manufacturing processes, machines, manufactures, material compositions, devices, methods, and steps in the specific embodiments described in the specification. Any person with ordinary skill in the art may understand the current or future development processes, machines, manufactures, material compositions, devices, methods, and steps from the content of the disclosure, which may all be adopted according to the disclosure as long as they may implement substantially the same function or obtain substantially the same result in an embodiment described here. Therefore, the scope of the disclosure includes the above manufacturing processes, machines, manufactures, material compositions, devices, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of the disclosure also includes the combination of each claim and embodiment. The scope of the disclosure shall be subject to the scope defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202410838760.3 | Jun 2024 | CN | national |
This application claims the priority benefit of U.S. provisional application Ser. No. 63/603,642, filed on Nov. 29, 2023 and China application serial no. 202410838760.3, filed on Jun. 26, 2024. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
| Number | Date | Country | |
|---|---|---|---|
| 63603642 | Nov 2023 | US |
