Patent Application
20250125264
With the development of integrated circuit technologies, remarkable progress has been made in the manufacturing process of semiconductor devices. In recent years, however, the development of two-dimensional semiconductor technology has been accompanied by various challenges, including physical limits, limits of existing development technology, limits of storage electron density, etc. In this context, to solve the difficulties encountered by two-dimensional semiconductor devices and to pursue lower production costs per unit memory cell, a plurality of chips may be stacked by using a bonding process (e.g., hybrid bonding, bumping, and wire bonding) to form a three-dimensional semiconductor device. However, for the three-dimensional semiconductor device, connection structures between different chips still have problems such as large parasitic capacitance and large parasitic resistance, which affect the signal transmission quality.
The present disclosure relates to the field of semiconductors, and in particular, to a memory chip, a logic chip, a chip stack structure, and a memory.
The present disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory.
The technical solutions of the present disclosure are realized as follows.
In a first aspect, an embodiment of the present disclosure provides a memory chip, where a top surface of the memory chip has a first axis and a second axis, the first axis and the second axis are perpendicular to each other and intersect at a center of the top surface, the first axis is parallel to one edge of the top surface, and the second axis is parallel to the other edge of the top surface; the memory chip includes four first transmission structures and B second transmission structure groups, where B is a natural number; the four first transmission structures are arranged symmetrically about the first axis, and the four first transmission structures are arranged symmetrically about the second axis; each one of the second transmission structure groups includes four second transmission structures, and the four second transmission structures are arranged symmetrically about the first axis and the four second transmission structures are arranged symmetrically about the second axis; the memory chip receives one first identification signal from each one of the first transmission structures and generates a chip position identification code based on four first identification signals; signal levels transmitted by the four second transmission structures in a same one of the second transmission structure groups are the same, and the memory chip receives one second identification signal from each one of the second transmission structure groups and generates a stack position identification code based on B second identification signals; where the memory chip determines a position number thereof in a chip stack structure to which the memory chip belongs according to the stack position identification code and the chip position identification code.
In a second aspect, an embodiment of the present disclosure provides a logic chip, where a top surface of the logic chip has a first axis and a second axis, the first axis and the second axis are perpendicular to each other and intersect at a center of the top surface, the first axis is parallel to one edge of the top surface, and the second axis is parallel to the other edge of the top surface; the logic chip includes four third transmission structures and B fourth transmission structure groups, where B is a natural number; the four third transmission structures are arranged symmetrically about the first axis and the four third transmission structures are arranged symmetrically about the second axis; each one of the fourth transmission structure groups includes four fourth transmission structures, and the four fourth transmission structures are arranged symmetrically about the first axis and the four fourth transmission structures are arranged symmetrically about the second axis; the logic chip is configured to generate four first identification signals and transmit the four first identification signals to the four third transmission structures in a one-to-one correspondence, where the four first identification signals indicate a chip position identification code of a memory chip adjacent to the logic chip; the logic chip is further configured to receive one second identification signal from each one of the fourth transmission structure groups and generate a stack position identification code based on B second identification signals in an initialization process; or generate B second identification signals of a default state and send one of the second identification signals to one of the fourth transmission structure groups in a normal operation stage.
In a third aspect, an embodiment of the present disclosure provides a chip stack structure. The chip stack structure includes the logic chip as described in the second aspect and at least one stack unit, and the logic chip and the at least one stack unit are sequentially stacked along a third direction; each one of the at least one stack unit includes a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip sequentially stacked along the third direction, and the third direction is perpendicular to a top surface of each one of the memory chips; the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are each the memory chip as described in the first aspect;
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are merely illustrative of a related application and are not intended to limit the application. In addition, it should be noted that for the convenience of description, only the portions relevant to the related applications are shown in the drawings. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are for the purpose of describing the embodiments of the present disclosure only and are not intended to limit the present disclosure. In the following description, reference is made to “some embodiments” which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms “first\second\third” referred to in the embodiments of the present disclosure are merely used for distinguishing similar objects and do not represent a specific ordering for the objects. It can be understood that “first\second\third” may be subjected to interchange of a specific order or sequence if permitted, such that the embodiments of the present disclosure described herein can be implemented in an order other than that shown or described.
Before describing the embodiments of the present disclosure, three directions for describing three-dimensional structures that may be used in the planes involved in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.
Referring to
Referring to
As shown in
As shown in
Meanwhile, the types of the transmission structures are not limited to the above two types, and a structure capable of achieving electrical connection among different stacked chips may be considered as the transmission structure.
In particular, the illustrations presented in the present disclosure are not meant to be actual views of any particular microelectronic apparatus or components thereof, but are merely idealized representations for describing illustrative embodiments. The drawings are not necessarily to scale.
The embodiments of the present disclosure are described in detail below with reference to the drawings.
In an embodiment, a memory chip and a logic chip are provided. The memory chip/the logic chip includes a plurality of transmission structures penetrating through the chip along a third direction, and the transmission structures are used to implement signal transmission among different chips. Illustratively, the transmission structure may be a conductive via (e.g., a through silicon via). All the transmission structures may be located at any positions. In particular, every four transmission structures can be regarded as a transmission structure group in function, but the respective positions of the four transmission structures are not limited.
In a specific embodiment, eight memory chips and one logic chip are stacked in a face-to-back manner to form a 3D memory device, and the respective transmission structures of the eight memory chips are aligned along the third direction, and nine transmission structures aligned along the third direction are connected to form an electrical path. Referring to
Meanwhile, each memory chip and the logic chip are further provided with a plurality of driving circuits (only one driving circuit is shown in a dashed box in
For the whole memory device, the eight memory chips are divided into four channels (CH0, CH1, CH4, CH5) for management, and the signal Signal_CH0 of the channel CH0 is transmitted through an electrical path formed by “the transmission structure T0 in logic chip-the transmission structure T0 in the memory chip 0-the transmission structure T0 in the memory chip 1-the transmission structure T0 in the memory chip 2-the transmission structure T0 in the memory chip 3-the transmission structure T0 in the memory chip 4-the transmission structure T0 in the memory chip 5-the transmission structure T0 in the memory chip 6-the transmission structure T0 in the memory chip 7”, while the select signals of the data selector mux0 in the memory chip 0 and the data selector mux4 in the memory chip 4 are both SEL_C0, i.e., the signal Signal_CH0 can enter the memory chip 0 and the memory chip 4 via the aforementioned electrical path; the process of signal output can be similarly understood.
As can be seen from the above, the memory chip 0 only needs to acquire signals from the transmission structure T0, and the memory chip 1 only needs to acquire signals from the transmission structure T1, . . . , that is, each memory chip only needs to acquire signals from one transmission structure in one transmission structure group. It is worth noting that different memory chips may need to acquire signals from different transmission structures. However, since all memory chips need to be designed to have the same structure during the manufacturing process (which can save cost and labor to the maximum), all transmission structures in the memory chips need to be designed with corresponding driving structures and data selectors for structural consistency. Further, in the case that the chip stack structure shown in
In another embodiment, referring to
In this way, the memory chip 0 can acquire the signal Signal_CH0 through the output end of the transmission structure T0 in the logic chip, the memory chip 1 can acquire the signal Signal_CH1 through the input end of the transmission structure T0 in the memory chip 0, the memory chip 2 can acquire the signal Signal_CH4 through the input end of the transmission structure T0 in the memory chip 1, and the memory chip 3 can acquire the signal Signal_CH5 through the input end of the transmission structure T0 in the memory chip 2, . . . , such that for each memory chip, only one transmission structure in each transmission structure group needs to be connected to the driving circuit, and no data selector is needed, such that the number of devices can be reduced, thereby reducing the parasitic capacitance. However, compared with the direct connection configuration of transmission structures in
In particular, in the chip stack structures of
In summary, in one aspect, the chip stack structure in
In yet another embodiment of the present disclosure, referring to
The memory chip 10 includes four first transmission structures (A0-A3) and B second transmission structure groups, and
Referring to
The memory chip 10 receives one first identification signal from each first transmission structure and generates a chip position identification code CID based on four first identification signals. The signal levels transmitted by the four second transmission structures in the same second transmission structure group are the same, and the memory chip 10 receives one second identification signal from each second transmission structure group and generates a stack position identification code SID based on B second identification signals.
Here, the memory chip 10 determines a position number thereof in the chip stack structure to which the memory chip belongs based on the stack position identification code SID and the chip position identification code CID.
In a specific embodiment, four memory chips 10 are stacked to form a stack unit, and the logic chip and a plurality of stack units further form a chip stack structure. The chip position identification code CID indicates a position number of the memory chip 10 in the stack unit to which the memory chip belongs; the stack position identification code SID indicates a position number of a stack unit to which the memory chip 10 belongs in the chip stack structure to which the stack unit belongs.
Taking a chip stack unit formed by stacking one logic chip and eight memory chips (every four memory chips are a stack unit, and there are two stack units), the CID has a 2-bit sub-signal CID<1:0> and the SID has a 2-bit sub-signal SID<1:0>. In the normal operation stage of the memory chip 10, numbering is performed by starting from the logic chip (i.e., bottom to top), and the CID<1:0> and SID<1:0> of each chip are as shown in Table 1; in the initialization stage of the memory chip 10, numbering is performed from the side away from the logic chip (i.e., from top to bottom), and the CID<1:0> and SID<1:0> of each chip are as shown in Table 2.
In some embodiments, referring to
In some embodiments, referring to
First, the comparison circuit 31 is coupled to the first decoding circuit 22 and is configured to generate an effective first control signal when the chip position identification code CID<1:0> is the same as the preset chip position identifier, where the preset chip position identifier indicates that the memory chip 10 is the last chip in the stack unit to which the memory chip belongs. Illustratively, referring to Table 1 or Table 2, the preset chip position identifier=11; for Table 1, i.e., when the memory chips are numbered from bottom to top, the memory chips 3 and 7 are the last chips in the respective stack units to which the memory chips belong; for Table 2, i.e., when the memory chips are numbered from top to bottom, the memory chip 4 and the memory chip 0 are the last chips in the respective stack unit to which the memory chips belong. Here, being effective may refer to a high-level state, and being ineffective may refer to a low-level state, or vice versa.
Next, the logic processing circuit 32 is coupled to B second transmission structure groups and is configured to receive one second identification signal SignalB from each second transmission structure group and generate the stack position identification code SID<1:0> based on the received B second identification signals SignalB<1:0> (illustrated with B=2). Here, the signals transmitted by the four second transmission structures in the same second transmission structure group are subjected to an OR logic to form one second identification signal.
Thirdly, the logic operation circuit 33 is coupled to the comparison circuit 31 and the logic processing circuit 32 and is configured to receive the first control signal and the stack position identification code SignalB<1:0>, perform a plus-one operation on the stack position identification code SignalB<1:0> to generate and output a second identification signal SignalB′<1:0> of a next memory chip 10 when the first control signal is effective, and output the stack position identification code SignalB<1:0> of the memory chip 10 as the second identification signal SignalB′<1:0> of the next memory chip 10 when the first control signal is ineffective.
Finally, the logic processing circuit 32 is further configured to receive the second identification signals SignalB′<1:0> of the next memory chip 10 output by the logic operation circuit 33 and transmit them to the next memory chip 10 through B second transmission structure groups, where the ith second identification signal SignalB′<i−1> of the next memory chip 10 is transmitted to the next memory chip 10 via the ith second transmission structure group, and i is a natural number less=than or equal to B.
It should be noted that the signal values of the second identification signals SignalB<1:0> are respectively the same as the signal values of the stack position identification codes SID<1:0>, except that they are located at different circuit positions, and there may be signal transmission and enhancement in the middle.
As such, for the first three memory chips 10 in each stack unit, each memory chip only needs to directly transmit the stack position identification code SID to a next memory chip 10; however, for the last one memory chip 10 in each stack unit, it performs a plus-one operation on the stack position identification code SID and then transmits the stack position identification code SID to a next memory chip 10.
In some embodiments, referring to
Only one example of the conductive via and the contact structure is provided; referring to
Referring to
In some embodiments, the logic processing circuit 32 is further coupled to the first decoding circuit 22 (not shown in this figure, but understood in combination with the text) and is configured to: receive a chip position identification code CID<1:0>; in the case that the chip position identification code CID<1:0> indicates that the memory chip 10 is located at an even-numbered position, receive the second identification signal SignalB<1:0> of the memory chip from the conductive via of each second transmission structure in the corresponding second transmission structure group via the second driving circuit 321 and send the generated stack position identification code SID<1:0> to the logic operation circuit 33; and send the second identification signal SignalB′<1:0> of the next memory chip 10 output by the logic operation circuit 33 to the contact structure of each second transmission structure in the corresponding second transmission structure group via the third driving circuit 322.
For example, referring to
Meanwhile, the logic processing circuit 32 is further configured to, in the case that the chip position identification code CID<1:0> indicates that the memory chip 10 is in an odd-numbered position, receive a second identification signal SignalB<1:0> of the memory chip from the contact structure of each second transmission structure in the corresponding second transmission structure group via the third driving circuits 322, send the generated stack position identification code SID<1:0> to the logic operation circuit 33, and send the second identification signal SignalB′<1:0> of the next memory chip 10 output by the logic operation circuit 33 via the second driving circuits 321 to the conductive via of each second transmission structure in the corresponding second transmission structure group.
For example, referring to
That is, the second transmission structure supports both top-to-bottom transmission and bottom-to-top transmission, thereby implementing the two numbering mechanisms of the initialization process and the normal operation process. Specifically, the memory chip 10 provided by the embodiment of the present disclosure supports face-to-face stacking; referring to the foregoing Table 1 and Table 2, the memory chip 0 and the memory chip 1 are stacked in a face-to-face manner, the memory chip 1 and the memory chip 2 are stacked in a back-to-back manner, the memory chip 2 and the memory chip 3 are stacked in a face-to-face manner, . . . , and so on. As such, when signals are transmitted upward from the logic chip, the memory chip 0, the memory chip 2, the memory chip 4, and the memory chip 6 are facing upward, and the second identification signal SignalB<1:0> needs to be acquired from the conductive vias (of the second transmission structures) penetrating through the substrate, and the newly generated second identification signal SignalB′<1:0> is sent to the contact structures (of the second transmission structures) penetrating through the top surface; the memory chip 1, the memory chip 3, the memory chip 5, and the memory chip 7 are facing downward, and the second identification signal SignalB<1:0> needs to be acquired from the contact structures (of the second transmission structures) penetrating through the top surface, and the newly generated second identification signal SignalB′<1:0> is sent to the conductive vias. When transmitting from the uppermost memory chip down to the logic chip, the transmission direction of each memory chip is exactly opposite to what is described above. Specifically, the memory chip 0, the memory chip 2, the memory chip 4, and the memory chip 6 are facing upward, and the second identification signal SignalB<1:0> needs to be acquired from the contact structures (of the second transmission structures) penetrating through the top surface, and the newly generated second identification signal SignalB′<1:0> is sent to the conductive vias (of the second transmission structures) penetrating through the substrate; the memory chip 1, the memory chip 3, the memory chip 5, and the memory chip 7 are facing downward, and the second identification signal SignalB<1:0> needs to be acquired from the conductive vias (of the second transmission structures) penetrating through the substrate, and the newly generated second identification signal SignalB′<1:0> is sent to the contact structures (of the second transmission structures) penetrating through the top surface.
Therefore, in some embodiments, referring to
the third driving circuit 322 includes a second OR logic circuit 44, an even driving output circuit 46, and an odd driving input circuit 45; the input end of the second OR logic circuit 44 is coupled to the contact structure of each second transmission structure of the corresponding second transmission structure group, the odd driving input circuit 45 is coupled between the output end of the second OR logic circuit 44 and the input end of the logic operation circuit 33, and the even driving output circuit 46 is coupled between the output end of the logic operation circuit 33 and the contact structure of each second transmission structure of the corresponding second transmission structure group;
the control end of the odd driving input circuit 45 and the control end of the odd driving output circuit 43 both receive a first odd switching signal odd1; the control end of the even driving input circuit 42 and the control end of the even driving output circuit 46 both receive a first even switching signal even1; if the chip position identification code CID<1:0> indicates that the memory chip is in an odd-numbered position, the first odd switching signal odd1 is in an enabled state, and the first even switching signal even1 is in a disabled state; if the chip position identification code CID<1:0> indicates that the memory chip is in an even-numbered position, the first odd switching signal odd1 is in a disabled state, and the first even switching signal even1 is in an enabled state.
Here, the specific code value of the odd-numbered position is determined according to an actual application scenario, and the specific code value of the even-numbered position is determined according to the actual application scenario. In particular, the odd-numbered positions and even-numbered positions are not only parity of the actual positions of the chips; even-numbered positions refer to the positions of the memory chips requiring transmission of the second identification signal from the bottom surface to the top surface, and odd-numbered positions refer to the positions of the memory chips requiring transmission of the second identification signal from the top surface to the bottom surface. Referring to the foregoing Table 1 and Table 2, when CID<1:0>=00/10, it can be considered to be in an odd-numbered position; when CID<1:0>=01/11, it can be considered to be in an even-numbered position.
As such, referring to
It should be further noted that, the signals transmitted by the four second transmission structures are subjected to an OR logic to generate a corresponding second identification signal, which has the following advantages: the signals transmitted by the four second transmission structures are subjected to an OR logic to generate one second identification signal, and if a path corresponding to one of the second transmission structures is damaged, the overall transmitted second identification signal is not affected, and on the contrary, the other second transmission structures in the same group can still ensure the normal transmission of the second identification signal, so that the anti-damage capability of the memory chip is improved.
In some embodiments, as shown in
Referring to
As such, for the last memory chip of each stack unit, the result obtained from performing a plus-one operation on the stack position identification code SID<1:0> is output to the next memory chip; for the other memory chips of each stack unit, the stack position identification code SID<1:0> is directly transmitted to the next memory chip.
In some embodiments, referring to
The logic processing circuit 32 is further configured to generate a second identification signal signalB<1:0> of a default state based on the weak driving circuit if the second transmission structure does not transmit an effective signal, and generate a second identification signal signalB<1:0> based on the effective signal transmitted by the second transmission structure if the second transmission structure transmits the effective signal.
Illustratively, the default state is low level. In short, if there is no signal transmission in the second transmission structure (specifically, there is no external strong driving signal transmission in the second transmission structure), the second transmission structure is in a low-level state. As such, the weak driving circuit can enable the lowest or the uppermost chip to generate the second identification signal signalB<1:0> of a default state, and the transmission from bottom to top in the initialization process or the transmission from top to bottom in the normal operation process can be met only by changing the transmission direction of the second identification signal; in addition, as mentioned above, the signals transmitted by the four second transmission structures are subjected to an OR logic to generate one second identification signal, and if the path corresponding to one of the second transmission structures is damaged, the second transmission structure is in the low-level state, and the overall transmitted second identification signal is not affected.
In some embodiments, as shown in
Each odd driving input circuit 45 is coupled to one first logic device 323; the odd driving input circuit 45 includes a first inverting driving unit 451 and a second inverting driving unit 452; the output end of the second OR logic circuit 44 is connected to the input end of the first inverting driving unit 451, the output end of the first inverting driving unit 451 is connected to the input end of the second inverting driving unit 452, the output end of the second inverting driving unit 452 is connected to the input end of the logic operation circuit 33, and the control end of the first inverting driving unit 451 and the control end of the second inverting driving unit 452 both receive the first odd switching signal odd1; the output end of the first logic device 323 is connected to the input end of the first inverting driving unit 451, the first input end of the first logic device 323 receives a power-on indication signal poweron, and the second input end of the first logic device 323 is connected to the output end of the first inverting driving unit 451.
Each even driving input circuit 42 is coupled to one second logic device 324; the even driving input circuit 42 includes a third inverting driving unit 421 and a fourth inverting driving unit 422; the output end of the first OR logic circuit 41 is connected to the input end of the third inverting driving unit 421, the output end of the third inverting driving unit 421 is connected to the input end of the fourth inverting driving unit 422, the output end of the fourth inverting driving unit 422 is connected to the input end of the logic operation circuit 33, and the control end of the third inverting driving unit 421 and the control end of the fourth inverting driving unit 422 both receive the first even switching signal even1; the output end of the second logic device 324 is connected to the input end of the third inverting driving unit 421, the first input end of the second logic device 324 receives a power-on indication signal poweron, and the second input end of the second logic device 324 is connected to the output end of the third inverting driving unit 421.
In a specific embodiment, the first logic device 323 and the second logic device 324 are both two-input NOR gates; after the memory chip 10 is powered on, the power-on indication signal poweron is a high level; the second identification signal of a default state is a low level. However, this does not constitute a relevant limitation.
As such, after the weak driving circuit with the above structure is powered on, in the case that the second identification signal is determined, the input level state and output level state of the weak driving circuit are kept locked, and a static current path does not exist, such that the power consumption of the circuit is effectively reduced, and meanwhile the influence on other structures is avoided.
In another embodiment, the weak driving circuit may be implemented by a fixed resistance (relatively large value) grounded or in other ways not mentioned.
Illustratively, the first transmission structure may penetrate through the conductive via of the entire chip along a third direction, and the first transmission structure may also be of a type similar to the second transmission structure, i.e., consisting of a conductive via and a contact structure that do not penetrate through the entire memory chip. Here, the conductive via at least includes a through-silicon-via (TSV), specifically a vertical interconnection structure, or in other embodiments, the conductive via may be another via with a conductive function, which is not specifically limited.
Specifically, the first transmission structure is manufactured by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process; the conductive via in the second transmission structure is manufactured by any one or more of a via-first process and a via-middle process; different first transmission structures are electrically isolated from each other and different second transmission structures are also electrically isolated from each other.
It should be noted that the via-first process refers to a via process method in which a via structure is manufactured before a device structure, such as a metal oxide semiconductor field effect transistor (MOSFET, or MOS transistor), is manufactured. The via-middle process refers to a via process in which a via structure is formed during the manufacturing process in the process flow, often after a device is formed and before a stack is manufactured. The via-last process refers to a manufacturing process in which vias are formed at the front side of a wafer after a back end of line (BEOL) process is completed. The back side via-last process refers to a manufacturing process in which a via structure is formed at the back side of a wafer after a BEOL process is completed. That is, the via-first process may refer to first manufacturing vias and then manufacturing a circuit; the via-middle process may refer to first manufacturing a circuit and a portion of metal layers, then manufacturing vias, and finally manufacturing the remaining vias; the via-last process and the back side via-last process may refer to first manufacturing a circuit and metal layers and then manufacturing vias.
Additionally, the contact structure may include at least one or more of the following structures: a copper pillar, a metal interconnection line, and a bump.
As such, the embodiment of the present disclosure provides a memory chip 10, in which the transmission structure has 4-quadrant symmetry (arranged symmetrically about the first axis and about the second axis) and can be directly applied to face-to-face, back-to-back, and back-to-face stack structures; a rotation connection structure as shown in
In still another embodiment of the present disclosure, referring to
The logic chip 50 includes four third transmission structures (C0-C3) and B fourth transmission structure groups, where B is a natural number.
The logic chip 50 is configured to generate four first identification signals and transmit the four first identification signals to four third transmission structures in a one-to-one correspondence, where the four first identification signals indicate the chip position identification code of the memory chip (i.e., a memory chip 0) adjacent to the logic chip 50; the logic chip 50 is further configured to receive one second identification signal from each fourth transmission structure group and generate a stack position identification code based on B second identification signals in an initialization process, or generate B second identification signals of a default state and transmit one second identification signal to one fourth transmission structure group in a normal operation stage, so that other memory chips receive corresponding second identification signals from respective fourth transmission structure groups to generate their stack position identification codes.
In some embodiments, referring to
In particular, for the logic chip 50, the first identification signal signalA<0> is not necessarily transmitted by the first transmission structure C0, and may be transmitted by the first transmission structure C3 or the first transmission structure C2; the remaining first identification signals signalA also have similar problems, and it is necessary to consider the stacking form of the logic chip 50 and the memory chip 10, which can be understood with further reference to the following illustration of the chip stack structure.
Illustratively, in a normal operation process, four first identification signals signalA<3:0>=0001, so that CIDs<1:0> of the logic chip and the memory chip 0 are 00, referring to Table 1 above; in an initialization process, four first identification signals signalA<3:0>=1000, so that CIDs of the logic chip and the memory chip 0<1:0> are 11, referring to Table 2 above. As such, for the chip stack structure_50, the serial number of each memory chip during the normal operation is counted by starting from the logic chip 50 (for example, Table 1), and the serial number of each memory chip in an initialization process is counted by starting from the side far away from the logic chip 50 (for example, Table 2).
In some embodiments, referring to
The second signal generating circuit 64 is coupled to the B control output circuits 63 and is configured to generate B second identification signals of a default state in a normal operation stage and transmit the ith second identification signal signalB<i−1> to the input end of the ith control output circuit 63 in a one-to-one correspondence, where the output end of the ith control output circuit 63 is coupled to each fourth transmission structure in the ith fourth transmission structure group; i is a natural number less than or equal to B;
each fourth transmission structure in the ith fourth transmission structure group is coupled to the input end of the ith third OR logic circuit 61, the output end of the third OR logic circuit 61 is coupled to the input end of the ith control output circuit 63, and the output end of the ith control input circuit 62 is coupled to the internal circuit of the logic chip 50;
in an initialization process, the output end of the ith control input circuit 62 outputs the ith second identification signal signalB<i−1> (also equivalent to SID<i−1> in
where the control end of the control output circuit 63 receives the output enabled signal Outen, and the control end of the control input circuit 62 receives the input enabled signals Inen; if the logic chip 50 is in a normal operation stage, the input enabled signal Inen is in a disabled state, and the output enabled signal Outen is in an enabled state; if the logic chip 50 is in an initialization process, the input enabled signal Inen is in an enabled state, and the output enabled signal Outen is in a disabled state.
In other embodiments, the second signal generating circuit 64 and the control output circuit 63 may not be provided, but a weak driving circuit similar to that in the foregoing description is provided to generate the second identification signal of the default state.
As such, in a normal operation stage, four first identification signals signalA<3:0>=0001, and the chip position identification code CID<1:0>=00 (even-numbered position), and thereby the control output circuit 63 is in an enabled state (on), the control input circuit 62 is in a disabled state (off), and the SID<1:0> generated by the second signal generating circuit 64 at this time is 00, which is transmitted upwards as signalB<1:0> along the fourth transmission structure group; taking a chip stack structure formed by the logic chip 50 and eight memory chips as an example, in the initialization process, the four first identification signals signalA<3:0> in the logic chip is 1000, and the chip position identification code CID<1:0>=11 (odd-numbered position), and thereby the control output circuit 63 is in the disabled state, the control input circuit 62 is in the enabled state, and at this time, the logic chip 50 receives signalB<1:0>=10 from the fourth transmission structure group, i.e., SID<1:0>=10.
In some embodiments, the third transmission structure or the fourth transmission structure is manufactured by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process; different third transmission structures are electrically isolated from each other and different fourth transmission structures are also electrically isolated from each other.
That is, each of the third and fourth transmission structures may be a conductive via penetrating through the entire chip, or may take the form of a conductive via+contact structure that does not penetrate through the entire chip, or may take other forms not mentioned.
In still another embodiment of the present disclosure, referring to
The first memory chip 11 and the second memory chip 12 are stacked in a face-to-face manner, the second memory chip 12 and the third memory chip 13 are stacked in a back-to-back manner, and the third memory chip 13 and the fourth memory chip 14 are stacked in a face-to-face manner; the logic chip 50 and the first memory chip 11 (in the first stack unit) are stacked in a back-to-back manner; or the logic chip 50 and the first memory chip 11 are stacked in a face-to-back manner.
It should be understood that in
In the embodiment of the present disclosure, face-to-face stacking means that the top surfaces of two chips are approximately aligned with each other along the third direction and the center points and the first axes and the second axes of the top surfaces of the two chips are all aligned along the third direction; back-to-back stacking means that the top surfaces of two chips are approximately aligned with each other along the third direction; face-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of another chip along the third direction. The “chip” may refer to a logic chip or a memory chip in the case that whether it is a logic chip or a memory chip is not specified.
In some embodiments, it should be noted that in one possibility, for two chips connected in a face-to-face manner, (positions where the conductive vias are aligned along the third direction in) bonding surfaces of the two chips are electrically connected through a hybrid bonding structure (also referred to as a bonding post); for two chips connected in a back-to-back manner or in a face-to-back manner, (positions where the conductive vias are aligned along the third direction in) bonding surfaces of the two chips are electrically connected through conductive bumps (UBumps, also referred to as microbumps).
In another possibility, for two chips connected in a face-to-face manner or for two chips connected in a back-to-back manner or for two chips connected in a face-to-back manner, (positions where the conductive vias are aligned along the third direction in) bonding surfaces of the two chips are connected through a hybrid bonding structure. That is, (positions where the conductive vias are aligned along the third direction in) bonding surfaces of two chips connected in a face-to-face manner are electrically connected through a hybrid bonding structure, and (positions where the conductive vias are aligned along the third direction in) bonding surfaces of two chips connected in a back-to-back manner and (positions where the conductive vias are aligned along the third direction in) bonding surfaces of two chips connected in a face-to-back manner are also electrically connected through a hybrid bonding structure.
In yet another possibility, for two chips connected in a face-to-face manner or for two chips connected in a back-to-back manner, (positions where the conductive vias/contact structures are aligned along the third direction in) bonding surfaces of the two chips are connected through conductive bumps. That is, (positions where the conductive vias/contact structures are aligned along the third direction in) bonding surfaces of two chips connected in a face-to-face manner are connected through conductive bumps, and (positions where the conductive vias/contact structures are aligned along the third direction in) bonding surfaces of two chips connected in a back-to-back manner and (positions where the conductive vias/contact structures are aligned along the third direction in) bonding surfaces of two chips connected in a face-to-back manner are also connected through conductive bumps.
Here, the above chip may refer to the logic chip 50 or the memory chip 10.
It should be noted that compared to the conductive bumping process, the face-to-face connection using the hybrid bonding process enables adjacent chips to fit more closely with almost no gaps, thereby greatly reducing the height of the chip stack structure, which is one of the advantages of the face-to-face stacking. Of course, two chips connected in a back-to-back manner may also be connected through a hybrid bonding structure, but the connection performance is not as good as that of face-to-face stacking. It should be further noted that, when the transmission structure in the memory chip is a via of the via-last type or the back side via-last type from the back of the wafer, the bonding between the memory chips is the bonding of the vias; when the transmission structure in the memory chip is a via of the via-first type or the via-middle type, for two memory chips connected in a face-to-face manner, positions where the conductive vias are aligned along the third direction in the bonding surfaces of the two chips may be electrically connected through a hybrid bonding process or a conductive bumping process.
It should be noted that each chip includes a high-bit transmission region and a low-bit transmission region, and an arrow of each chip in
Meanwhile,
In some embodiments, referring to
Referring to
In short, the way in which the logic chip 50 is arranged at this time is the same as that of the fourth memory chip 14.
It should be noted that, due to process errors, the “alignment” in this embodiment is not an absolute alignment, and the deviation within a reasonable range can be regarded as alignment.
It should be noted that the entire area of the top surface of the logic chip 50 and the area of the top surface of the memory chip 10 may or may not be completely uniform. In the case that the area of the top surface of the logic chip 50 and that of the memory chip 10 are different, the alignment of the above signal zones is adaptively understood as “alignment of orientation”.
It should be noted that, referring to
As shown in
Each memory chip obtains a 0th-bit first identification signal signalA<0> from the first transmission structure_0 (A0), each memory chip obtains a first-bit first identification signal signalA<1> from the first transmission structure_1 (A1), each memory chip obtains a second-bit first identification signal signalA<2> from the first transmission structure_2 (A2), and each memory chip obtains a third-bit first identification signal signalA<3> from the first transmission structure_3 (A3).
As such, when the logic chip 50 transmits the first identification signals signalA<3:0> of the same combination value, the code values of the first identification signals signalA<3:0> received by the memory chips at different positions in the same stack unit are different, and the first identification signals of different memory chips are not required to be each transmitted by using an independent transmission structure, so that the occupied area of the chip and the cost are reduced.
In some embodiments, referring to
As shown in
It should be noted that the second transmission structure_0 (B0), the second transmission structure_1 (B1), the second transmission structure_2 (B2), and the second transmission structure_3 (B3) are all used for transmitting the second identification signal signalB<0>, and four signalB<0> (s) are subjected to an OR logic to generate an SID<0>, and the second transmission structure_4 (B4), the second transmission structure_5 (B5), the second transmission structure_6 (B6), and the second transmission structure_7 (B7) are all used for transmitting the second identification signal signalB<1>, and four signalB<1> (s) are subjected to an OR logic to generate an SID<1>.
It should be noted that in some operation scenarios, the diagonal stripe pillars between the chips in
In particular,
In other embodiments, the second axis BB′ may also be used as a boundary between the high-bit transmission region and the low-bit transmission region, and in this case, the alignment relationship of the first transmission structures and the third transmission structures is as shown in
In still other embodiments, referring to
In short, the way in which the logic chip 50 is arranged at this time is the same as that of the second memory chip 12.
Referring to
Referring to
In particular,
In other embodiments, the second axis BB′ may also be used as a boundary between the high-bit transmission region and the low-bit transmission region, and in this case, the alignment relationship of the first transmission structures and the third transmission structures is as shown in
As can be seen from the above, for the chip stack structure_70, the transmission structure along the third direction is different in different chips. Specifically, from a physical perspective, the conductive vias therein are still in a direct connection configuration, but from a perspective of absolute positions of the conductive vias, the conductive vias therein can be regarded as in a functionally rotational configuration, that is, a signal transmission effect similar to that of
Based on the aforementioned operation principle of the comparison circuit, the logic processing circuit, and the logic operation circuit in each memory chip, the transmission principle of SID and CID in the chip stack structure_70 is as follows:
Referring to Table 4, in the initialization process, after the initially combined signalA<3:0> is generated by the logic chip and then transmitted via the third transmission structures and the first transmission structures: the signalA<3:0> received by the memory chip 0 and the memory chip 4 is 1000, which is decoded to obtain CID<1:0>=11, which represents that the memory chip is the third memory chip in the stack unit to which it belongs; the signalA<3:0> received by the memory chip 1 and the memory chip 5 is 0100, which is decoded to obtain CID<1:0>=10, which represents that the memory chip is the second memory chip in the stack unit to which it belongs; the signalA<3:0> received by the memory chip 2 and the memory chip 6 is 0010, which is decoded to obtain CID<1:0>=01, which represents that the memory chip is the first memory chip in the stack unit to which it belongs; the signalA<3:0> received by the memory chip 3 and the memory chip 7 is 0001, which is decoded to obtain CID<1:0>=00, which represents that the memory chip is the 0th memory chip in the stack unit to which it belongs. Meanwhile, the SID is transmitted from top to bottom, and the weak driving circuit in the logic chip 7 enables its SID<1:0> to be 00; when the SID<1:0> is transmitted to the memory chip 4 downwards, since the memory chip 4 is the last one chip of the stack unit, the memory chip 4 performs a plus-one operation on the SID<1:0> and transmits it to the memory chip 3, and the SID<1:0> received by the memory chip 3 is 01, so that the SID<1:0> of the memory chip 0 to the memory chip 3 is 01, but the SID<1:0> of the memory chip 4 to the memory chip 7 is 00.
From the above, it can be seen that for the chip stack structure_70 provided according to an embodiment of the present disclosure, the transmission structures therein have four-quadrant symmetry (arranged symmetrically about the first axis and about the second axis) and can be directly applied to a face-to-face stack structure, a back-to-back stack structure, or a back-to-face stack structure; the chip stack structure has the following advantages: (1) the transmission of the chip position identification code CID can be achieved by only using four first transmission structures without respectively arranging four first transmission structures for each memory chip; in short, for the chip stack structure formed by eight memory chips and a logic chip, only four first transmission structures need to be arranged, and thus the number of the first transmission structures is small, and the chip area and the cost can be saved; (2) the transmission of the stack position identification code SID is performed through a second transmission structure formed by the conductive via and the contact structure together, and the last one memory chip is subjected to a plus-one operation, so that the transmission can be achieved only by two second transmission structure groups (i.e., eight second transmission structures), and thus the number of the second transmission structures is small, and the chip area and the cost are saved; (3) the second transmission structure can enable transmission from top to bottom or from bottom to top, so that transmission logic can be well achieved in the case of face-to-face stacking, and two numbering mechanisms in an initialization process and a normal operation process are supported; (4) the second transmission structure group transmits one bit of the stack position identification code SID together, so that correct transmission can still be ensured when part of the second transmission structures fail, and the failure handling performance is improved. In addition, compared with the memory chip 10 in
In still another embodiment of the present disclosure, referring to
The above description shows merely preferred embodiments of the present disclosure and is not intended to limit the protection scope of the present disclosure. It should be noted that in the present disclosure, the terms “include”, “comprise”, or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, a method, an item, or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, item, or apparatus. Without further limitation, an element defined by the phrase “including a . . . ” or “comprising a . . . ” does not exclude the presence of other identical elements in the process, method, item, or apparatus that includes the element. The serial numbers of the embodiments of the present disclosure described above are for the purpose of describing only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the method embodiments provided in the present disclosure may be combined in any manner without conflict to obtain new method embodiments. The features disclosed in the product embodiments provided in the present disclosure may be combined in any manner without conflict to obtain new product embodiments. The features disclosed in the method or device embodiments provided in the present disclosure may be combined in any manner without conflict to obtain new method or device embodiments. The above is only the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto; changes or substitutions that any one skilled in the art can easily think of within the technical scope disclosed by the present disclosure shall all fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the protection scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311343408.4 | Oct 2023 | CN | national |
This is a continuation of International Application No. PCT/CN2024/119830 filed on Sep. 19, 2024, which claims priority to Chinese Patent Application No. 202311343408.4 filed on Oct. 16, 2023. The disclosures of the above-referenced applications are hereby incorporated by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2024/119830 | Sep 2024 | WO |
| Child | 18945100 | US |
