The present invention relates to three-dimensional integrated circuit structures and circuits.
The electronics industry continues to strive for ever-increasing electronic functionality and performance in a wide variety of products, including (by way of example only) personal electronics (e.g., “smart” watches and fitness wearables), personal computers, tablet computers, wireless network components, televisions, cable system “set top” boxes, radar systems, and cellular telephones. Increased functionality and/or performance commonly translates to more transistors and other electronic components on an integrated circuit (IC) die. While the number of transistors per unit area of an IC die has increased over time as IC manufacturing process nodes have shrunk device dimensions, the two-dimensional (2-D) planar “footprint” of some IC dies has not decreased at the same rate, primarily owing to the use of more (albeit smaller) transistors to implement increased functionality and/or performance. The 2-D footprint of an IC die is one constraint on reducing the size of modules and circuit boards within products.
In order to shrink the 2-D footprint of an IC die, a number of three-dimensional (3-D) technologies have been developed that have focused on stacking and bonding aligned IC dies on different wafers (also known as wafer-to-wafer bonding), stacking and bonding individual IC dies on non-singulated IC dies on a wafer (also known as die-to-wafer bonding), and stacking and bonding an individual IC die on another IC die (also known as die-to-die bonding). One such technology may be referred to as “hybrid bonding interconnect” (HBI), in which the circuitry of a 2-D IC is divided and fabricated on different wafers or dies and then vertically stacked in a 3-D structure, with, for example, about half of the circuitry formed on a first or “bottom” wafer/die, and about half of the circuitry formed on a second or “top” wafer or die that is then bonded to the bottom wafer/die. Bonding of the two wafers/dies generally uses both dielectric materials (e.g., silicon dioxide, SiCN, SiCOH, and/or analogous alloys) and conductive interconnect materials (e.g., copper, aluminum, and/or their alloys). In general, a high density of interconnects between the top and bottom wafers/dies is desirable to achieve good communications between them. The interconnect pitch can be between about 0.2 to 10 μm, and preferably in approximately the 2-5 μm range. HBI technology has a demonstrated high interconnect density, is a planar technology that does not require underfill or carrier wafer integration, and enables formation of interconnects between two IC wafers/dies during the bonding stage of processing at relatively low temperatures (e.g., <400° C.).
As one example of the planar space savings provided by HBI technology,
HBI technology allows for a number of different stacking structures. By way of background,
After the last FEOL step, a wafer generally consists of isolated transistors without any interconnecting conductors. The back end of line (BEOL) is the second portion of IC fabrication where the individual devices (transistors, capacitors, resistors, inductors, etc.) are interconnected with conductors formed as part of or between one or more metal interconnect layers. BEOL includes fabrication of electrical contacts (pads), vias, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. For example, in
Although shown as a line in
While HBI technology is known and has been applied to some degree in the microprocessor, electronic memory, and digital logic fields, usage of HBI technology for analog circuitry, and particularly for radio frequency (RF) circuitry, has not been as widespread. RF circuitry poses a number of design challenges in 2-D ICs that can be exacerbated in 3-D designs, keeping in mind that each RF FET imposes some resistance, RON, when set to a conducting (ON) state, some capacitance, COFF, when set to a non-conducting (OFF) state, has a gate capacitance to be charged or discharged to change states, and may be operating at frequencies well in excess of 100 MHz. Thus, it is important, and often critical, to design for parasitic resistances, capacitances, and/or inductances that can adversely affect power efficiency, linearity, noise factor (NF), and impedance matching, etc., and/or cause generation of unwanted harmonic frequencies.
As one example of RF circuitry,
Shown in
The parallel arrangement of individual FETs 504 within the FET cells 502x provides the ability to convey current to meet a specification. In some applications, the number of parallel-connected FETs 504 within a cell 502x may be many hundreds of FETS. The serial arrangement of FET cells 502x provides the ability to withstand a specified design voltage. In some applications, the number of serially-connected FET cells 502x may be many tens of FET cells. Further, multiple switch arrays 500 may be implemented on a single die, such as for series and shunt switch circuits for an antenna tuning switch IC. Altogether, the number of FETs in one or more switch arrays 500 on an RF IC may exceed 100,000 drain-source finger pairs, many of which may be conveying frequencies well in excess of 100 MHz. In light of the parasitic resistances, capacitances, and/or inductances that can arise from laying out such a quantity of FETs, it should be appreciated that simply applying HBI technology to bond two ICs embodying such analog RF circuitry is not a simple design exercise.
Accordingly, there is a need for 3-D integrated circuit structures and circuits that enable high performance FET switch arrays while consuming less planar area than conventional 2-D IC dies.
The present invention encompasses 3-D integrated circuit structures and circuits that enable high performance FET switch arrays while consuming less planar area than conventional 2-D IC dies.
In one embodiment, an integrated FET switch circuit includes a first wafer/die including a first set of groups of FET cells laid out in a sequence, each group of FET cells including a first side drain bus and a second side source bus; and a second wafer/die joined to the first wafer/die through hybrid bonding interconnects and including a second set of groups of FET cells laid out in a sequence, each group of FET cells including a first side drain bus and a second side source bus; wherein the first side drain bus of each group in the first wafer/die is electrically connected through the hybrid bonding interconnects to the second side source bus of a first corresponding group in the second wafer/die; and wherein the second side source bus of each group in the first wafer/die is electrically connected through the hybrid bonding interconnects to the first side drain bus of a second corresponding group in the second wafer/die.
In another embodiment, an integrated FET switch circuit includes a first wafer/die including a first set of groups of FET cells laid out in a sequence, each group of FET cells including a first side drain bus and a second side source bus, the groups of FET cells being coupled in series; and a second wafer/die joined to the first wafer/die through hybrid bonding interconnects and including a second set of groups of FET cells laid out in a sequence, each group of FET cells including a first side drain bus and a second side source bus, the groups of FET cells being coupled in series; wherein the first side drain bus of each group in the first wafer/die is electrically connected through the hybrid bonding interconnects to the first side drain bus of a corresponding group in the second wafer/die; and wherein the second side source bus of each group in the first wafer/dic is electrically connected through the hybrid bonding interconnects to the second side source bus of the corresponding group in the second wafer/dic.
In yet another embodiment, an integrated FET switch circuit includes a first wafer/die including a first set of FET cells laid out in a sequence, the FET cells being coupled in series, each set of FET cells including a first side drain bus and a second side source bus; and a second wafer/die joined to the first wafer/die through hybrid bonding interconnects and including a second set of FET cells laid out in a sequence, the FET cells being coupled in series, each set of FET cells including a first side drain bus and a second side source bus; wherein the first side drain bus of the set of FET cells in the first wafer/die is electrically connected through the hybrid bonding interconnects to the first side drain bus of the set of FET cells in the second wafer/die; and wherein the second side source bus of the set of FET cells in the first wafer/die is electrically connected through the hybrid bonding interconnects to the second side source bus of the set of FET cells in the second wafer/die.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference numbers and designations in the various drawings indicate like elements.
The present invention encompasses 3-D integrated circuit structures and circuits that enable high performance FET switch arrays while consuming less planar area than conventional 2-D IC dies.
A distinct departure from the cell layout shown in
When the top wafer/die is flipped over on top of the bottom wafer/die during the HBI bonding process (e.g., the top wafer/die is figuratively “pivoted” around an HBI Junction Line 618 as suggested by the arrow 620), the HBI plugs 616 in associated FET cells 612a-612c, 614a-614c are aligned and can bond, completing the circuit structure shown schematically in
It should be appreciated that some dimensions in
Another advantage of the interleaved architecture shown in
Yet another advantage of the interleaved architecture shown in
The embodiment shown in
Although conventional FET cells with “outer” edge source and drain buses may be used in the embodiments shown in
Another advantage of “inside” placement of the drain and source buses 514a, 514b is reduced RON resistance, since the buses can be placed anywhere above the drain region 506 and source region 508 “fingers” and connected to those fingers via metal interconnect layers. Accordingly, the distance to both ends of such fingers is shorter—and hence lower in resistance-compared to bus placement at an edge of those fingers.
Each FET cell pair 912a, 914a-914b in a wafer/die includes one or more HBI plugs configured to electrically connect, after HBI bonding, with an HBI plug in the other wafer/die. Thus, for example, FET cell pair 912a in the bottom wafer/die includes an HBI plug 916 formed in electrical contact with a first side (left-side in the figure) drain bus D of FET cell pair 912a and configured to be bonded to a corresponding HBI plug 916 formed in electrical contact with a second side (right-side in the figure) source bus S of FET cell pair 914a. As another example, FET cell pair 912a in the bottom wafer/die includes an HBI plug 916 formed in electrical contact with a second side (right-side in the figure) source bus S of FET cell pair 912a and configured to be bonded to a corresponding HBI plug 916 formed in electrical contact with the first side (left-side in the figure) drain bus D of FET cell pair 914b. Again, while the HBI plugs 916 are shown formed directly over a drain bus D or source bus S, the HBI plugs 916 may be positioned elsewhere by appropriate use of conductive vias 906 and/or traces 908 (see, e.g.,
When the top wafer/die is flipped over on top of the bottom wafer/die during the HBI bonding process (e.g., the top wafer/die is figuratively “pivoted” around an HBI Junction Line 618 as suggested by the arrow 620), the HBI plugs 916 in associated FET cell pairs 912a, 914a-914b are aligned and can bond, completing the circuit structure shown schematically in
An advantage of the interleaved architecture shown in
Yet another advantage of the interleaved architecture shown in
As should be apparent, additional interleaving ratios may be used (e.g., 3:3 interleaving, 4:4 interleaving, etc.) by expanding the number of FET cells per group for the sets of cells associated with the top and bottom wafers/dies to include 3, 4, or more sequentially-connected FET cells before connecting the sets from wafer/die to wafer/die. Thus, most generally, the first and second sets of FET cells associated with the top and bottom wafers/dies each comprise one or more groups of FET cells, where each group includes n FET cells, where n≥1, and where, when n>1, the FET cells within a group are coupled in series. Note, however, that the size of the groups in the first and second sets need not be identical. For example, a bottom wafer/die may include n=2 FETs per group in the associated first set of FET cells, and a top wafer/die may include n=1 FET per group in the associated second set of FET cells. Since the groups in the sets of FET cells each comprise n FET cells, the left-most drain bus of each group of n FET cells can be considered a “first side” drain bus for the group, and the right-most source bus of each group of two FET cells can be considered a “second side” source bus for the group.
Although conventional FET cell pairs with “outer” edge source and drain buses may be used in the embodiments shown in
Although
Advantages of the parallel architecture shown in
Thus, while similar to the embodiment shown in
It may be useful for some applications to back-bias the FET cells of the top wafer/die, particularly for an SOI top wafer/die. This may be accomplished by fabricating a conductive aligned supplemental (CAS) gate structure adjacent to “primary” FETs in the FET layer of the top wafer/die. In essence, this aspect of the invention takes advantage of the existence of an inherent secondary parasitic back-channel FET of some primary FETs (e.g., an SOI FET) by fabricating such ICs using a process which allows access to the back side of the FET, such as the known Single Layer Transfer (SLT) process. Thereafter, a CAS gate structure is fabricated relative to a dielectric layer (e.g., the BOX layer) juxtaposed to a primary FET such that a control voltage applied to the CAS gate can regulate the electrical characteristics of the regions of the primary FET. The CAS gate structure may be formed, for example, using redistribution layer (RDL) techniques.
For example,
With the presence of the added CAS gate, a secondary FET (shown in a dashed square 1305) comprises the drain D, the source S, the CAS gate dielectric material (i.e., BOX layer 1308 and/or a passivation layer 1310) between the CAS gate and the body B of the primary FET 1304, and the CAS gate. A primary FET 1304 having an added CAS gate may be referred to as a “CAS-gated FET”. Further details regarding the structure and methods of fabricating CAS-gated FETs may be found in U.S. Pat. No. 10,580,903, issued Mar. 3, 2020, entitled “Semiconductor-On-Insulator Transistor with Improved Breakdown Characteristics”, assigned to the assignee of the present invention and hereby incorporated by reference.
The secondary FET is an independently controllable MOSFET regulated by applying control signals to the CAS gate. This is in contrast to the formerly inherently present but uncontrolled secondary parasitic back-channel FET of SOI FET embodiments. A CAS-gated FET thus generally presents as a five-terminal device: source S, drain D, primary gate G, CAS gate, and a body contact (often not shown in symbolic representations). Note that there may be circumstances in which a CAS gate may be beneficial, but the body contact may not be needed, and thus such an IC structure would present as a four-terminal device.
The relative thickness of the dielectric GOX layer 1306 for the primary gate G is generally much thinner (typically on the order of 2 to 3 orders of magnitude thinner) than the dielectric (i.e., BOX layer 1308 and/or a passivation layer 1310) for the CAS gate. Thus, the CAS gate generally will have a smaller impact on current and threshold voltage in the body B of the primary FET 1304 for a particular applied voltage level. However, by applying control voltages to a CAS gate (typically DC voltages), various effects can be induced in and around the body B of the corresponding primary FET 1304, depending on the type of transistor originally made in the SOI structure. For example, for a partially depleted SOI primary FET 1304, the primary gate G and the CAS gate are isolated by undepleted silicon in the body of the device. Hence, voltages applied to the CAS gate will mostly affect back-channel leakage current, meaning leakage current that cannot be controlled by the primary gate G. Such leakage currents can be large compared to the leakage currents of the main body B under the primary gate G, often because the primary FET is designed to ensure low leakage currents. For example, for RF and analog circuits, very low leakage is key to proper performance. Charged nodes or storage capacitors can be discharged by leakage currents, thereby forcing a recharge cycle that can induce spurious signals (“spurs”) in analog circuits that can degrade RF and analog system performance.
For a so-called fully depleted SOI primary FET 1304, a voltage applied to the CAS gate will couple capacitively to the primary body B of the primary FET 1304, thereby inducing some threshold voltage shift in the primary FET. The impact of leakage current in a fully depleted FET will have the same effects as for a partially depleted FET.
Another benefit of FETs having a CAS gate is that multiple FET devices can be identically fabricated (e.g., same implant doping levels) but controlled by respective CAS control voltages to operate with different threshold voltages, VT. For example, in some applications, it may be useful to have some FETs with a lower VT while other FETs have a higher VT. This can be achieved by biasing the CAS gates of such FETs with different voltage values, which leads to the otherwise identical FETs exhibiting different threshold voltages VT.
CAS-gated FETs generally have a higher voltage handling capability (i.e., a higher breakdown voltage VBD) than conventional FETs (typically exceeding an added 1-2 VDC of voltage handling capability for an SOI NMOS CAS-gated FET) due to the ability to bias the CAS gate such that the body B is more depleted than can be accomplished by the primary gate G alone. In addition, CAS-gated FETs generally have a lower ON resistance, RON, than conventional FETs (typically exceeding about 15% lower for switch FETs and about 30% lower for regular FETs, for SOI NMOS CAS-gated FET) due to the ability to bias the CAS gate such that the body B is more enhanced than can be accomplished by the primary gate G alone, resulting in lower insertion loss as well as a higher current capacity without increasing heat generation. CAS-gated FETs may have lower leakage currents in subthreshold operating conditions due to the ability to bias the back-channel region of the body in a fully OFF condition. Notably, all of these benefits—particularly high breakdown voltage VBD, low RON, and lower leakage currents—are available from the same CAS-gated FET under different operating conditions, just by varying the bias voltage applied to its CAS gate.
The advantageous characteristics of CAS-gated FETs are particularly useful for signal switching applications, and especially RF signal switching circuits and systems. For example, referring to
Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.
As one example of further integration of embodiments of the present invention with other components,
The substrate 1400 may also include one or more passive devices 1406 embedded in, formed on, and/or affixed to the substrate 1400. While shown as generic rectangles, the passive devices 1406 may be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected by conductive traces on or in the substrate 1400 to other passive devices 1406 and/or the individual ICs 1402a-1402d.
The front or back surface of the substrate 1400 may be used as a location for the formation of other structures. For example, one or more antennae may be formed on or affixed to the front or back surface of the substrate 1400; one example of a front-surface antenna 1408 is shown, coupled to an IC die 1402b, which may include RF front-end circuitry. Thus, by including one or more antennae on the substrate 1400, a complete radio may be created.
Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.
Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.
As an example of wireless RF system usage,
A wireless device 1506 may be capable of communicating with multiple wireless communication systems 1502, 1504 using one or more of telecommunication protocols such as the protocols noted above. A wireless device 1506 also may be capable of communicating with one or more satellites 1508, such as navigation satellites (e.g., GPS) and/or telecommunication satellites. The wireless device 1506 may be equipped with multiple antennas, externally and/or internally, for operation on different frequencies and/or to provide diversity against deleterious path effects such as fading and multi-path interference.
The wireless communication system 1502 may be, for example, a CDMA-based system that includes one or more base station transceivers (BSTs) 1510 and at least one switching center (SC) 1512. Each BST 1510 provides over-the-air RF communication for wireless devices 1506 within its coverage area. The SC 1512 couples to one or more BSTs 1510 in the wireless system 1502 and provides coordination and control for those BSTs 1510.
The wireless communication system 1504 may be, for example, a TDMA-based system that includes one or more transceiver nodes 1514 and a network center (NC) 1516. Each transceiver node 1514 provides over-the-air RF communication for wireless devices 1506 within its coverage area. The NC 1516 couples to one or more transceiver nodes 1514 in the wireless system 1504 and provides coordination and control for those transceiver nodes 1514.
In general, each BST 1510 and transceiver node 1514 is a fixed station that provides communication coverage for wireless devices 1506, and may also be referred to as base stations or some other terminology known in the telecommunications industry. The SC 1512 and the NC 1516 are network entities that provide coordination and control for the base stations and may also be referred to by other terminologies known in the telecommunications industry.
An important aspect of any wireless system, including the systems shown in
The receiver path Rx receives over-the-air RF signals through at least one antenna 1602 and a switching unit 1604, which may be implemented with active switching devices (e.g., field effect transistors or FETs, including FET switch arrays of the types disclosed in
In the illustrated example, a transmitter path Tx includes Baseband, Back-End, IF Block, and RF Front End sections (again, in some implementations, the differentiation between sections may be different). Digital data from one or more system components 1624 is transformed to an analog signal by a digital-to-analog converter 1626, the output of which is applied to a modulator 1628, which also may be coupled to the second local oscillator 1620. The modulated output of the modulator 1628 may be subjected to an IF filter 1630 before being amplified by an IF amplifier 1632. The output of the IF amplifier 1632 is then combined in a mixer 1634 with the output of the first local oscillator 1612 to produce an RF signal. The RF signal may be amplified by a driver 1636, the output of which is applied to a power amplifier (PA) 1638. The amplified RF signal may be coupled to an RF filter 1640, the output of which is coupled to at least one antenna 1602 through the switching unit 1604.
The operation of the transceiver 1600 is controlled by a microprocessor 1642 in known fashion, which interacts with system control components 1644 (e.g., user interfaces, memory/storage devices, application programs, operating system software, power control, etc.). In addition, the transceiver 1600 will generally include other circuitry, such as bias circuitry 1646 (which may be distributed throughout the transceiver 1600 in proximity to transistor devices), electro-static discharge (ESD) protection circuits, testing circuits (not shown), factory programming interfaces (not shown), etc.
In modern transceivers, there are often more than one receiver path Rx and transmitter path Tx, for example, to accommodate multiple frequencies and/or signaling modalities. Further, as should be apparent to one of ordinary skill in the art, some components of the transceiver 1600 may be positioned in a different order (e.g., filters) or omitted. Other components can be (and often are) added, such as (by way of example only) additional filters, impedance matching networks, variable phase shifters/attenuators, power dividers, etc.
As discussed above, the current invention enables high performance FET switch arrays while consuming less planar area than conventional 2-D IC dies. As a person of ordinary skill in the art will understand, a system architecture is beneficially impacted by the current invention in critical ways, including enabling smaller sizes while maintaining important RF characteristics such as power efficiency, linearity, noise factor (NF), and impedance matching, without significant generation of unwanted harmonic frequencies.
Another aspect of the invention includes methods for creating integrated FET switch circuits. For example,
As another example,
As yet another example,
Additional aspects of the above method may include one or more of the following: wherein the integrated FET switch circuit is an integrated FET radio frequency switch circuit; wherein each group within the first set of groups and the second set of groups includes only one FET cell; wherein each group within the first set of groups and the second set of groups includes only two serially-coupled FET cells; wherein each group within the first set of groups and the second set of groups includes only n serially-coupled FET cells, where n≥1; wherein the number of FET cells in the groups of the first set of groups is different from the number of FET cells in the groups of the second set of groups; wherein at least one FET cell in at least one of the first set of groups and/or the second set of groups includes a plurality of FETs coupled in parallel; wherein the FET cells of the second set of groups are CAS-gated FETs; wherein the FET cells of the second set of groups are back-biased; wherein the first side drain bus and the second side source bus of each group within the first set of groups and the second set of groups are spaced inside the edges of the group; and/or further including at least one intermediate hybrid bonding interconnect between the first set of FET cells and the second set of FET cells.
As the above examples should make clear, the invention applies to wafer-to-wafer HBI bonding, die-to-wafer HBI bonding, and die-to-die HBI bonding. Further, techniques analogous to HBI may also be used to bond top and bottom wafers/dies having the same architectures encompassed by the present invention. In addition, while several patterns of HBI connections have been shown, it should be appreciated that additional patterns may be used (e.g., 3:3 interleaving, 4:4 interleaving, etc.) and that combinations of some of the patterns may be used (e.g., 1:1 interleaving for a first part of a switch circuit and 2:2 interleaving for a second part of the switch circuit). Note also that metal interconnect layers with smaller dimensions (e.g., such as metal interconnect layers M1 and/or M2) may be used as routing layers to connect with smaller pitch HBI plugs. Thus, in general, a 3-D HBI stack of FET cells may be modified to add or remove metal layers based on HBI pitch and the intended application.
The substrates of the top and bottom wafers/dies may be of various types, including (in either order) SOI/SOI, SOI/bulk silicon bulk, silicon/bulk silicon, engineered substrate/bulk silicon, and engineered substrate/SOI. Engineered substrates include but are not limited to carbon-doped silicon, strained silicon, and porous silicon substrates, as well as other types having some modification of the constituent layers that compose the wafer/die through additional processing steps to make the wafer/die a better substrate for RF applications, such as by adding a trap rich layer right under the BOX layer of a SOI wafer/die to help improve RF performance.
The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.
As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.
With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and/or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.
Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BICMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, MESFET, SiGe, InP, ESOS (epitaxial SOS), BSOS (bonded SOS), and SOI-on-anything (e.g., SOG=silicon-on-glass, SOC=silicon-on-ceramic, etc.) technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.
A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.
It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).
The present application is a continuation of International Application No. PCT/US2023/017960 filed on Apr. 7, 2023, which, in turn, claims priority to U.S. Provisional Patent Application No. 63/330,610, filed on Apr. 13, 2022, for “3-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES AND CIRCUITS,” the contents of all of which are incorporated herein by reference in their entirety.
Number | Date | Country | |
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63330610 | Apr 2022 | US |
Number | Date | Country | |
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Parent | PCT/US2023/017960 | Apr 2023 | WO |
Child | 18884764 | US |