Some memory cells can include a floating gate and a nitride wrapped around three sides of the floating gate. Undesired charges may become trapped in the nitride, particularly in portions of the nitride that are not directly between the control gate and the floating gate. The threshold voltage (Vt) of a cell may be altered by the undesired charges trapped in the nitride.
The following detailed description refers to the accompanying drawings which show, by way of illustration, specific aspects and embodiments in which the present subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present subject matter.
The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer, such as a substrate, regardless of the actual orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side”, “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the actual orientation of the wafer or substrate. The terms “wafer” and “substrate” are used herein to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
Generally discussed herein are three-dimensional (3D) memories, memory cells, and methods of making and using the same. In one or more embodiments, a 3D vertical memory can include a memory stack. A memory stack can include a stack of at least two memory cells and a dielectric between adjacent memory cells, where each memory cell includes a control gate (CG) and a charge storage structure, such as a floating gate (FG) or charge trap (CT), configured to store electrons or holes accumulated on it. Information is represented by the amount of electrons or holes stored by the cell. The memory stack can further include a barrier material, such as nitride in an inter-gate dielectric (IGD) comprising a composite of oxide-nitride-oxide (“ONO”), where the IGD can be between the charge storage structure and the CG. The barrier material and the charge storage structure can be laterally positioned adjacent, horizontally aligned to each other, or have substantially equal heights.
A NAND array architecture is an array of memory cells arranged such that the memory cells of the array are coupled in logical rows to access lines (which are coupled to, and in some cases are at least partially formed by, the CGs of the memory cells), which are conventionally referred to as word lines. Some memory cells of the array are coupled together in series between a source line and the data line, which is conventionally referred to as a bit line.
Memory cells in NAND array architecture can be programmed to a desired data state. For example, electric charge can be accumulated (e.g., placed) on, or removed from, an FG of a memory cell to program the cell into a desired one of a number of data states. A memory cell conventionally referred to as a single level cell (SLC) can be programmed to a desired one of two data states, e.g., a “1” or a “0” state. Memory cells conventionally referred to as multilevel cells (MLCs) can be programmed to a desired one of more than two data states.
When electrons are stored on the FG, they modify the Vt of the cell. Thus, when the cell is “read” by placing a specific voltage on the CG (e.g., by driving the access line coupled to the cell with a read voltage), electrical current will either flow or not flow in the cell's channel depending on the Vt of the cell and the specific voltage placed on the CG. This presence or absence of current can be sensed and translated into 1's and 0's, reproducing the stored data.
Each memory cell may not directly couple to a source line and a data line. Instead, the memory cells of an example array may be arranged together in strings, typically of 4, 8, 16, 32, or more cells each, where the memory cells in the string are coupled together in series between a common source line and a data line.
A NAND array can be accessed by a row decoder activating a row of memory cells by driving the access line coupled to those cells with a voltage. In addition, the access lines coupled to the unselected memory cells of each string can be driven with a different voltage. For example, the unselected memory cells of each string can be driven with a pass voltage so as to operate them as pass transistors, allowing them to pass current in a manner that is unrestricted by their programmed data states. Current can then flow from the source line to the data line through each memory cell of the series coupled string, restricted by the memory cell of each string that is selected to be read. This places the currently encoded, stored data values of the row of selected memory cells on the data lines. A page of data lines is selected and sensed, and then individual data words can be selected from the sensed data words from the page and communicated from the memory apparatus.
The flash memory, such as a NAND array, may be formed as a 3D memory with stacks of more than one memory cells. The CGs for the memory cells may be adjacent to CG recesses.
The barrier film 104B can include a second dimension 314B that is substantially equal through its first dimension 312B (e.g., the barrier film 104B can include a substantially uniform thickness across its entire first dimension 312B), such as shown in
The barrier film 104B can include a face and the FG 102B can have a face, such as the face corresponding to the plane 316A, opposing the face of the barrier film 104B and substantially parallel to the face of the barrier film 104B. Each part of the face of the barrier film 104B can be separated from the face of the floating gate 102B by a substantially equal distance, such as shown in
The FG 102B can have a planar side (e.g., the side corresponding to the plane 316A) facing the barrier film 104B. The CG 106 can have a planar side (e.g., the side corresponding to the plane 316B) facing the barrier film 104B. The barrier film 104B can have a first planar side facing and substantially parallel to the planar side of the FG 102B and a second planar side facing and substantially parallel to the planar side of the CG 106. The first dimension 312C of the CG 106 can be substantially equal to the corresponding first dimension 312B of the barrier film 104B, such as shown in
As used herein, “vertical memory string” can mean a “vertical memory stack” (e.g., alternating CG 106 and tier dielectric 524 layers with CG recesses 530 between tier dielectric 524 layers) with a CG recess 530 filled in with dielectric 108, an FG 102, and barrier film 104, and including a pillar 110 (e.g., a filled trench 528, such as a trench filled with polysilicon). Also, the term “vertical memory” can be used to indicate a final form.
The trench 528 and the CG recesses 530 can be at least partially filled with a barrier material 532, such as shown in
A second layer of dielectric 108 (which may or may not be the same dielectric material as the first layer) can be formed, such as by growing the dielectric 108 using an in situ steam generation process (ISSG), on the barrier films 104, such as shown in
A third layer of dielectric 108, such as a tunnel oxide, can be formed (e.g., grown) on the FGs 102, and a pillar 110 can be formed in the trench 528, such as shown in
The trench 528 and the CG recesses 530 can be at least partially filled with a sacrificial material 636. As shown in
The barrier material 532 can be etched to at least partially remove the barrier material 532 from the trench 528 and the CG recesses 530. As shown in
A second layer of dielectric 108 can be grown on exposed surfaces of the barrier films 104, such as shown in
The trench 528 and the CG recesses 530 can be at least partially filled with a charge storage material 534, such as shown in
The vertical memory 600 depicted in
Alternatively, the vertical memory 800 depicted in
A problem associated with memory cells that include a barrier film, such as nitride, adjacent to an FG on more than one side can be charges getting trapped in portions of the nitride that do not separate the FG and a CG (e.g., in portions of the nitride that are not directly between the FG and the CG). Also, trapped charge can migrate along the IGD, such as through program, erase, or temperature cycling. Such charge trapping or movement can alter the threshold voltage (Vt) of the memory cell or degrade incremental step pulse programming (ISPP) relative to memory cells that do not have such charge trapping in the nitride.
Such charge trapping or migration on the nitride can be at least partially eliminated by including nitride adjacent to only one surface of the FG (e.g., by including nitride that is substantially rectangular and not “U” shaped). Such a configuration can include charge being trapped on the FG rather than on the nitride.
An advantage of one or more embodiments can include reducing the incidents of erase saturation in memory cells. Another advantage can include improved alignment between the FG and CG due to eliminating a source of variation in manufacturing, such as the nitride wrapping in irregular shapes around corners in a CG recess or a tier oxide. Instead the FG shape and size can be defined by a plasma enhanced chemical vapor deposition (PECVD) process, which can be a substantially uniform stack deposition process.
Program and erase properties of a memory cell are a function of a gate coupling ratio, which is a function of a capacitance between the FG and the CG of a memory cell. With a wrapped nitride, such as shown in
Another advantage can include an increased channel length to memory cell first dimension ratio, such a configuration can increase the reliability of the respective memory cell.
The above description and the drawings illustrate some embodiments of the invention to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description.
This application is a continuation of U.S. application Ser. No. 14/610,755, filed Jan. 30, 2015, issued as U.S Pat. No. 9,230,986, which is a divisional of U.S. application Ser. No. 13/748,747, filed Jan. 24, 2013, issued as U.S. Pat. No. 8,946,807, all of which are incorporated herein by reference in their entirety.
Number | Name | Date | Kind |
---|---|---|---|
6159797 | Lee | Dec 2000 | A |
6445029 | Lam et al. | Sep 2002 | B1 |
6583009 | Hui et al. | Jun 2003 | B1 |
7369436 | Forbes | May 2008 | B2 |
7682902 | Hsiao et al. | Mar 2010 | B2 |
7910446 | Ma et al. | Mar 2011 | B2 |
8124478 | Park et al. | Feb 2012 | B2 |
8187936 | Alsmeier et al. | May 2012 | B2 |
8258034 | Ramaswamy et al. | Sep 2012 | B2 |
8581321 | Son et al. | Nov 2013 | B2 |
8680605 | Jeon | Mar 2014 | B2 |
8946807 | Hopkins et al. | Feb 2015 | B2 |
9171863 | Wang | Oct 2015 | B2 |
9184175 | Dennison et al. | Nov 2015 | B2 |
9230986 | Hopkins et al. | Jan 2016 | B2 |
9231086 | Khoueir et al. | Jan 2016 | B2 |
9608000 | Hopkins et al. | Mar 2017 | B2 |
9793282 | Dennison et al. | Oct 2017 | B2 |
20050006697 | Hsieh | Jan 2005 | A1 |
20050133851 | Forbes | Jun 2005 | A1 |
20060237768 | Forbes et al. | Oct 2006 | A1 |
20070047304 | Lee et al. | Mar 2007 | A1 |
20080012061 | Ichige et al. | Jan 2008 | A1 |
20080067583 | Kidoh et al. | Mar 2008 | A1 |
20080173928 | Arai et al. | Jul 2008 | A1 |
20080253183 | Mizukami et al. | Oct 2008 | A1 |
20080277720 | Youn et al. | Nov 2008 | A1 |
20090026460 | Ou | Jan 2009 | A1 |
20090121271 | Son et al. | May 2009 | A1 |
20090184360 | Jin | Jul 2009 | A1 |
20090283813 | Ishii et al. | Nov 2009 | A1 |
20090283819 | Ishikawa et al. | Nov 2009 | A1 |
20100003795 | Park | Jan 2010 | A1 |
20100163968 | Kim et al. | Jul 2010 | A1 |
20100181612 | Kito et al. | Jul 2010 | A1 |
20100187592 | Chen et al. | Jul 2010 | A1 |
20100200908 | Lee et al. | Aug 2010 | A1 |
20100240205 | Son et al. | Sep 2010 | A1 |
20100323505 | Ishikawa et al. | Dec 2010 | A1 |
20110201167 | Satonaka et al. | Aug 2011 | A1 |
20110220987 | Tanaka et al. | Sep 2011 | A1 |
20110248334 | Sandhu et al. | Oct 2011 | A1 |
20110294290 | Nakanishi | Dec 2011 | A1 |
20120001247 | Alsmeier | Jan 2012 | A1 |
20120001249 | Alsmeier et al. | Jan 2012 | A1 |
20120058629 | You et al. | Mar 2012 | A1 |
20120132981 | Imamura et al. | May 2012 | A1 |
20120217564 | Tang et al. | Aug 2012 | A1 |
20120326221 | Sinha | Dec 2012 | A1 |
20130049095 | Whang | Feb 2013 | A1 |
20130171788 | Yang et al. | Jul 2013 | A1 |
20140131784 | Davis | May 2014 | A1 |
20140203344 | Hopkins et al. | Jul 2014 | A1 |
20140264532 | Dennison et al. | Sep 2014 | A1 |
20150140797 | Hopkins et al. | May 2015 | A1 |
20160049417 | Dennison et al. | Feb 2016 | A1 |
20160093626 | Izumi et al. | Mar 2016 | A1 |
20160351580 | Hopkins et al. | Dec 2016 | A1 |
20170200801 | Hopkins et al. | Jul 2017 | A1 |
20170365615 | Dennison et al. | Dec 2017 | A1 |
Number | Date | Country |
---|---|---|
1401140 | Mar 2003 | CN |
1791974 | Jun 2006 | CN |
101118910 | Feb 2008 | CN |
101223640 | Jul 2008 | CN |
101292351 | Oct 2008 | CN |
101364614 | Feb 2009 | CN |
101512729 | Aug 2009 | CN |
101847602 | Sep 2010 | CN |
105027285 | Nov 2015 | CN |
105164808 | Dec 2015 | CN |
105027285 | Jun 2017 | CN |
107256867 | Oct 2017 | CN |
2973710 | Jan 2016 | EP |
2007005814 | Jan 2007 | JP |
2007294595 | Nov 2007 | JP |
2009295617 | Dec 2009 | JP |
2012094694 | May 2012 | JP |
2012119445 | Jun 2012 | JP |
2012146773 | Aug 2012 | JP |
2012227326 | Nov 2012 | JP |
2016514371 | May 2016 | JP |
5965091 | Aug 2016 | JP |
1020100104908 | Sep 2010 | KR |
1020110130916 | Dec 2011 | KR |
1020120101818 | Sep 2012 | KR |
10-1764626 | Jul 2017 | KR |
201442211 | Nov 2014 | TW |
201507168 | Feb 2015 | TW |
201526207 | Jul 2015 | TW |
I548065 | Sep 2016 | TW |
I575716 | Mar 2017 | TW |
201737472 | Oct 2017 | TW |
WO-2006132158 | Dec 2006 | WO |
WO-2012009140 | Jan 2012 | WO |
WO-2014116864 | Jul 2014 | WO |
WO-2014149740 | Sep 2014 | WO |
Entry |
---|
US 9,754,952, 09/2017, Dennison et al. (withdrawn) |
“International Application Serial No. PCT/US2014/012798, International Search Report dated May 19, 2014”, 3 pgs. |
“International Application Serial No. PCT/US2014/012798, Written Opinion dated May 19, 2014”, 11 pgs. |
“International Application Serial No. PCT/US2014/020658, International Search Report dated Jun. 26, 2014”, 3 pgs. |
“International Application Serial No. PCT/US2014/020658, Written Opinion dated Jun. 26, 2014”, 4 pgs. |
Hang-Ting, Lue, et al., “A Novel Planar Floating-Gate (FG) / Charge Trapping (CT) NAND Device Using BE-SONOS Inter-Poly Dielectric (IPD)”, In proceeding of: Electron Devices Meeting (IEDM), (2009), 34.3:1-4. |
Kitamura, Takuya, et al., “A Low Voltage Operating Flash Memory Cell with High Coupling Ratio”, (1998). |
Seo, Moon-Sik, et al., “The 3 dimensional Vertical FG NAND Flash Memory Cell Arrays with the Novel Electrical S/D/ Technique using the Extending Sidewall Contral Gate (ESCG)”, 4 pages. |
“European Application Serial No. 14770149.4, Invitation Pursuant to Rule 62a(1) EPC dated Aug. 30, 2016”, 2 pgs. |
“Korean Application Serial No. 10-2015-7029545, Office Action dated Oct. 18, 2016”, (With English Translation), 13 pgs. |
Kuppurao, Satheesh, et al., “EQuipment Frontiers: Thermal Processing: In situ steam generation: A new rapid thermal oxidation technique”, Solid State Technology, (Jul. 2000), Cover, Index, 233-239. |
“U.S. Appl. No. 13/838,297, Notice of Allowance dated Jul. 9, 2015”, 9 pgs. |
“U.S. Appl. No. 13/838,297, Response dated Mar. 16, 2015 to Non Final Office Action dated Dec. 16, 2014”, 10 pgs. |
“U.S. Appl. No. 14/722,824, Non Final Office Action dated Jul. 25, 2016”, 9 pgs. |
“U.S. Appl. No. 14/722,824, Response dated Jul. 11, 2016 to Restriction Requirement dated May 10, 2016”, 7 pgs. |
“U.S. Appl. No. 14/722,824, Restriction Requirement dated May 10, 2016”, 6 pgs. |
“U.S. Appl. No. 14/925,589, Non Final Office Action dated May 19, 2016”, 6 pgs. |
“U.S. Appl. No. 14/925,589, Response dated Aug. 18, 2016 to Non Final Office Action dated May 19, 2016”, 6 pgs. |
“Chinese Application Serial No. 201480013075.1, Preliminary Amendment dated May 30, 2016”, W/ English Claims, 48 pgs. |
“European Application Serial No. 14743125.8, Extended European Search Report dated Jun. 21, 2016”, 8 pgs. |
“European Application Serial No. 14743125.8, Preliminary Amendment dated Mar. 9, 2016”, 13 pgs. |
“European Application Serial No. 14770149.4, Preliminary Amendment dated Apr. 28, 2016”, 22 pgs. |
“International Application Serial No. PCT/US2014/012798, International Preliminary Report on Patentability dated Aug. 6, 2015”, 13 pgs. |
“International Application Serial No. PCT/US2014/020658, International Preliminary Report on Patentability dated Sep. 24, 2015”, 6 pgs. |
“Japanese Application Serial No. 2016-500651, Notice of Rejection dated Mar. 1, 2016”, W/ English Translation, 4 pgs. |
“Japanese Application Serial No. 2016-500651, Response dated May 20, 2016 to Notice of Rejection dated Mar. 1, 2016”, W/ English Claims, 6 pgs. |
“Protrusion”, Merriam-Webster Dictionary, 2 pgs. |
“Taiwanese Application Serial No. 103102815, Amendment dated Nov. 10, 2014”, W/ English Claims, 52 pgs. |
“Taiwanese Application Serial No. 104110136, Office Action dated Jan. 26, 2016”, W/ English Translation, 3 pgs. |
“Taiwanese Application Serial No. 104110136, Response dated Apr. 28, 2016 to Office Action dated Jan. 26, 2016”, W/ English Claims, 7 pgs. |
“U.S. Appl. No. 14/925,589, Corrected Notice of Allowance dated Jun. 27, 2017”, 2 pgs. |
“European Application Serial No. 14743125.8, Communication Pursuant to Article 94(3) EPC dated May 22, 2017”, 6 pgs. |
“Japanese Application Serial No. 2015-555280, Office Action dated Jul. 4, 2017”, w/English Translation, 27 pgs. |
“Taiwanese Application Serial No. 103109314, Response dated Oct. 3, 2017 to Office Action dated Apr. 6, 2017”, w/English Translation, 41 pgs. |
“Japanese Application Serial No. 2015-555280, Response dated Oct. 12, 2017 to Office Action dated Jul. 4, 2017”, w/English Claims, 17 pgs. |
“Chinese Application Serial No. 201480024450.2, Office Action dated May 3, 2017”, With English Translation, 17 pgs. |
“Korean Application Serial No. 10-2015-7029545, Response dated Apr. 25, 2017 to Final Office Action dated Mar. 27, 2017”, W/English Claims, 14 pgs. |
“Taiwanese Application Serial No. 103109314, Office Action dated Apr. 6, 2017”, w/ English Translation, 23 pgs. |
“U.S. Appl. No. 14/925,589, Notice of Allowance dated Apr. 27, 2017”, 7 pgs. |
“Japanese Application Serial No. 2015-555280, Office Action dated Feb. 27, 2018”, 31 pgs. |
“U.S. Appl. No. 14/925,589, Corrected Notice of Allowance dated Sep. 13, 2017”, 2 pgs. |
“Korean Application Serial No. 10-2017-7021238, Office Action dated Aug. 16, 2017”, with English translation of the rejections, 5 pgs. |
“U.S. Appl. No. 15/691,477, Notice of Allowance dated Oct. 10, 2017”, 8 pgs. |
“Chinese Application Serial No. 201480024450.2, Response dated Sep. 18, 2017 to Office Action dated May 3, 2017”, 18 pgs. |
“European Application Serial No. 14743125.8, Response dated Dec. 1, 2017 to Communication Pursuant to Article 94(3) EPC dated May 22, 2017”, 11 pgs. |
“Korean Application Serial No. 10-2017-7021238, Response dated Oct. 16, 2017 to Office Action dated Aug. 16, 2017”, 12 pgs. |
U.S. Appl. No. 13/838,297, filed Mar. 15, 2013, U.S. Pat. No. 9,184,175, Floating Gate Memory Cells in Vertical Memory. |
U.S. Appl. No. 14/925,589, filed Oct. 28, 2015, Floating Gate Memory Cells in Vertical Memory. |
U.S. Appl. No. 13/748,747, filed Jan. 24, 2013, U.S. Pat. No. 8,946,807, 3D Memory. |
U.S. Appl. No. 14/610,755, filed Jan. 30, 2015, U.S. Pat. No. 9,230,986, 3D Memory. |
U.S. Appl. No. 14,722,824, filed May 27, 2015, Devices and Methods Including an Etch Stop Protection Material. |
U.S. Appl. No. 15/470,617, filed Mar. 27, 2017, Devices and Methods Including an Etch Stop Protection Material. |
“U.S. Appl. No. 14/722,824, Amendment Under 37 C.F.R. filed 2-/-17”, 4 pgs. |
“U.S. Appl. No. 14/722,824, Examiner Interview Summary dated Nov. 14, 2016”, 3 pgs. |
“U.S. Appl. No. 14/722,824, Notice of Allowance dated Nov. 7, 2016”, 5 pgs. |
“U.S. Appl. No. 14/722,824, PTO Response to Rule 312 Communication dated Feb. 15, 2017”, 2 pgs. |
“U.S. Appl. No. 14/925,589, Notice of Allowance dated Jan. 12, 2017”, 7 pgs. |
“Chinese Application Serial No. 201480013075.1, Office Action dated Sep. 19, 2016”, w/English Translation, 10 pgs. |
“Chinese Application Serial No. 201480013075.1, Response dated Feb. 3, 2017 to Office Action dated Sep. 19, 2016”, w/English Claims, 30 pgs. |
“European Application Serial No. 14770149.4, Extended European Search Report dated Nov. 25, 2016”, 9 pgs. |
“Korean Application Serial No. 10-2015-7029545, Final Office Action dated Mar. 27, 2017”, w/English Translation, 6 pgs. |
“Korean Application Serial No. 10-2015-7029545, Response dated Dec. 18, 2016 to Office Action dated Oct. 18, 2016”, w/English Claims, 19 pgs. |
Number | Date | Country | |
---|---|---|---|
20160133752 A1 | May 2016 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 13748747 | Jan 2013 | US |
Child | 14610755 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 14610755 | Jan 2015 | US |
Child | 14987147 | US |