Patent Application
20250112121
The present invention generally relates to semiconductor devices and processing methods, and more particularly to semiconductor devices having a signal or power delivery circuit to bypass protective structures in semiconductor device packaging.
Integrated circuit devices are constructed by forming diffusion regions in a substrate and then building up wiring connections from the substrate through to a back end of line (BEOL) structure. Such devices present a diffusion region (e.g., source/drain region) on one side of the device formed in the substrate, and a contact is dropped down to connect with the diffusion region. Metal lines connect to the contacts and are themselves connected by other contacts and metal lines to form a metal structure in accordance with a chip design. This region of a device is referred to as an active prime region. Active prime regions have protective structures, such as, crackstops that reduce the chances of catastrophic cracks propagating through the active prime region and guard rings that help to protect edges of the semiconductor device and prevent electrostatic discharge and/or parasitic electrical losses. These protective structures prevent lateral connections to the active prime region since these protective structures form a hermetic or impenetrable barrier around an outside perimeter of the device.
In accordance with an embodiment of the present invention, a semiconductor device includes a prime active region and a barrier region within the active prime region to define a barrier across a depth of the active prime region. A bypass structure includes a contact connecting to a component within the active prime region and extending outside the active prime region. A metal layer connects to the first contact outside the active prime region, and a through via passes through the depth of the active prime region and connects to a solder bump.
In accordance with another embodiment of the present invention, a semiconductor device includes a prime active region and a barrier region within the active prime region to define a barrier across a depth of the active prime region and including at least a crackstop. An outside bypass structure includes a contact connecting to a component within the active prime region and extending outside the active prime region. A metal layer connects to the first contact outside the active prime region, and a through via passes through the depth of the active prime region outside the barrier region and connects to a solder bump.
In accordance with another embodiment of the present invention, a method for fabricating a semiconductor device includes forming a contact through a first carrier substrate to connect to a component within an active prime region, the contact extending outside the active prime region, the active prime region including barrier region to define a barrier across a depth of the active prime region. A through hole is opened through a depth of the prime active region and the first carrier. The through hole is filled to form a through via passing through the depth of the active prime region and the first carrier. One or more metal layers are formed on the first carrier to connect to the contact and the through via outside the active prime region. A solder bump connection is formed to the through via wherein the contact, the through via and one or more metal layers form a bypass structure to provide access to the active prime region.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The following description will provide details of preferred embodiments with reference to the following figures wherein:
In accordance with embodiments of the present invention, devices and methods are described which include semiconductor devices having electrical paths that extend beyond and through protective barriers disposed about a chip. In one illustrative embodiment, a packaged chip can include barriers and rings that circumscribe a periphery of a chip. These barriers and rings are often impenetrable and do not permit electrical connections through these barriers and rings. It is often the case that solder bumps on a top surface of a chip are the only electrical access point for the chip. These solder bumps make connections to other structures such as leads or other chips.
In useful embodiments, the barriers and rings can include, for example, a crack stop barrier wall that surrounds a periphery of a chip, a guard ring that surrounds the chip to provide grounding or electrical protection, a die seal, seal ring or edge seal structure which can secure and protect the chip in its housing or carrier.
In one embodiment, a chip includes a backside power distribution network with substantially sized wires that can deliver power to a backside redistribution layer (RDL) using at least one through silicon via (TSV) permitting for a bypass of any hermetic or Chip/Package Interactions (CPI) sealing of a crackstop barrier or other structures. An RDL is a layer of wiring metal interconnects that redistribute signal access to different parts of the chip. In one embodiment, the TSV permits a connection that bypasses the crackstop barrier and other structures into an active device region, e.g., the TSV connects to the RDL and/or a secondary TSV (e.g., through a carrier substrate) to create the bypass connection. The power RDL wire can connect two TSVs that go across back end of line (BEOL) dielectric levels and a carrier substrate.
In one embodiment, the bypass connection bypasses epitaxy layers in the chip, and an electrical connection is made to a buried power rail. Different contact structures can be employed to pass through the epitaxial layer of the chip, e.g., source/drain (S/D) contacts, recessed S/D contact, via to buried power rail (VBPR), which forms silicide at a sidewall of the epitaxial material, etc. The bypass passes through the active device layers and connects to a backside of an active prime region to bypass the impenetrable crackstop wall barrier (or other structure) on an underside of the active prime region.
In accordance with embodiments of the present invention, conductive paths are provided that bypass protective features to permit connections from an exterior portion outside an active prime region to regions within the active prime region, including other conductive paths, conductive components, transistors, etc. In addition, connections can be made to other chips or devices. The conductive paths permit connections that would otherwise be impermissible due to the presence of hermetically sealed protective features, such as, crackstops, guard rings, etc. In addition, connections can be internal and provided fully within the active prime region.
In a useful embodiment, a backside electrical or power signal delivery structure for a backside power delivery network (BSPDN) can bypass a continuous impenetrable hermetic crackstop barrier and can be used for power distribution or electrical signal transmission. The delivery structure can be made of rows of outer or inner bumps-to-TSVs dedicated to signals/communication chip to chip, or can have TSVs connected to an RDL wiring level and smaller TSV built in/through a carrier substrate. The TSVs can have different orientations (e.g., up or down). The delivery structure can have one or more TSVs that bridge through the BEOL dielectric layers, the active device layers and a carrier substrate. A RDL level connects the one or more TSVs to a secondary TSV where the secondary TSV bridges through, e.g., a carrier wafer and connects to a buried wiring level, a transistor device with S/D epi or a power distribution network under the transistor device and separated by a dielectric layer.
In one embodiment, the power distribution network includes two TSVs, a backside RDL and a power wire, where a via trench contact connects the S/D of the transistor to the buried power rail (BPR). The BPR is connected to power wires through buried vias, and power wires are connected to the BEOL wires. Recessed contacts can be employed to connect epi and VBPR to BPR. BEOL wires can be connected to a bottom power wire through the bypass.
Embodiments of the present invention can be employed in any type of semiconductor device or chip. For example, the present embodiments can include input/output (IO) circuits, high performance computing (HPC) circuits, clock buffers, processors, memory devices or any other integrated circuit chip or combinations thereof. Adding additional conductive paths to a device in accordance with embodiments of the present invention can be integrated into any fabrication process with minimal or no impact on expense or processing time.
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The semiconductor device or chip 100 includes outside bypasses 108 and inside bypasses 106. Outside bypasses 108 include a through silicon via (TSV) 120 that connects to a component or metal structure within the active prime region 102 and then connects to a metal line or redistribution line (RDL) to connect to another contact or TSV or other conductive structure outside the confines of the active prime region 102. Inside bypasses 106 include a through silicon via (TSV) 120 that connects to a component or metal structure within the active prime region 102 and then connects to a metal line or redistribution line (RDL) to connect to another contact or TSV or other conductive structure inside the confines of the active prime region 102. Both the inside and outside bypasses, 106, 108 exit the active prime region 102. The outside bypasses 108 exit a depth of the active prime region 102 and are positioned outside the barrier region 107, while inside bypasses 106 exit the depth of the active prime region 102 and are positioned with the barrier region 107.
Any number of outside bypasses 108 and inside bypasses 106 can be employed. The outside bypasses 108 and inside bypasses 106 can be employed to connect the present semiconductor device or chip 100 to other chips. In one embodiment, the outside bypasses 108 and inside bypasses 106 are employed to connect signal or power to the semiconductor device or chip 100. In another embodiment, the outside bypasses 108 and inside bypasses 106 can be employed to connect to a single or specific component of the semiconductor device or chip 100.
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Outside bypasses 108 and inside bypasses 106 include at least one TSV 120, which connects a solder bump 110 to a contact 130, 132 or other structure in the active prime region 102 by RDL 122. Contact 130 corresponds with outside bypasses 108 and can include any structure within the chip 100, e.g., S/D regions, another contact, a TSV, etc. Contact 132 corresponds with inside bypasses 106 and can include any structure within the chip 100, e.g., an S/D region, another contact a TSV, etc.
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Outside bypass 108 connects a solder bump 110 to a component 148 located within the active prime region 102. A conductive path for outside bypass 108 includes TSV 120, RDL 122, contact 130. In one embodiment, the TSV 120 passes through a carrier substrate 142, bonding layer 144 and capping layer 146. The contact 130 also passes through the carrier substrate 142, bonding layer 144 and capping layer 146 into BEOL layers 140 to make contact with component 148. Component 148 can include an epitaxial layer, a semiconductor active region, a metal structure, another contact, a TSV, a redistribution network or any other structure that would benefit from a bypass connection. In one embodiment, contact 130 can pass through active device layers, a semiconductor substrate and make contact with metal structures 152 on a top side of the chip 100 or make contact with buried metal structures anywhere within the active prime region 102 at any depth or position.
Inside bypass 106 connects a solder bump 110 to a component 150 located within the active prime region 102 and still within the barrier region 156. A conductive path for inside bypass 106 includes TSV 120, RDL 122, contact 132. In one embodiment, the TSV 120 passes through a carrier substrate 142, bonding layer 144 and capping layer 146. The contact 132 also passes through the carrier substrate 142, bonding layer 144 and capping layer 146 into BEOL layers 140 to make contact with component 150. Component 150 can include an epitaxial layer, a semiconductor active region, a metal structure, another contact, a TSV, a redistribution network or any other structure that would benefit from a bypass connection. In one embodiment, contact 132 can pass through active device layers, a semiconductor substrate and make contact with metal structures 152 on a top side of the chip 100 or make contact with buried metal structures anywhere within the active prime region 102 at any depth or position.
In one embodiment, outside bypasses 108 and inside bypasses 106 can be employed in a power distribution network (PDN), and in particular a backside PDN (BSPDN). In such an embodiment, power can be distributed to one or more TSVs 120 to RDL 122 and a power wire 160. The power wire 160 can connect to a solder bump 110 and/or include a power rail 162 or contact pad for connecting to one or more TSVs 120 or to RDL 122. In one embodiment, the power rail 162 can be buried within the layers of the chip in the active prime region 102. Here, the power distribution network can include a via trench contact that connects a S/D of a transistor to the buried power rail (BPR). The BPR can be connected to power wires through buried vias, and power wires can be connected to BEOL wires. Recessed contacts can be employed to connect epi and VBPR to BPR. BEOL wires can be connected to a bottom power wire through the bypass.
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In one embodiment, a packaged chip 206 includes inside bypasses 106. The inside bypasses 106 have downward facing contacts 133. Downward facing contacts 133 are formed through the carrier substrate 142 away from the active prime region 102. In another embodiment, a packaged chip 208 also includes inside bypasses 106. The inside bypasses 106 have upward facing contacts 132. The upward facing contacts 132 are formed through the carrier substrate 142 toward the active prime region 102.
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In one embodiment, a packaged chip 214 includes outside bypasses 108 and inside bypasses 106. The chip 214 includes downward facing contacts 131. Downward facing contacts 131 are formed through the carrier substrate 142 away from the active prime region 102. Downward facing contacts 131 are formed on multiple metal levels 220 so that connections to TSVs 120 for outside bypasses 108 and inside bypasses 106 can overlap with a same footprint. In another embodiment, a packaged chip 216 also includes outside bypasses 108 and inside bypasses 106. The chip 216 includes upward facing contacts 130. The upward facing contacts 130 are formed through the carrier substrate 142 toward the active prime region 102. Downward facing contacts 131 are formed on multiple metal levels 220 so that connections to TSVs 120 for outside bypasses 108 and inside bypasses 106 can overlap with a same footprint.
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Semiconductor components, e.g., active regions, such as source/drain regions (S/D regions), gate structures, capacitor plates, memory elements, etc. are formed. Other components can include other electronic and electrical components. Metal structures within dielectric protection layers are also formed.
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The semiconductor substrate 402 is processed in accordance with a process of record and in accordance with a device type being manufactured. For example, a nanosheet or nanosheets 422 can be applied to the semiconductor substrate 402 and/or a power distribution network 418 with a buried power rail 420 can be fabricated, as needed. In addition, barrier protection features, such as a crackstop 414 and/or a guard ring 416 are formed.
Semiconductor components, e.g., active regions, such as source/drain regions (S/D regions), gate structures, capacitor plates, memory elements, etc. are formed. Other components can include other electronic and electrical components. Metal structures within dielectric protection layers are also formed.
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Exemplary applications/uses to which the present invention can be applied include, but are not limited to semiconductor devices. Semiconductor devices can include processors, memory devices, application specific integrated circuits (ASICs), logic circuits or devices, combinations of these and any other circuit device. In such devices, one or more semiconductor devices can be included in a central processing unit, a graphics processing unit, and/or a separate processor- or computing element-based controller (e.g., logic gates, etc.). The semiconductor devices can include one or more on-board memories (e.g., caches, dedicated memory arrays, read only memory, etc.). In some embodiments, the semiconductor devices can include one or more memories that can be on or off board or that can be dedicated for use by a hardware processor subsystem (e.g., ROM, RAM, basic input/output system (BIOS), etc.).
In some embodiments, the semiconductor devices can include and execute one or more software elements. The one or more software elements can include an operating system and/or one or more applications and/or specific code to achieve a specified result. In still other embodiments, the semiconductor devices can include dedicated, specialized circuitry that perform one or more electronic processing functions to achieve a specified result. Such circuitry can include one or more field programmable gate arrays (FPGAs), and/or programmable applications programmable logic arrays (PLAs).
It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe1-x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.
Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper.” “top.” “bottom” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.
It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
Having described preferred embodiments of devices and methods (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
