Patent Application
20100059729
This invention relates to electronic memory circuits.
As semiconductor memories approach limits beyond which they will no longer be able to produce the density/cost/performance improvements so famously set forth in Moore's law, a host of memory technologies are being investigated as potential replacements for conventional silicon complementary metal oxide semiconductor (CMOS) integrated circuit memories. Among the technologies being investigated are phase change memory technologies. Phase-change memory arrays are based upon memory elements that switch among two material phases, or gradations thereof, to exhibit corresponding distinct electrical characteristics. Alloys of elements of group VI of the periodic table, such as Te, S or Se, referred to as chalcogenides or chalcogenic materials, can be used advantageously in phase change memory cells. In the chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa. Further, the resistivity of the chalcogenide materials generally depend on the temperature with the amorphous state generally being more temperature dependent that the crystalline state.
A chalcogenide memory device may utilize the wide range of resistance values available for the material as the basis of memory operation. Each resistance value corresponds to a distinct structural state of the chalcogenide material and one or more of the states can be selected and used to define operation memory states. Chalcogenide materials exhibit a crystalline state, or phase, as well as an amorphous state, or phase. Different structural states of a chalcogenide material differ with respect to the relative proportions of crystalline and amorphous phase in a given volume or region of chalcogenide material. The range of resistance values is generally bounded by a set state and a reset state of the chalcogenide material. By convention, the set state is a low resistance structural state whose electrical properties are primarily controlled by the crystalline portion of the chalcogenide material and the reset state is a high resistance structural state whose electrical properties are primarily controlled by the amorphous portion of the chalcogenide material.
Phase change may be induced by increasing the temperature locally. For some alloys, below 150° C., both of the phases are stable. Above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the chalcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then cool it off rapidly, i.e. quench. From the electrical standpoint, it is possible to reach the crystallization and melting temperatures by causing a current to flow through a crystalline resistive element that heats the chalcogenic material by the Joule effect.
Each memory state of a chalcogenide memory material corresponds to a distinct range of resistance values and each memory resistance value range signifies unique informational content. Operationally, the chalcogenide material can be programmed into a particular memory state by providing an electric current pulse of an appropriate amplitude and duration to transform the chalcogenide material into the structural state having the desired resistance. By controlling the amount of energy provided to the chalcogenide material, it is possible to control the relative proportions of crystalline and amorphous phase regions within a volume of the material and to thereby control the structural (and corresponding memory) state of the chalcogenide material to store information.
Each memory state can be programmed by providing the current pulse characteristics of the state and each state can be identified, or “read”, in a non-destructive fashion by measuring the resistance. Programming among the different states is fully reversible and the memory devices can be written and read over a virtually unlimited number of cycles to provide robust and reliable operation. The variable resistance memory functionality of chalcogenide materials is currently being exploited in the OUM (Ovonic Universal (or Unified) Memory) devices that are beginning to appear on the market. Basic principles and operation of OUM type devices are presented, for example, in U.S. Pat. Nos. 6,859,390; 6,774,387; 6,687,153; and 6,314,014; the disclosures of which are incorporated by reference herein, as well as in several journal articles including, “Low Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials,” published in EE transactions on Electron Devices, vol. 51, p. 714-719 (2004) by Pirovana et al.; and “Morphing Memory,” published in IEEE Spectrum, vol. 167, p. 363-364 (2005) by Weiss.
The behavior (including switching, memory, and accumulation) and chemical compositions of chalcogenide materials have been described, for example, in the following U.S. Pat. Nos. 6,671,710; 6,714,954; 6,087,674; 5,166,758; 5,296,716; 5,536,947; 5,596,522; 5,825,046; 5,687,112; 5,912,839; and 3,530,441, the disclosures of which are hereby incorporated by reference. These references present proposed mechanisms that govern the behavior of chalcogenide materials. The references also describe the structural transformations from the crystalline state to the amorphous state (and vice versa) via a series of partially crystalline states in which the relative proportions of crystalline and amorphous regions vary during the operation of electrical and optical programming of chalcogenide materials.
A wide range of chalcogenide compositions has been investigated in an effort to optimize the performance characteristics of chalcogenic devices. Chalcogenide materials generally include a chalcogen element and one or more chemical or structural modifying elements. The chalcogen element (e.g. Te, Se, S) is selected from column VI of the periodic table and the modifying elements may be selected, for example, from column III (e.g. Ga, Al, In), column IV (e.g. Si, Ge, Sn), or column V (e.g. P, As, Sb) of the periodic table. The role of modifying elements includes providing points of branching or cross-linking between chains comprising the chalcogen element. Column IV modifiers can function as tetracoordinate modifiers that include two coordinate positions within a chalcogenide chain and two coordinate positions that permit branching or crosslinking away from the chalcogenide chain. Column III and V modifiers can function as tricoordinate modifiers that include two coordinate positions within a chalcogenide chain and one coordinate position that permits branching or crosslinking away from the chalcogenide chain. Embodiments in accordance with the principles of the present invention may include binary, ternary, quaternary, and higher order chalcogenide alloys. Examples of chalcogenide materials are described in U.S. Pat. Nos. 5,166,758, 5,296,716, 5,414,271, 5,359,205, 5,341,328, 5,536,947, 5,534,712, 5,687,112, and 5,825,046 the disclosures of which are all incorporated by reference herein. Chalcogenide materials may be deposited with a reactive sputtering process with gasses such as N2 or O2: forming a chalcogenide nitride, or oxide, for example and chalcogenide may be modified by an ion implantation or other process.
Early work in chalcogenide devices demonstrated electrical switching behavior in which switching from an “off” resistive state to an “on” conductive state was induced upon application of a voltage at or above the threshold voltage of the active chalcogenide material. This effect is the basis of the Ovonic Threshold Switch (OTS) and remains an important practical feature of chalcogenide materials. The OTS provides highly reproducible switching at ultrafast switching speeds. Basic principles and operational features of the OTS are presented, for example, in U.S. Pat. Nos. 3,271,591; 5,543,737; 5,694,146; and 5,757,446; the disclosures of which are hereby incorporated by reference, as well as in several journal articles including “Reversible Electrical Switching Phenomena in Disordered Structures,” Physical Review Letters, vol. 21, p. 1450-1453 (1969) by S. R. Ovshinsky; “Amorphous Semiconductors for Switching, Memory, and Imaging Applications,” IEEE Transactions on Electron Devices, vol. ED-20, p. 91-105 (1973) by S. R. Ovshinsky and H. Fritzsche; the disclosures of which are hereby incorporated by reference. Three-terminal OTS devices are disclosed, for example, in U.S. Pat. Nos. 6,969,867 and 6,967,344; the disclosures of which are hereby incorporated by reference.
Although highly efficient and cost effective, process methods and device structures that improve the performance of phase change memories would be highly desirable.
A programmable resistance memory cell in accordance with the principles of the present invention includes a volume of programmable resistance material formed between and coupled to two electrodes. The volume of programmable resistance material includes a region of enhanced programmability that is positioned to maximize the effect of a programming current. In an illustrative embodiment, the region of enhanced programmability is positioned at a distance from regions of high thermal conductivity, such as areas in close proximity to electrodes. The programmable resistance material may be, for example, phase change material, such as chalcogenide material. Such enhanced programmability may be implemented as preferential resetting, for example.
In a phase change material embodiment, the phase change material may include a region of enhanced phase change that is positioned at a distance from either electrode. The region of enhanced phase change may be created by modifying the “unprogrammed resistance” profile of the volume of phase change material. A region of enhanced phase change may also be created by modifying the melting point of phase change material within the volume. In particular, a region of enhanced phase change may be created by reducing the melting point of phase change material within the volume. Combinations of lowered melting point and increased resistivity are also contemplated within the scope of the invention. By “unprogrammed resistance” we mean the resistance of the material in its minimal-resistance state. This minimal resistance, “unprogrammed resistance,” state may also be referred to herein as the SET state. In an illustrative embodiment, the phase change material includes a region of material that exhibits higher resistance than the surrounding phase change material, even in the SET state, and such an enhanced-resistance region is positioned at a distance from either electrode: midway between electrodes in an illustrative embodiment. The enhanced-resistance region may bisect the current path between the cell's electrodes and, in an illustrative embodiment, may form a disk of enhanced resistance material across a pore of phase change material. Such a disk of enhanced resistance material may be formed by implanting the phase change material to increase the phase change material's resistance. For example, a memory cell including a modified SET resistance profile may be formed by implanting Si+, N+, N2+, O+, or O2+, ions in phase change memory material. Alternatively, a disk of enhanced resistance material may be formed by successively depositing a layer of “base” phase change material, a layer of enhanced-resistance phase change material, then another layer of “base” phase change material in a pore, for example.
However a region of enhanced-resistance is produced, such a region dissipates more energy for a given current flow between a cell's electrodes than surrounding areas of lower resistance. By dissipating more energy, the enhanced-resistance material attains a higher temperature and, therefore, changes phase at lower current levels than surrounding phase change material. In that sense, the enhanced-resistance regions are enhanced programmability regions. Positioning such regions of enhanced programmability at a remove from thermally dissipative elements, such as electrodes, further enhances the programmability of the material, because less thermal energy will be channeled away from the region undergoing a phase change. If, in addition, such a region of enhanced programmability is positioned to “seal off” all current paths between the electrodes, phase change can be limited to the enhanced-programmability region. Use of a confined cell, such as a filled-pore cell, facilitates such a process.
In an illustrative embodiment, the phase change material is confined, in a pore structure situated between two electrodes for example, and the minimal resistance profile of the device exhibits a continuously-variable distribution having a peak in a location at a distance from both electrodes. An electrical resistance distribution in accordance with the principles of the present invention configures a phase change memory cell to concentrate power in a region where it is most effective at changing the phase of a critical portion of device's phase change memory material, thereby reducing the device's power consumption.
A memory that employs a modified SET resistance profile in accordance with the principles of the present invention may be particularly suitable for operation in a variety of electronic devices, including cellular telephones, radio frequency identification devices (RFID), computers (portable and otherwise), solid state drives (SSDs), location devices (e.g., global positioning system (GPS) devices, particularly those that store and update location-specific information), and handheld electronic devices, including personal digital assistants (PDAs), and entertainment devices, such as MP3 players, for example.
Although this invention will be described in terms of certain preferred embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the benefits and features set forth herein, are also within the scope of this invention. Various structural, logical, process step, chemical, and electrical changes may be made without departing from the spirit or scope of the invention. Polarities and types of devices and supplies may be substituted in a manner that would be apparent to one of reasonable skill in the art. Accordingly, the scope of the invention is defined only by reference to the appended claims.
At the leftmost extreme of the graph the phase change material exhibits a relatively high resistance of 1 MΩ. Such a resistance is characteristic of a RESET state. A current pulse of amplitude ISET crystallizes a sufficient amount of phase change material to provide a relatively low resistance path from one electrode to another. Current pulses of greater amplitude may be applied to the phase change device in an attempt to increase the resistance of the device. In the illustrative embodiment of
With a current pulse of amplitude IMELT, the energy content of the current pulse is sufficient to melt at least a portion of phase change material. With rapid quenching, the melted phase change material is transformed to an amorphous state. That is, a relatively short duration programming pulse (e.g., on the order of tens of nanoseconds) allows the melted material to cool before significant crystallization of the melted material may occur. As a result, a portion of phase change material in the current path between the electrodes is transformed by the current pulse IMELT to an amorphous state that is characterized by a relatively high electrical resistance. The value of increased resistance selected to define IMELT may be somewhat arbitrary. For the sake of this discussion, a resistance increase from the low, SET, resistance, to 0.5% of the high, RESET, resistance corresponds to the melt resistance, RMELT, and melt current amplitude, IMELT. At the other extreme of amorphization, the saturation resistance is the maximum attainable resistance of the phase change material and the saturation current, ISAT, is the corresponding current pulse amplitude.
The assumption that the volume of phase change material 202 is initially in a crystalline phase, corresponding to a SET state, is built in to
As indicated in
The result is a tendency for phase change material to melt, as indicated in
The resistivity profile of
One measure of the extent to which phase change material 202 is melted in order to amorphize sufficient material to RESET the cell of
However, in this illustrative embodiment, the volume of material within the programmed volume is substantially less than that required in the conventional embodiment of
In accordance with the principles of the present invention, the location of the peak resistivity is chosen to coincide with the location of the greatest vertical thermal isolation. In this way, a phase change memory cell in accordance with the principles of the present invention increases power dissipation in a region where the power will be most effectively utilized to melt and amorphize the phase change material, as illustrated in the power dissipation graphical representation of
Similarly, in a modified-melting temperature embodiment, the volume of material within the programmed volume is substantially less than that required in the conventional embodiment of
In accordance with the principles of the present invention, the location of the minimal melting temperature is chosen to coincide with the location of the greatest vertical thermal isolation. In this way, a phase change memory cell in accordance with the principles of the present invention increases the propensity for melting in a region where the power will be most effectively utilized to melt and amorphize the phase change material. Because the melting temperature of the phase-change material steadily decreases with distance from an electrode contact, the volume of phase change material that reaches the modified melting temperature Tm′ steadily increases with distance from either electrode contact, as indicated by the temperature profile of
In this illustrative embodiment, the volume of amorphized material in the programmed volume required to achieve the saturation resistance is substantially less than that required in the conventional embodiment of
As with the embodiment described in the discussion related to
Because the resistivity profile of the phase-change material abruptly increases at a distance from either electrode contact, power generation (in the form of Joule heating, i2R) also abruptly increases at a distance from either electrode contact. This is reflected in the step-increase of the curve of
A programmable resistance memory cell having an Gaussian SET resistivity profile in accordance with the principles of the present invention (such as that of
The ion implantation profile of
Similarly, a programmable resistance memory cell in accordance with the principles of the present invention with a “negative Guassian” profile may be produced, for example, by implantation in a phase change material such as GST225. In accordance with the principles of the present invention, the incident energy of the ions may be chosen so that the projected ion range is half the height of the phase change alloy cylinder. Additionally, the implantation dose may be chosen so that at the peak of the implant distribution, the concentration of the implanted ions is between about 5% and 10%, yielding a decrease in melting temperature of 50% to 75% in the peak implant, minimal melting temperature, region.
The conceptual block diagram of
Accesses carried out by the row 708 and column 706 drivers include reading from the memory cells of the matrix 704 and writing to the memory cells of the matrix 704. Peripheral circuitry 712 includes decoding circuitry 714 which accepts address signals and decodes the address signals to determine which of the row 708 and column 706 drivers to activate and, thereby, which of the memory cells within the array 704 to access.
Peripheral circuitry 712 may include control circuitry 716 that accepts READ, WRITE, and CLOCK signals and develops control signals for the memory 700. The control signals developed for the memory 700 may include data direction control (e.g., “read from” or “write to” the storage matrix tile 702) and clock signals, for example. The input/output circuitry 718 includes circuitry configured to accept data for writing to and to drive data read from the storage matrix tile 702.
The programmable resistance devices described in the discussion related to the previous figures may be employed to particular advantage in a wide variety of systems. The schematic diagram of
An electronic system 800 in accordance with the principles of the present invention may be a microprocessor that operates as a CPU 805, in combination with embedded chalcogenide-based electronic nonvolatile memory that operates as RAM 810 and/or ROM 815, or as a portion thereof. In this illustrative example, the microprocessor/chalcogenide-nonvolatile memory combination may be standalone, or may operate with other components, such as those of
In implementations within the scope of the invention, a bus 830 interconnects the components of the system 800. A bus controller 825 is provided for controlling bus 830. An interrupt controller 835 may or may not be used for receiving and processing various interrupt signals from the system components. Such components as the bus 830, bus controller 825, and interrupt controller 835 may be employed in a large-scale implementation of a system in accordance with the principles of the present invention, such as that of a computer, a router, a portable computer, or a data storage system, for example.
Mass storage may be provided by diskette 842, CD ROM 847, or hard drive 852. Data and software may be exchanged with the system 800 via removable media such as diskette 842 and CD ROM 847. Diskette 842 is insertable into diskette drive 841 which is, in turn, connected to bus 830 by a controller 840. Similarly, CD ROM 847 is insertable into CD ROM drive 846 which is, in turn, connected to bus 830 by controller 845. Hard disc 852 is part of a fixed disc drive 851 which is connected to bus 830 by controller 850. Although conventional terms for storage devices (e.g., diskette) are being employed in this description of a system in accordance with the principles of the present invention, any or all of the storage devices may be implemented using a memory which may include chalcogenide-based nonvolatile memory in accordance with the principles of the present invention. Removable storage may be provided by a nonvolatile storage component, such as a thumb drive, that employs a chalcogenide-based nonvolatile memory in accordance with the principles of the present invention as the storage medium. Storage systems that employ chalcogenide-based nonvolatile memory as “plug and play” substitutes for conventional removable memory, such as disks or CD ROMs or thumb drives, for example, may emulate existing controllers to provide a transparent interface for controllers such as controllers 840, 845, and 850, for example.
User input to the system 800 may be provided by any of a number of devices. For example, a keyboard 856 and mouse 857 are connected to bus 830 by controller 855. An audio transducer 896, which may act as both a microphone and/or a speaker, is connected to bus 830 by audio controller 897, as illustrated. Other input devices, such as a pen and/or tabloid may be connected to bus 830 and an appropriate controller and software, as required, for use as input devices. DMA controller 860 is provided for performing direct memory access to RAM 810, which, as previously described, may be implemented in whole or part using chalcogenide-based nonvolatile memory devices in accordance with the principles of the present invention. A visual display is generated by video controller 865 which controls display 870. The display 870 may be of any size or technology appropriate for a given application.
In a cellular telephone or portable entertainment system embodiment, for example, the display 870 may include one or more relatively small (e.g. on the order of a few inches per side) LCD displays. In a large-scale data storage system, the display may be implemented as large-scale multi-screen, liquid crystal displays (LCDs), or organic light emitting diodes (OLEDs), including quantum dot OLEDs, for example.
The system 800 may also include a communications adaptor 890 which allows the system to be interconnected to a local area network (LAN) or a wide area network (WAN), schematically illustrated by bus 891 and network 895. An input interface 899 operates in conjunction with an input device 893 to permit a user to send information, whether command and control, data, or other types of information, to the system 800. The input device and interface may be any of a number of common interface devices, such as a joystick, a touch-pad, a touch-screen, a speech-recognition device, or other known input device. In some embodiments of a system in accordance with the principles of the present invention, the adapter 890 may operate with transceiver 873 and antenna 875 to provide wireless communications, for example, in cellular telephone, RFID, and wifi computer implementations.
Operation of system 800 is generally controlled and coordinated by operating system software. The operating system controls allocation of system resources and performs tasks such as processing scheduling, memory management, networking, and I/O services, among other things. In particular, an operating system resident in system memory and running on CPU 805 coordinates the operation of the other elements of the system 800.
In illustrative handheld electronic device embodiments of a system 800 in accordance with the principles of the present invention, such as a cellular telephone, a personal digital assistance, a digital organizer, a laptop computer, a handheld information device, a handheld entertainment device such as a device that plays music and/or video, small-scale input devices, such as keypads, function keys and soft keys, such as are known in the art, may be substituted for the controller 855, keyboard 856 and mouse 857, for example. Embodiments with a transmitter, recording capability, etc., may also include a microphone input (not shown).
In an illustrative RFID transponder implementation of a system 800 in accordance with the principles of the present invention, the antenna 875 may be configured to intercept an interrogation signal from a base station at a frequency F1. The intercepted interrogation signal would then be conducted to a tuning circuit (not shown) that accepts signal F1 and rejects all others. The signal then passes to the transceiver 873 where the modulations of the carrier F1 comprising the interrogation signal are detected, amplified and shaped in known fashion. The detected interrogation signal then passes to a decoder and logic circuit which may be implemented as discrete logic in a low power application, for example, or as a microprocessor/memory combination as previously described. The interrogation signal modulations may define a code to either read data out from or write data into a chalcogenide-based nonvolatile memory in accordance with the principles of the present invention. In this illustrative embodiment, data read out from the memory is transferred to the transceiver 873 as an “answerback” signal on the antenna 875 at a second carrier frequency F2. In passive RFID systems, power is derived from the interrogating signal and memory such as provided by a chalcogenide-based nonvolatile memory in accordance with the principles of the present invention is particularly well suited to such use.
