Claims
- 1. An apparatus comprising:
- a computer chassis;
- a chip package, said chip package comprising at least one power pin and at least one signal pin; and,
- a bracket coupled to said chassis, said bracket further comprising a first socket receiving said power pin and a second socket receiving said signal pin, wherein said first socket electrically couples said power pin to said bracket and said second socket electrically isolates said signal pin from said bracket.
- 2. The apparatus of claim 1 further comprising a current source electrically coupled to said bracket.
- 3. An apparatus comprising:
- a computer chassis;
- a chip package, said chip package comprising at least one solder power connection and at least one solder signal connection; and,
- a bracket coupled to said chassis, said bracket further comprising a first landing pad electrically coupled to said power connection and a second landing pad electrically coupled to said signal connection, wherein said first landing pad electrically couples said power connection to said bracket and said second landing pad electrically isolates said signal connection from said bracket.
- 4. The apparatus of claim 3 further comprising a current source electrically coupled to said bracket.
- 5. The apparatus of claim 3 wherein said bracket further comprises a signal pin mechanically and electrically coupled to said second landing pad for coupling said chip package solder signal connection to an interconnecting circuit.
RELATED APPLICATIONS
The present application is related to the following patent and co-pending applications: U.S. Patent entitled "Daisy Chained Clock Distribution Scheme," by Borkar, et al., U.S. Pat. No. 5,546,023, issued Aug. 13, 1996 and filed Jun. 26, 1995; U.S. Patent Application entitled "Point-To-Point Phase-Tolerant Communication," by Self et al., application Ser. No. 08/296,019, filed Aug. 25, 1994; U.S. Patent Application entitled "Microprocessor Point-To-Point Communication," by Self et al., application Ser. No. 08/295,556, filed Aug. 25, 1994; U.S. Patent Application entitled "Multilayer Solder Interconnection Structure," by Mashimoto, application Ser. No. 08/625,797, filed Mar. 29, 1996; U.S. Application entitled "Power-Pod Power Delivery System," by McCutchan et al., application Ser. No. 08/672,864, filed on Jun. 28, 1996; U.S. Patent Application entitled "Use of Flexible Interconnects and Point-to-Point Communications Protocol to Connect Subsystems with Dissimilar Thermal Properties," by Borkar et al., application Ser. No. 08/772,260, filed Dec. 31, 1996; Patent Application entitled "Method and Apparatus for Mounting a Very Large Scale Integration (VLSI) Chip Package to a Computer Chassis for Current Supply," by Borkar et al., application Ser. No. 08/777,601, filed Dec. 31, 1996; U.S. Patent Application entitled "Method and Apparatus for Retrofit Mounting a VLSI Chip to a Computer Chassis for Current Supply," by Borkar et al. application Ser. No. 08/775,784, filed Dec. 31, 1996; and U.S. Patent Application entitled "Method and Apparatus for Mounting a Power Supply to a Computer Chassis for Cooling," by Borkar et et al., application Ser. No. 08/775,782, filed Dec. 31, 1996.
US Referenced Citations (54)
Foreign Referenced Citations (1)
Number |
Date |
Country |
412 115 |
Nov 1966 |
CHX |