Embodiments disclosed herein pertain to arrays of recessed access gate lines, to arrays of conductive lines, to arrays of recessed access gate lines and conductive lines, to memory circuitry, to methods of forming an array of recessed access gate lines, to methods of forming an array of conductive lines, and to methods of forming an array of recessed access gate lines and an array of conductive lines.
Integrated circuitry may be fabricated over and within semiconductor substrates. Individual device components of the circuitry may be separated or electrically isolated from other device components by dielectric or other isolation formed over and/or within the semiconductor substrate. One form of isolation is commonly referred to as trench isolation, wherein trenches are etched into semiconductor substrate material and subsequently filled with one or more dielectric materials. The trenches and isolation material therein may surround islands of semiconductor substrate material, commonly referred to as active area regions, where some of the individual circuit components are fabricated.
Integrated circuitry can be fabricated to have many functions, and may include many different electronic devices such as capacitors, transistors, resistors, diodes, etc. One type of electronic device is a recessed access device, which is a field effect transistor that has its gate construction received wholly or partially within a trench formed in semiconductor material. A gate dielectric separates the conductive gate from the semiconductor material. A pair of source/drain regions is formed within semiconductor material elevationally higher than the conductive gate materials. Application of suitable voltage to the conductive gate material within the trench enables current to flow through the semiconductor material between the source/drain regions along the trench sidewalls and around the base of the trench. The gates of recessed access devices in some circuit constructions transversally cross some active area regions and extend between other immediately end-to-end adjacent active area regions. Due to proximity of the gate material of a recessed access gate line passing between and close to the ends of active area regions, adverse circuit operation may occur. Such problems include parasitic coupling and adverse sub-threshold current leakage. Problems such as these may be mitigated by increasing the end-to-end spacing between active area regions and/or reducing the width of the recessed access gate lines. However, such techniques may have their own adverse effects.
Another challenge in integrated circuitry fabrication is interconnection of conductive lines to lower elevation circuit components. As circuit components become smaller and closer together, it becomes increasingly difficult to control critical dimension, mask alignment, and provide acceptable margins of error when forming contact openings to the lower elevation circuit components.
Embodiments of the invention include arrays of recessed access gate lines, arrays of conductive lines, memory circuitry, methods of forming arrays of recessed access gate lines, and methods of forming arrays of conductive lines. One embodiment of an array of recessed access gate lines is described initially with reference to
Substrate 10 includes active area regions 14 comprising active area material 12 having dielectric trench isolation material 16 there-between. Any of the materials and/or structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Further unless otherwise stated, each material may be formed using any suitable or yet-to-be-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples. Example trench isolation material is doped silicon dioxide, undoped silicon dioxide, and/or silicon nitride. Example active area material is semiconductor material, for example comprising doped or undoped monocrystalline silicon and/or polycrystalline silicon. Individual active area regions 14 may be considered as comprising opposing ends 18. Active area material 12 within active area regions 14 may be considered as having an outer surface 20. Outer surface 20 may be planar, for example as shown, and may comprise an elevationally outermost surface of active area material 12 within active area regions 14.
Trench isolation material 16 comprises dielectric projections 24 which extend into opposing ends 18 of individual active area regions 14 under elevationally outermost surface 20, with active area material 12 being elevationally over dielectric projections 24. In some embodiments, dielectric projections 24 are referred to as dielectric end projections to distinguish from dielectric lateral projections described below. An example projecting distance longitudinally into the ends of the active area regions is from about 5 to 10 nanometers from the respective furthest longitudinal extents of active area material 12 at the respective ends 18. An example depth from outermost surface 20 where dielectric projections 24 start projecting is from about 10 to 20 nanometers.
Recessed access gate lines 26 individually extend transversally across active area regions 14. Recessed access gate lines 26 also individually extend between ends 18 of immediately end-to-end adjacent active area regions 14 within dielectric trench isolation material 16.
In one embodiment and as shown (
An array of recessed access gate lines in accordance with the invention may be used in any existing or yet-to-be-developed integrated circuitry. As an example, an array of recessed access gate lines may be used in memory circuitry having a plurality of memory cells, and for example where the memory cells are DRAM cells individually comprising a capacitor. Example such circuitry is diagrammatically shown in
Another embodiment in accordance with the invention is next described with reference to
Active area regions 14 may be considered as having a mid-portion 45 having a mid-portion surface 44 which is elevationally inward relative to elevationally outermost surface 20 proximate ends 18. Conductive lines 46 individually extend transversally across and elevationally over mid-portion 45 of individual active area regions 14. Conductive material is directly against mid-portion surface 44 of active area material 12 and conductively couples with the conductive line 46 transversally crossing thereover. In this document, a material or structure is “directly against” another when there is at least some physical touching contact of the stated materials or structures relative one another. In contrast, “over”, “on”, and “against” not preceded by “directly”, encompass “directly against” as well as construction where intervening material(s) or structure(s) result(s) in no physical touching contact of the stated materials or structures relative one another.
In one embodiment, dielectric trench isolation material 16 between sides 40 of immediately side-to-side adjacent active area regions 14 comprises opposing sidewalls 50 that taper laterally inward (i.e., relative dielectric trench isolation material 16) elevationally inward of furthest extents of dielectric projections 42 into sides 40 of those immediately side-to-side adjacent active area regions 14. In one embodiment, dielectric trench isolation material 16 between sides 40 comprises opposing sidewalls 52 that are substantially vertical elevationally outward of furthest lateral extents of dielectric projections 42 into sides 40. An example projecting distance laterally into the active area regions is from about 5 to 10 nanometers from the furthest lateral extents of the active area material of the respective sides 40. An example depth from outermost surface 20 where dielectric projections 42 start projecting is from about 10 to 20 nanometers.
In one embodiment, individual active area regions 14 are longitudinally elongated along a straight longitudinal axis, for example a respective axis 55 as shown in
Any other attribute as described above with respect to the
An array of conductive lines in accordance with the invention may be used in any existing or yet-to-be-developed integrated circuitry. As examples, the conductive lines may be interconnect lines, may be sense lines, and/or may be gate lines. As a specific example, an array of recessed access gate lines may be used in memory circuitry having a plurality of memory cells, and for example where the memory cells are DRAM cells individually comprising a capacitor. Example such circuitry 10a is diagrammatically shown in
Embodiments of the invention include combining at least some of the variously described and shown aspects in an array of recessed access gate lines and conductive lines, for example as shown with respect to a substrate fragment 10b in
In one embodiment, the mid-portion surface is elevationally inward relative to the elevationally outermost surface of active area material in the individual active area regions proximate the opposing ends. In one embodiment, the individual active area regions are longitudinally elongated along a straight longitudinal axis. The mid-portion surface is laterally narrower perpendicular to the longitudinal axis than the elevationally outermost surfaces proximate the opposing ends independent of whether the mid-portion surface is elevationally inward relative to the elevationally outermost surface of the active area material proximate the opposing ends.
The embodiment of
Referring to
Referring to
Referring to
Any suitable technique(s) may be used in etching the isolation trenches deeper to the second depth. One such example is described with reference to
Referring to
Referring to
Referring to
Referring to
Masking material 70 may be formed and substrate material 12 may be etched to produce the example desired profiles using any existing or yet-to-be-developed techniques. By way of examples only, where active area material 12 comprises elemental silicon, an example technique for producing the isolation trench outline as shown in
Producing the structures of
Embodiments of the invention also include a method of forming an array of conductive lines, for example the conductive lines shown in the example embodiment of
Referring to
Referring to
Referring to
Referring to
Processing could continue, for example, in fabricating the structure of
In one embodiment and prior to etching the contact openings, recessed access gate lines may be formed which individually extend transversally across active area regions 14 and also extend between ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. For example referring to
Method embodiments of the invention also encompass a combination of the above generally described methods whereby, for example, dielectric end projections 24 and dielectric lateral projections 42 are both formed (e.g., at the same time or separately).
In some embodiments, a method of forming an array of recessed access gate lines comprises etching isolation trenches into semiconductor material to a first depth to define active area regions. The isolation trenches are etched deeper into the semiconductor material to a second depth. The etching to the second depth projects the isolation trenches longitudinally into opposing ends of individual active area regions below the first depth. Dielectric trench isolation material is formed in the extended isolation trenches including projecting portions thereof to form dielectric projections extending into the opposing ends of the individual active area regions under an elevationally outermost surface of the semiconductor material of the active area regions. The semiconductor material is elevationally over the dielectric projections. Recessed access gate lines are formed which individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material.
In some embodiments, a method of forming an array of conductive lines comprises etching isolation trenches into semiconductor material to a first depth to define active area regions. The isolation trenches are etched deeper into the semiconductor material to a second depth. The etching to the second depth projects the isolation trenches laterally into opposing sides of individual active area regions below the first depth. Dielectric trench isolation material is formed in the extended isolation trenches including projecting portions thereof to form dielectric projections extending laterally into the opposing sides of the individual active area regions under an elevationally outermost surface of the semiconductor material of the active area regions. The semiconductor material is elevationally over the dielectric projections. A contact opening is etched into the semiconductor material at a mid-portion of the individual active area regions to form a mid-portion semiconductor material surface that is elevationally inward relative to the elevationally outermost surface of the semiconductor material in the individual active area regions. Conductive lines are formed that individually extend transversally across and elevationally over the mid-portions of the active area regions. Conductive material is directly against the mid-portion surface of the individual active area regions and is conductively coupled to the conductive line transversally crossing thereover.
In some embodiments, a method of forming an array of recessed access gate lines and an array of conductive lines comprises etching isolation trenches into semiconductor material to a first depth to define active area regions. The isolation trenches are etched deeper into the semiconductor material to a second depth. The etching to the second depth projects the isolation trenches longitudinally into opposing ends of individual active area regions below the first depth and projects the isolation trenches laterally into opposing sides of the individual active area regions below the first depth. Dielectric trench isolation material is formed in the extended isolation trenches including projecting portions thereof to form dielectric end projections extending into the opposing ends of the individual active area regions under an elevationally outermost surface of the semiconductor material of the active area regions and to form dielectric lateral projections extending laterally into the opposing sides of the individual active area regions under the elevationally outermost surface of the semiconductor material of the active area regions. The semiconductor material is elevationally over the end and lateral dielectric projections. Recessed access gate lines are formed which individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. After forming the recessed access gate lines, a contact opening is etched into the semiconductor material at a mid-portion of the individual active area regions to form a mid-portion semiconductor material surface that is elevationally inward relative to the elevationally outermost surface of the semiconductor material in the individual active area regions. Conductive lines are formed that individually extend transversally across and elevationally over the mid-portions of the active area regions. Conductive material is directly against the mid-portion surface of the individual active area regions and is conductively coupled to the conductive line transversally crossing thereover.
In some embodiments, an array of recessed access gate lines comprises active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material.
In some embodiments, an array of conductive lines comprises active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending laterally into opposing sides proximate opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions proximate the opposing ends. The active area material is elevationally over the dielectric projections proximate the opposing ends. Conductive lines individually extend transversally across and elevationally over a mid-portion of the individual active area regions. Conductive material is directly against a mid-portion surface of the active area material of the individual active area regions and is conductively coupled to the conductive line transversally crossing thereover. The mid-portion surface is elevationally inward relative to the elevationally outermost surface of the active area material in the individual active area regions proximate the opposing ends.
In some embodiments, an array of conductive lines comprises active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending laterally into opposing sides proximate opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions proximate the opposing ends. The active area material is elevationally over the dielectric projections proximate the opposing ends. Conductive lines individually extend transversally across and elevationally over a mid-portion of the individual active area regions. Conductive material is directly against a mid-portion surface of the active area material of the individual active area regions and is conductively coupled to the conductive line transversally crossing thereover. The individual active area regions are longitudinally elongated along a straight longitudinal axis. The mid-portion surface is laterally narrower perpendicular to the longitudinal axis than the elevationally outermost surfaces proximate the opposing ends.
In some embodiments, an array of recessed access gate lines and conductive lines comprises active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric end projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric end projections. The trench isolation material comprises dielectric lateral projections extending laterally into opposing sides proximate the opposing ends under an elevationally outermost surface of the active area material proximate the opposing ends. The active area material is elevationally over the dielectric end projections proximate the opposing ends. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Conductive lines individually extend transversally across and elevationally over a mid-portion of the individual active area regions. Conductive material is directly against a mid-portion surface of the active area material of the individual active area regions and is conductively coupled to the conductive line transversally crossing thereover. The mid-portion surface is elevationally inward relative to the elevationally outermost surface of the active area material in the individual active area regions proximate the opposing ends.
In some embodiments, an array of recessed access gate lines and conductive lines comprises active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric end projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric end projections. The trench isolation material comprises dielectric lateral projections extending laterally into opposing sides proximate the opposing ends under an elevationally outermost surface of the active area material proximate the opposing ends. The active area material is elevationally over the dielectric end projections proximate the opposing ends. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Conductive lines individually extend transversally across and elevationally over a mid-portion of the individual active area regions. Conductive material is directly against a mid-portion surface of the active area material of the individual active area regions and is conductively coupled to the conductive line transversally crossing thereover. The individual active area regions are longitudinally elongated along a straight longitudinal axis. The mid-portion surface is laterally narrower perpendicular to the longitudinal axis than the elevationally outermost surfaces proximate the opposing ends.
In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
This patent resulted from a divisional application of U.S. patent application Ser. No. 13/948,746, filed Jul. 23, 2013, entitled “Methods Of Forming An Array Of Conductive Lines, And Methods Of Forming An Array Of Recessed Access Gate Lines And An Array Of Conductive Lines”, naming Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, and Haitao Liu as inventors, the disclosure of which is incorporated by reference.
Number | Name | Date | Kind |
---|---|---|---|
4437226 | Scolof | Mar 1984 | A |
4489478 | Sakuri | Dec 1984 | A |
4845048 | Tamaki et al. | Jul 1989 | A |
5027184 | Scolof | Jun 1991 | A |
5112771 | Ishii et al. | May 1992 | A |
5442222 | Takasu | Aug 1995 | A |
5466621 | Hisamoto et al. | Nov 1995 | A |
5612230 | Yuzuihara et al. | Mar 1997 | A |
5681773 | Tseng et al. | Oct 1997 | A |
5801083 | Yu et al. | Sep 1998 | A |
5963789 | Tsuchiaki | Oct 1999 | A |
5972758 | Liang | Oct 1999 | A |
5998808 | Matsushita | Dec 1999 | A |
6232202 | Hong | May 2001 | B1 |
6285057 | Hopper et al. | Sep 2001 | B1 |
6300215 | Shin | Oct 2001 | B1 |
6313008 | Leung et al. | Nov 2001 | B1 |
6448100 | Schulte et al. | Sep 2002 | B1 |
6465865 | Gonzalez | Oct 2002 | B1 |
6482701 | Ishikawa et al. | Nov 2002 | B1 |
6521538 | Soga et al. | Feb 2003 | B2 |
6537862 | Song | Mar 2003 | B2 |
6642090 | Fried et al. | Nov 2003 | B1 |
6716757 | Lin et al. | Apr 2004 | B2 |
6774390 | Sugiyama et al. | Aug 2004 | B2 |
6784076 | Gonzalez et al. | Aug 2004 | B2 |
6921982 | Joshi et al. | Jul 2005 | B2 |
7005347 | Bhalla et al. | Feb 2006 | B1 |
7160789 | Park | Jan 2007 | B2 |
7220640 | Kim | May 2007 | B2 |
7291877 | Brederlow et al. | Nov 2007 | B2 |
7319252 | Chang | Jan 2008 | B2 |
7326634 | Lindert et al. | Feb 2008 | B2 |
7407845 | Lee et al. | Aug 2008 | B2 |
7407847 | Doyle et al. | Aug 2008 | B2 |
7413955 | Kim | Aug 2008 | B2 |
7422960 | Fischer et al. | Sep 2008 | B2 |
7537994 | Taylor et al. | May 2009 | B2 |
7671390 | Sonsky et al. | Mar 2010 | B2 |
7820505 | Brederlow et al. | Oct 2010 | B2 |
7825011 | Meunier-Bellard et al. | Nov 2010 | B2 |
7906388 | Sonsky | Mar 2011 | B2 |
7935602 | Wang et al. | May 2011 | B2 |
7939403 | Grisham et al. | May 2011 | B2 |
8124475 | Brederlow et al. | Feb 2012 | B2 |
8222102 | Grisham et al. | Jul 2012 | B2 |
8409946 | Grisham et al. | Apr 2013 | B2 |
20020031898 | Gonzalez et al. | Mar 2002 | A1 |
20020109155 | Shin et al. | Aug 2002 | A1 |
20020135549 | Kawata | Sep 2002 | A1 |
20020177282 | Song | Nov 2002 | A1 |
20030109766 | Gonzalez et al. | Oct 2003 | A1 |
20030227036 | Sugiyama et al. | Dec 2003 | A1 |
20040108523 | Chen et al. | Jun 2004 | A1 |
20040110358 | Lee | Jun 2004 | A1 |
20040110383 | Tanaka | Jun 2004 | A1 |
20040113230 | Divakaruni et al. | Jun 2004 | A1 |
20040150071 | Kondo et al. | Aug 2004 | A1 |
20040195610 | Morikado | Oct 2004 | A1 |
20040198003 | Yeo et al. | Oct 2004 | A1 |
20040198009 | Chen et al. | Oct 2004 | A1 |
20040262687 | Jung et al. | Dec 2004 | A1 |
20050029619 | Forbes | Feb 2005 | A1 |
20050087842 | Forbes | Apr 2005 | A1 |
20050136617 | Jang | Jun 2005 | A1 |
20050176186 | Lee et al. | Aug 2005 | A1 |
20050199932 | Abbott et al. | Sep 2005 | A1 |
20050218438 | Lindert et al. | Oct 2005 | A1 |
20050250279 | Son et al. | Nov 2005 | A1 |
20050282342 | Adan | Dec 2005 | A1 |
20050285149 | Chang | Dec 2005 | A1 |
20060003526 | Brederlow et al. | Jan 2006 | A1 |
20060046428 | Baiocco et al. | Mar 2006 | A1 |
20060068591 | Radosavljevic et al. | Mar 2006 | A1 |
20060076595 | Wu | Apr 2006 | A1 |
20060157688 | Bhattacharyya | Jul 2006 | A1 |
20060172497 | Hareland et al. | Aug 2006 | A1 |
20060244106 | Morikado | Nov 2006 | A1 |
20060292787 | Wang et al. | Dec 2006 | A1 |
20070034922 | Bhattacharyya | Feb 2007 | A1 |
20070082448 | Bong-soo et al. | Apr 2007 | A1 |
20070111439 | Jung et al. | May 2007 | A1 |
20070148934 | Cho et al. | Jun 2007 | A1 |
20070228383 | Bernstein et al. | Oct 2007 | A1 |
20070246754 | Sonsky et al. | Oct 2007 | A1 |
20080017931 | Shih et al. | Jan 2008 | A1 |
20080038888 | Brederlow et al. | Feb 2008 | A1 |
20090072351 | Meunier-Bellard et al. | Mar 2009 | A1 |
20090127615 | Sonsky | May 2009 | A1 |
20090159987 | Oh | Jun 2009 | A1 |
20090184355 | Brederlow et al. | Jul 2009 | A1 |
20100159683 | Lee et al. | Jun 2010 | A1 |
20110156103 | Penzes | Jun 2011 | A1 |
20120326214 | Cho | Dec 2012 | A1 |
20130320436 | Kim | Dec 2013 | A1 |
20140117492 | Kim | May 2014 | A1 |
Number | Date | Country |
---|---|---|
10157785 | Jun 2003 | DE |
0059264 | Sep 1982 | EP |
1229579 | Aug 2002 | EP |
H05110083 | Apr 1993 | JP |
H05243573 | Sep 1993 | JP |
H11150265 | Jun 1999 | JP |
2001093861 | Apr 2001 | JP |
2002359369 | Dec 2002 | JP |
2003-037272 | Feb 2003 | JP |
2003-243667 | Aug 2003 | JP |
2005079517 | Mar 2005 | JP |
2005-123404 | May 2005 | JP |
2005-229107 | Aug 2005 | JP |
2006-503440 | Jan 2006 | JP |
095120411 | Apr 2008 | TW |
096131528 | Jul 2011 | TW |
WO 2004038770 | May 2004 | WO |
WO 2005117073 | Dec 2005 | WO |
PCTUS2006020877 | Aug 2006 | WO |
WO 2006109265 | Oct 2006 | WO |
WO 2006117734 | Nov 2006 | WO |
PCTUS2006020877 | Dec 2006 | WO |
PCTUS2007016947 | Feb 2008 | WO |
PCTUS2007022856 | Mar 2008 | WO |
PCTUS2007016947 | Mar 2009 | WO |
PCTUS2007022856 | May 2009 | WO |
Entry |
---|
Ananthan, “FinFET—Current Research Issues”, School of Electrical and Computer Engineering, Purdue University; 2003; 5 pp. |
Kim et al., “S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) Technology for 70nm DRAM feature size and beyond”, 2005 Symposium on VLSI Technology Digest, pp. 34-35. |
Yeo et al., “80 nm 512M DRAM with Enhanced Data Retention Time Using Partially-Insulated Cell Array Transistor (PiCAT)”, 2004 Symposium on VLSI Technology Digest of Technology, 2004 IEEE, pp. 30-31. |
Number | Date | Country | |
---|---|---|---|
20160155745 A1 | Jun 2016 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 13948746 | Jul 2013 | US |
Child | 15005360 | US |