Patent Application
20190019893
The present disclosure generally relates to display techniques, and particularly relates to an array substrate, its manufacturing method, and a liquid crystal display (LCD) panel using the array substrate.
Following the advancement in the dimension and resolution of liquid crystal displays (LCDs), Thin Film Transistor (TFT) becomes the mainstream technique for LCD devices. Currently, TFT active layer is mainly formed using Indium Gallium Zinc Oxide (IGZO) and, within the active layer, TFT channels are formed on the source and drain patterns. Due to that IGZO is highly sensitive in terms of its electrical properties, the channels are easily damaged during the LCD manufacturing process for example by the etching solution when forming the source and drain patterns, thereby affecting the channels' electrical properties.
Therefor the present disclosure teaches an array substrate, its manufacturing method, and a liquid crystal display (LCD) panel using the array substrate that prevent damages to and ensure electrical properties of Thin Film Transistor (TFT) channels.
An embodiment of the array substrate manufacturing method includes the following steps.
sequentially forming a gate pattern and a gate insulation layer are a substrate;
sequentially forming an active layer, an amorphous silicon layer, a metallic layer, and a photoresist layer on the gate insulation layer;
conducting exposure and development on the photoresist layer using a half-tone mask and forming a first photoresist area and second photoresist areas to the lateral sides of the first photoresist area, where the first photoresist area has a smaller thickness than that of the second photoresist areas;
removing the active layer, the amorphous silicon layer, and the metallic layer not covered by the first and second photoresist areas by etching;
conducting an ashing process on the first and second photoresist areas so as to remove the first photoresist area but keep a portion of the second photoresist area;
removing the metallic layer not covered by the portion of the second photoresist area by etching, and forming the source and drain patterns;
removing the portion of the second photoresist area;
forming a flat layer on the gate insulation layer and covers the source and drain patterns, where the flat layer has a via exposing the drain pattern; and
forming an electrode pattern on the flat layer, where the electrode pattern contacts the drain pattern through the via.
An embodiment of the array substrate includes the following components.
a substrate;
a gate pattern and a gate insulation layer sequentially formed on the substrate;
an active layer, an amorphous silicon layer, a source pattern, and a drain pattern sequentially formed on the gate insulation layer;
a flat layer on the gate insulation layer covering the source and drain patterns, where the flat layer has a via exposing the drain pattern; and
an electrode pattern on the flat layer, where the electrode pattern contacts the drain pattern through the via.
An embodiment of the LCD panel includes an array substrate and the array substrate includes the following components.
a substrate;
a gate pattern and a gate insulation layer sequentially formed on the substrate;
an active layer, an amorphous silicon layer, a source pattern, and a drain pattern sequentially formed on the gate insulation layer;
a flat layer on the gate insulation layer covering the source and drain patterns, where the flat layer has a via exposing the drain pattern; and
an electrode pattern on the flat layer, where the electrode pattern contacts the drain pattern through the via.
The advantages of the present disclosure is that an amorphous silicon layer, as a layer of protection, on the TFT active layer so that, during the formation of the source and drain patterns by etching, the amorphous silicon layer ensures the electrical properties of the TFT channels by preventing the etching solution from contacting the active layer and thereby damaging the TFT channels.
To make the technical solution of the embodiments according to the present disclosure, a brief description of the drawings that are necessary for the illustration of the embodiments will be given as follows. Apparently, the drawings described below show only example embodiments of the present disclosure and for those having ordinary skills in the art, other drawings may be easily obtained from these drawings without paying any creative effort. In the drawings:
In the following, the present disclosure is explained in details through embodiments and accompanying drawings. It should be understood that not all possible embodiments are disclosed. Other embodiments derived from the following embodiments by a reasonably skilled person in the art without significant inventive effort should be considered to be within the scope of the present disclosure.
The major objective of the present disclosure is to form an amorphous silicon layer on the Thin Film Transistor (TFT) active layer so that, during the formation of the source and drain patterns by etching, the amorphous silicon layer ensures the electrical properties of the TFT channels by preventing the etching solution from contacting the active layer and thereby damaging the TFT channels.
As illustrated in
In step S11, a gate pattern and a gate insulation layer are sequentially formed on a substrate.
As shown in
In the present embodiment, the gate pattern 221 may be formed on the substrate 21 through a masking process. Specifically, a metallic layer is first formed on the substrate 21 through Physical Vapor Deposition (PVD), and a photoresist layer is coated on the metallic layer. Then, the exposure and development process is conducted on the photoresist layer through a mask. The fully exposed portion of the photoresist is removed by developer solution, and the un-exposed portion of the photoresist remains. The part of the metallic layer not covered by the photoresist is etched and then the photoresist is removed. The remaining part of the metallic layer becomes the TFT gate pattern 221.
In the present embodiment, the gate insulation layer 23 may be formed on and cover the entire the gate pattern 221 through Chemical Vapor Deposition (CVD). The gate insulation layer 23 may be made of silicon oxide (SiOx). To enhance its abrasion resistance and insulation performance, the gate insulation layer 23 may also include silicon oxide and silicon nitride, such as SiO2 and Si3N4, sequentially formed on the gate pattern 221.
In step S12, an active layer, an amorphous silicon layer, a metallic layer, and a photoresist layer are sequentially formed on the gate insulation layer.
As shown in
In step S13, exposure and development are conducted on the photoresist layer using a half-tone mask and thereby forming a first photoresist area and second photoresist areas to the lateral sides of the first photoresist area. The first photoresist area has a smaller thickness than that of the second photoresist areas.
As shown in
In step S14, the active layer, the amorphous silicon layer, and the metallic layer not covered by the first and second photoresist areas are etched.
In the present embodiment, a wet etching process may be applied to the metallic layer 26. That is, by submerging the first and second photoresist areas 271 and 272 in the etching solution, the portion of the metallic layer 26 not covered by the first and second photoresist areas 271 and 272 reacts with and dissolves in the etching solution. The other portion of the metallic layer 26 covered by the first and second photoresist areas 271 and 272 then remains. Furthermore, a dry etching process may be applied to the amorphous silicon layer 25, and a wet etching process may be applied to the active layer 24.
In step S15, an ashing process is conducted on the first and second photoresist areas so as to remove the first photoresist area but keep a portion of the second photoresist area.
After the ashing process, the first photoresist area 271 is removed, and the second photoresist area remains but has a smaller thickness.
In step S16, the metallic layer not covered by the portion of the second photoresist area is etched and the source and drain patterns are formed.
In the present embodiment, the wet etching process may be again applied to the metallic layer 26. The portion of the metallic layer 26 not covered by the portion of the second photoresist area 272 does not react with the etching solution and remains and therefore forms the source pattern 222 and the drain pattern 223. The space between the source pattern 222, the drain pattern 223, and the active layer 24 may be deemed as the TFT channel, and the channel layer is above the active layer and between the second photoresist areas 272.
In step S17, the portion of the second photoresist area is removed.
In step S18, a flat layer is formed on the gate insulation layer and covers the source and drain patterns. The flat layer includes a via exposing the drain pattern.
In the present embodiment, the flat layer 28 is formed to cover the source and drain patterns 222 and 223 through a masking process. Specifically, an entire silicon oxide layer is formed through CVD, an entire photoresist layer is then coated on the silicon oxide layer, and then exposure and development is conducted through a mask. The fully exposed portion of the photoresist is removed by developer solution, and the un-exposed portion of the photoresist remains. The part of the silicon oxide layer not covered by the photoresist is etched to form the via 281 exposing the drain pattern 223. Finally, the photoresist is removed and the remaining silicon oxide layer becomes the flat layer 28.
In step S19, an electrode pattern is formed on the flat layer and contacts the drain pattern through the via.
In the present embodiment, the electrode pattern 29 is formed through a masking process according to existing arts. The electrode pattern 29 is the pixel electrodes of the array substrate, and its material may be Indium Tin Oxide (ITO).
As described above, the present embodiment forms an amorphous silicon layer 25 as a protection layer on TFT channels so that, during the formation of the source and drain patterns 222 and 223 by etching, the amorphous silicon layer 25 ensures the electrical properties of the TFT channels by preventing the etching solution from contacting the active layer 24 and thereby damaging the TFT channels.
As illustrated in
In step S31, a gate pattern and a gate insulation layer are sequentially formed on a substrate.
In step S32, an active layer, an amorphous silicon layer, a heavily doped silicon layer, a metallic layer, and a photoresist layer are sequentially formed on the gate insulation layer.
In step S33, exposure and development are conducted on the photoresist layer using a half-tone mask and thereby forming a first photoresist area and second photoresist areas to the lateral sides the first photoresist area. The first photoresist area has a smaller thickness than that of the second photoresist areas.
In step S34, the active layer, the amorphous layer, the heavily doped silicon layer, and the metallic layer not covered by the first and second photoresist areas are etched.
In step S35, an ashing process is conducted on the first and second photoresist areas so as to remove the first photoresist area but keep a portion of the second photoresist area.
In step S36, the heavily doped silicon layer and the metallic layer both not covered by the portion of the second photoresist area are etched and the source and drain patterns are formed.
In step S37, the portion of the second photoresist area is removed.
In step S38, a flat layer is formed on the gate insulation layer and covers the source and drain patterns. The flat layer includes a via exposing the drain pattern.
In step S39, an electrode pattern is formed on the flat layer and contacts the drain pattern through the via.
What is different from the previous embodiment lies in the inclusion of a heavily doped silicon layer 30 between the amorphous silicon layer 25 and the metallic layer 26 in step S32. The heavily doped silicon layer 30 may be doped with n+ ion impurities. For example, the heavily doped silicon layer 30 includes n+Si. In addition, in the etching process of step S34, a portion of the heavily doped silicon layer 30 not covered by the first and second photoresist areas 271 and 272 is removed by etching. Furthermore, in the etching process of step S36, a portion of the heavily doped silicon layer 30 not covered by the second photoresist areas 272 is removed by etching. In the array substrate produced by the present embodiment, heavily doped silicon layers 30 are formed between the amorphous silicon layer 25 and the drain pattern 223, and between the amorphous silicon layer 25 and the source pattern 222. The heavily doped silicon layers 30 improves the amorphous silicon layer 25's electrical contacts with the source and drain patterns 222 and 223, so as to ensure the electrical properties of the TFT channels.
As illustrated in
In step S51, a gate pattern and a gate insulation layer are sequentially formed on a substrate.
In step S52, an active layer, an amorphous silicon layer, and a heavily doped silicon layer are sequentially formed on the gate insulation layer.
In step S53, annealing is conducted on the heavily doped silicon layer so that silicon atoms of the heavily doped silicon layer enter and dope the active layer.
In step S54, a metallic layer and a photoresist layer are sequentially formed on the annealed heavily doped silicon layer.
In step S55, exposure and development are conducted on the photoresist layer using a half-tone mask and thereby forming a first photoresist area and second photoresist areas to the lateral sides the first photoresist area. The first photoresist area has a smaller thickness than that of the second photoresist areas.
In step S56, the active layer, the amorphous layer, the heavily doped silicon layer, and the metallic layer not covered by the first and second photoresist areas are etched.
In step S57, an ashing process is conducted on the first and second photoresist areas so as to remove the first photoresist area but keep a portion of the second photoresist area.
In step S58, the heavily doped silicon layer and the metallic layer both not covered by the portion of the second photoresist area are etched and the source and drain patterns are formed.
In step S59, the portion of the second photoresist area is removed.
In step S60, a flat layer is formed on the gate insulation layer and covers the source and drain patterns. The flat layer includes a via exposing the drain pattern.
In step S61, an electrode pattern is formed on the flat layer and contacts the drain pattern through the via.
During the annealing process, Si atoms in the heavily doped silicon layer 30 diffuse into the active layer 24 which becomes doped active layer 24 such as an N+IGZO layer. Si-doped IGZO better withstands reversed bias and light irradiation than un-doped IOGZO does. The present embodiment therefore may further enhance the electrical stability of TFT.
Through the above methods, a desired array substrate is produced.
The present disclosure also teaches a liquid crystal display (LCD) panel. As shown in
Embodiments of the present disclosure have been described, but not intending to impose any unduly constraint to the appended claims. Any modification of equivalent structure or equivalent process made according to the disclosure and drawings of the present disclosure, or any application thereof, directly or indirectly, to other related fields of technique, is considered encompassed in the scope of protection defined by the claims of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201710565730.X | Jul 2017 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2017/098439 | 8/22/2017 | WO | 00 |
