Patent Application
20150364438
1. Field of the Invention
Disclosed embodiments relate to balancing current distribution structures.
2. Description of the Related Art
Power management integrated circuits (PMIC's) are circuits specifically designed to manage the power consumption of a system. In particular, a PMIC may process the raw voltage from a power supply, such as a battery, and in turn supply regulated voltages to drive a plurality of off-chip power consumption entities separate from the PMIC. Modern PMIC's are becoming increasingly integrated due to greater system complexity. A typical PMIC may include many high-power on-chip modules for driving off-chip power consumption entities, such as switched-mode battery chargers (SMBC's), back light display drivers (WLED's), buck regulators, audio amplifiers, and flash LED drivers. The on-chip modules may dissipate considerable power when processing power to or from the off-chip entities.
Semiconductor integrated circuit chips can be connected in order to enable them to interact electrically with the outside world. A ball grid array (BGA) semiconductor chip package can employ a plurality of solder balls as external terminals. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The leads on a BGA can be shorter than with a perimeter-only type.
Power management integrated circuits (PMIC) products can have higher current requirement. Several balls can be used to share the current. By balancing current equally on each ball, the number of BGA balls used may be minimized.
The disclosure is directed to balancing current distribution structures.
For example, an exemplary embodiment is directed to an apparatus comprising: an input portion; a low resistance portion of a ball grid array (BGA) coupled to the input portion by at least two vias forming a three-dimensional section; and at least one ball of the BGA coupled to the low resistance portion over a narrow trace.
Another exemplary embodiment is directed to a method for balancing current delivery, the method comprising: coupling a low resistance portion of a ball grid array (BGA) to an input portion by at least two vias forming a three-dimensional section; and coupling at least one ball of the BGA to the low resistance portion over a narrow trace.
Still another exemplary embodiment is directed to an apparatus comprising: means for coupling a low resistance portion of a ball grid array (BGA) to an input portion by at least two vias forming a three-dimensional section; and means for coupling at least one ball of the BGA to the low resistance portion over a narrow trace.
Some advantages to the present disclosure include resistance from a first ball to a second ball of the array can be higher than resistance in other parts of the BGA. The increased resistance can limit the first ball current. Some embodiments can increase package reliability. Because the number of balls and vias is less than in prior art versions, there can be an increase in cost savings.
A more complete appreciation of aspects of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings which are presented solely for illustration and not limitation of the disclosure, and in which:
Various aspects are disclosed in the following description and related drawings. Alternate aspects may be devised without departing from the scope of the disclosure. Additionally, well-known elements of the disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of the disclosure.
The words “exemplary” and/or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and/or “example” is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term “aspects of the disclosure” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation.
Further, many aspects are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the disclosure may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the aspects described herein, the corresponding form of any such aspects may be described herein as, for example, “logic configured to” perform the described action.
The array package 100 is mounted on a printed circuit board (PCB) 110 or similar component. The PCB 110 is typically a laminate. The array package 100 is connected to the PCB 110 by a plurality of solder balls 115. The solder balls 115 may provide both a mechanical and electrical connection between the array package 100 and the PCB 110.
Each ball can have a section between itself and at least one other ball in the BGA 404. In
In one embodiment, current can be input at the input portion 402. The current can be received by the third ball 404C and the fourth ball 404D through vias 406. This current can be shared with the second ball 404B and travel through the first section 408A to the first ball 404A. For example, the narrower width of the first section 408A as compared to the second section 408B and the third section 408C can increase the resistivity of the first section 408A. Thus, the placement of the vias 406 on the fourth ball 404D, the placement of the vias near the third ball 404C, and the width of the first section 408A allow the BGA 404 to balance the current between the four balls.
In some embodiments, the BGA 504 can be routed around a packet edge. In some embodiments, the apparatus 500 can include a flip chip package. In some embodiments, the apparatus 500 can include a wire bond package. For illustrative purposes, the PCB 508 can have a thickness of 18 um. The balls 504A-D can have 500 um pitch and can be 300 um in size. A PCB layout trace can be 400 um wide and 18 um thick.
Table 1 provides exemplary data relating to
In some embodiments, the at least two vias are positioned close to a third ball of the at least four balls. In some embodiments, the at least two vias are coupled to a fourth ball of the at least four balls. In some embodiments, the input portion is coupled between a third ball of the at least four balls and a fourth ball of the at least four balls.
In
Generally, unless stated otherwise explicitly, the phrase “logic configured to” as used throughout this disclosure is intended to invoke an aspect that is at least partially implemented with hardware, and is not intended to map to software-only implementations that are independent of hardware. Also, it will be appreciated that the configured logic or “logic configured to” in the various blocks are not limited to specific logic gates or elements, but generally refer to the ability to perform the functionality described herein (either via hardware or a combination of hardware and software). Thus, the configured logics or “logic configured to” as illustrated in the various blocks are not necessarily implemented as logic gates or logic elements despite sharing the word “logic.” Other interactions or cooperation between the logic in the various blocks will become clear to one of ordinary skill in the art from a review of the aspects described below in more detail.
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The methods, sequences and/or algorithms described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in an electronic object. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
While the foregoing disclosure shows illustrative aspects of the disclosure, it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the aspects of the disclosure described herein need not be performed in any particular order. Furthermore, although elements of the disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
