Ball grid array

Abstract

A ball grid array includes: a semiconductor chip having multiple pads; and an interposer for mounting the semiconductor chip on a first surface. The interposer includes multiple wirings on the first surface and multiple ball terminals on a second surface opposite to the first surface. Each wiring is connected to a corresponding pad of the semiconductor chip, and is electrically connected to a corresponding ball terminal. At least one of ball terminals providing a power supply terminal or a ground terminal provides a common ball terminal for connecting to at least two of the pads of the semiconductor chip through two wirings.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:

FIG. 1 is a cross sectional view showing a ball grid array according to an example embodiment;

FIG. 2 is a plan view showing solder balls of an interposer;

FIG. 3 is a plan view showing the interposer for mounting a semiconductor chip thereon;

FIG. 4 is a diagram showing a wiring path in a first pattern, which connects lands to a common solder ball when the lands correspond to at least 2 pieces of pads employed as either power supply-purpose pads or GND-purpose pads;

FIG. 5A is a diagram showing a wiring path in a second pattern, which connects lands to a common solder ball when the lands correspond to at least 2 pieces of pads employed as either power supply-purpose pads or GND-purpose pads,

FIG. 5B is a partially sectional and perspective view showing the wiring path, and

FIG. 5C is an explanatory diagram explaining the reason why entering of noise can be more firmly prevented;

FIG. 6 is a cross sectional view showing a modification in which a ball grid array has been mounted on a surface of an interposer;

FIG. 7 is a plan view showing the interposer for mounting a semiconductor chip in the modification shown in FIG. 6;

FIG. 8 is a circuit diagram indicating a first circuit for separately checking as to whether or not an abnormal event such as a line disconnection occurs in the wiring lines connected to the common solder ball; and

FIG. 9 is a circuit diagram indicating a second circuit for separately checking as to whether or not an abnormal event such as a line disconnection occurs in the wiring lines connected to the common solder ball.

Claims

1. A ball grid array comprising: a semiconductor chip having a plurality of pads; andan interposer for mounting the semiconductor chip on a first surface of the interposer, whereinthe interposer includes a plurality of wirings disposed on the first surface and a plurality of ball terminals disposed on a second surface, which is opposite to the first surface,each wiring is connected to a corresponding pad of the semiconductor chip, and is electrically connected to a corresponding ball terminal, andat least one of ball terminals providing a power supply terminal or a ground terminal provides a common ball terminal for connecting to at least two of the pads of the semiconductor chip through two wirings.

2. The array according to claim 1, wherein the semiconductor chip further includes a plurality of functional circuits,each functional circuit has a power supply and a ground,the pads include a plurality of power supply pads and a plurality of ground pads, which correspond to the power supplies and the grounds in the functional circuits, respectively, andthe power supply pads are commonly connected to a first common ball terminal and/or the ground pads are commonly connected to a second common ball terminal.

3. The array according to claim 1, wherein the semiconductor chip further includes a plurality of functional circuits,each functional circuit has a power supply and a ground,the pads include a plurality of power supply pads and a plurality of ground pads, which correspond to the power supplies and the grounds in the functional circuits, respectively,the power supply pads include a plurality of small current power supply pads, each of which is capable of flowing a current smaller than a predetermined current,the ground pads include a plurality of small current ground pads, each of which is capable of flowing a current smaller than the predetermined current, andthe small current power supply pads are commonly connected to a first common ball terminal and/or the small current ground pads are commonly connected to a second common ball terminal.

4. The array according to claim 1, wherein the semiconductor chip further includes a plurality of functional circuits,each functional circuit has a power supply and a ground,the pads include a plurality of power supply pads and a plurality of ground pads, which correspond to the power supplies and the grounds in the functional circuits, respectively,the power supply pads include a plurality of small noise power supply pads, each of which generates a noise smaller than a predetermined noise,the ground pads include a plurality of small noise ground pads, each of which generates a noise smaller than the predetermined noise, andthe small noise power supply pads are commonly connected to a first common ball terminal and/or the small noise ground pads are commonly connected to a second common ball terminal.

5. The array according to claim 1, wherein the semiconductor chip further includes a plurality of functional circuits,each functional circuit has a power supply and a ground,the pads include a plurality of power supply pads and a plurality of ground pads, which correspond to the power supplies and the grounds in the functional circuits, respectively,the functional circuits further include an analog circuit for processing an analog signal and a plurality of digital circuits for processing a digital signal,the power supply pad corresponding to the power supply in the analog circuit is connected to one of the ball terminals,the ground pad corresponding to the ground in the analog circuit is connected to another ball terminal, andthe power supply pads corresponding to the power supplies in the digital circuits are commonly connected to a first common ball terminal, and/or the ground pads corresponding to the grounds in the digital circuits are commonly connected to a second common ball terminal.

6. The array according to claim 1, wherein the semiconductor chip further includes a plurality of functional circuits,each functional circuit has a power supply and a ground,the pads include a plurality of power supply pads and a plurality of ground pads, which correspond to the power supplies and the grounds in the functional circuits, respectively,the functional circuits further include an analog circuit for processing an analog signal and a plurality of digital circuits for processing a digital signal,the power supply pad corresponding to the power supply in the analog circuit is connected to a first ball terminal among the ball terminals,the ground pad corresponding to the ground in the analog circuit is connected to a second ball terminal among the ball terminals,the digital circuits include an input circuit for inputting a digital signal from an external circuit and a plurality of output circuits for outputting the digital signal to the external circuit,the power supply pad corresponding to the power supply in the input circuit is connected to a third ball terminal among the ball terminals,the ground pad corresponding to the ground in the input circuit is connected to a fourth ball terminal among the ball terminals, andthe power supply pads corresponding to the power supplies in the output circuits are commonly connected to a first common ball terminal, and/or the ground pads corresponding to the grounds in the output circuits are commonly connected to a second common ball terminal.

7. The array according to claim 1, wherein one of the pads is disposed between the two of the pads, which are connected to the common ball terminal,the one of the pads is capable of transmitting a significant signal so that the one of the pads provides a significant signal pad, andtwo wirings connecting to the two of the pads surround one wiring connecting to the significant signal pad on the first surface of the semiconductor chip.

8. The array according to claim 7, wherein the interposer further includes a plurality of through holes penetrating the interposer from the first surface to the second surface,each ball terminal and a corresponding wiring are connected through a conductive member in a corresponding through hole,the two wirings connecting to the two of the pads are commonly connected to a common conductive member in a common through hole,the one wiring connecting to the significant signal pad is connected to a significant signal conductive member in a significant signal through hole, anda distance between the common through hole and the semiconductor chip is larger than a distance between the significant signal through hole and the semiconductor chip.

9. The array according to claim 7, wherein the pads includes inner side pads and outer side pads,the inner side pads are disposed inside of the semiconductor chip, and the outer side pads are disposed outside of the semiconductor chip,the semiconductor chip is mounted on the interposer in a flip-chip mount manner,the significant signal pad is one of the inner side pads, andthe two of the pads are two of the outer side pads.

10. The array according to claim 1, wherein the interposer further includes a plurality of through holes penetrating the interposer from the first surface to the second surface,each ball terminal and a corresponding wiring are electrically connected through a conductive member in a corresponding through hole,the interposer further includes a branch line disposed on the second surface,the branch line connects the common ball terminal and at least two conductive members in two through holes,the two of the pads are connected to the common ball terminal through the branch line and the two conductive members, andthe two of the pads are individually connected to the two conductive members through two wirings.

11. The array according to claim 1, wherein the interposer further includes a plurality of through holes penetrating the interposer from the first surface to the second surface,each ball terminal and a corresponding wiring are electrically connected through a conductive member in a corresponding through hole,the two of the pads are connected to two wirings, respectively,the two wirings are commonly connected to a common conductive member in a common through hole,the common conductive member is connected to the common ball terminal so that the two of the pads are commonly connected to the common ball terminal, anda first impedance between the two of the pads and a connection portion of the two wirings is larger than a second impedance between the connection portion and the common ball terminal.

12. The array according to claim 11, wherein an electric passage between the two of the pads and the connection portion of the two wirings has a first width, andanother electric passage between the connection portion and the common ball terminal has a minimum width, which is larger than the first width.

13. The array according to claim 1, wherein the semiconductor chip further includes: a switching circuit for individually connecting and disconnecting two wiring passages disposed in the semiconductor chip, the two wiring passages being individually connected to the two of the pads; anda check circuit for individually checking conductivity of the two wiring passages when the switching circuit connects two wiring passages to the two of the pads one by one.

14. The array according to claim 1, wherein the semiconductor chip further includes: a current supplying circuit for individually supplying a current to two wiring passages disposed in the semiconductor chip, the two wiring passages being individually connected to the two of the pads;a detecting circuit for detecting a current flowing through each wiring passage, respectively; anda check circuit for individually checking conductivity of the two wiring passages based on the current detected by the detecting circuit when the current supplying circuit supplies the current to the two wiring passages.

15. The array according to claim 1, wherein at least one of the pads capable of transmitting a significant signal is connected to a plurality of wirings on the first surface of the interposer.