This disclosure relates generally to electrically conductive traces having high electrical conductivity and low mutual capacitance, and more specifically to bit lines formed using an electrically conductive material having a high electrical conductivity, and air gaps between the bit lines.
Continued demand for high density devices has driven semiconductor device manufacturers to design device features at or near manufacturing process tolerances. For example, bit lines in memory devices may be manufactured at or near process tolerances, which may result in bit lines being relatively narrow and being relatively close to other bit lines. In other words, in order to keep chip area, or “real estate,” occupied by the bit lines as small as possible, the bit lines may be made as narrow as possible and may be spaced as closely together as possible.
While this disclosure concludes with claims particularly pointing out and distinctly claiming specific embodiments, various features and advantages of embodiments within the scope of this disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown, by way of illustration, specific examples of embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable a person of ordinary skill in the art to practice the present disclosure. However, other embodiments enabled herein may be utilized, and structural, material, and process changes may be made without departing from the scope of the disclosure.
The illustrations presented herein are not meant to be actual views of any particular method, system, device, or structure, but are merely idealized representations that are employed to describe the embodiments of the present disclosure. In some instances similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other property.
The following description may include examples to help enable one of ordinary skill in the art to practice the disclosed embodiments. The use of the terms “exemplary,” “by example,” and “for example,” means that the related description is explanatory, and though the scope of the disclosure is intended to encompass the examples and legal equivalents, the use of such terms is not intended to limit the scope of an embodiment or of this disclosure to the specified components, steps, features, functions, or the like.
It will be readily understood that the components of the embodiments as generally described herein and illustrated in the drawings could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While the various aspects of the embodiments may be presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
Furthermore, specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless specified otherwise herein. Elements, circuits, and functions may be shown in block diagram form in order not to obscure the present disclosure in unnecessary detail. Conversely, specific implementations shown and described are exemplary only and should not be construed as the only way to implement the present disclosure unless specified otherwise herein. Additionally, block definitions and partitioning of logic between various blocks is exemplary of a specific implementation. It will be readily apparent to one of ordinary skill in the art that the present disclosure may be practiced by numerous other partitioning solutions. For the most part, details concerning timing considerations and the like have been omitted where such details are not necessary to obtain a complete understanding of the present disclosure and are within the abilities of persons of ordinary skill in the relevant art.
Those of ordinary skill in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. Some drawings may illustrate signals as a single signal for clarity of presentation and description. It will be understood by a person of ordinary skill in the art that the signal may represent a bus of signals, wherein the bus may have a variety of bit widths and the present disclosure may be implemented on any number of data signals including a single data signal.
The embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts can be performed in another sequence, in parallel, or substantially concurrently. In addition, the order of the acts may be re-arranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, other structure, or combinations thereof.
Any reference to an element herein using a designation such as “first,” “second,” and so forth does not limit the quantity or order of those elements, unless such limitation is explicitly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in some manner. In addition, unless stated otherwise, a set of elements may include one or more elements.
As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90% met, at least 95% met, or even at least 99% met.
As used herein, the term “low-k dielectric material” refers to a material that has a relative permittivity less than that of silicon dioxide. The relative permittivity of silicon dioxide is substantially 3.9. As used herein, the term “relative permittivity” refers to the ratio of the absolute permittivity of a material divided by the absolute permittivity of free space co (i.e., substantially 8.854×10-6 picofarads per micrometer (pF/μm)). Accordingly, the term “low-k dielectric material” refers herein to dielectric materials that have a relative permittivity of less than substantially 3.9, and an absolute permittivity of less than substantially 34.53×10−6 pF/μm. One example of a low-k dielectric material is organosilicate glass, which is silicon dioxide doped with carbon.
As used herein, the term “semiconductor material” refers to a material having a conductivity between those of electrically insulating materials and electrically conductive materials. For example, a semiconductor material may have a conductivity of between about 10−8 Siemens per centimeter (S/cm) and 104 S/cm (106 S/m) at room temperature (e.g., between about twenty degrees centigrade and about twenty-five degrees centigrade). Examples of semiconductor materials include elements found in column IV of the period table of elements such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include compound semiconductor materials such as binary compound semiconductor materials (e.g., gallium arsenide (GaAs)), ternary compound semiconductor materials (e.g., AlXGa1-XAs), and quaternary compound semiconductor materials (e.g., GaXIn1-XAsYP1-Y), without limitation. Compound semiconductor materials may include combinations of elements from columns III and V of the period table of elements (III-V semiconductor materials) or from columns II and VI of the period table of elements (II-VI semiconductor materials), without limitation. Semiconductor devices often include crystalline semiconductor materials. By way of non-limiting examples, transistors and diodes include crystalline semiconductor materials.
As used herein, the term “electrically conductive material” refers to materials having electrical conductivities greater than or equal to substantially 104 S/cm. Various different electrically conductive materials may be used to electrically connect circuit elements in semiconductor devices. By way of non-limiting example, electrically conductive materials may be used for bit lines (e.g., data lines) of a memory device to electrically connect memory cells to circuitry of the memory device (e.g., sense amplifier circuitry). The unrelenting demand for ever smaller devices in semiconductor devices has driven width and spacing of bit lines in memory devices to manufacturing process tolerances. As a result, bit lines, as well as other electrically conductive features (e.g., electrically conductive traces) in various semiconductor devices, may be made as narrow as possible and may be spaced as closely together as possible.
Parasitic resistances of electrically conductive traces such as bit lines may increase as the width of such traces decreases (i.e., narrower traces generally have higher parasitic resistances than wider traces if all other things are substantially equal). As a result, parasitic resistances of electrically conductive traces have generally increased with the ever persistent demand for smaller devices and higher device density in semiconductor devices.
Also, parasitic capacitances between adjacent electrically conductive traces such as bit lines may increase as the distance between the adjacent traces decreases (i.e., traces that are closer together generally have higher mutual capacitance than traces that are further apart from each other if all other things are substantially equal). As a result, parasitic capacitances between electrically conductive traces have generally increased with the ever persistent demand for smaller devices and higher device density in semiconductor devices.
The higher parasitic resistances and/or capacitances due to smaller and/or denser semiconductor devices may result in degradation of device performance as compared to larger and/or less dense semiconductor devices, which may have lower parasitic resistances and/or capacitances. For example, signal switching speed may be degraded due to higher resistances and/or capacitances. In devices such as memory devices, the higher parasitic resistances and/or capacitances of bit lines may increase a minimum detectable amount of charge that is delivered to a bit line during a read operation. With smaller and smaller charge storage elements (e.g., capacitive elements such as dynamic random access memory (DRAM) memory cells) used for memory cells, a relatively small amount of charge may be expected from a memory cell during a read operation. This relatively small amount of charge may be in opposition to increased minimum detectable amounts of charge at a bit line due, at least in part, to increased resistances and/or capacitances of bit lines. As a result, the likelihood of failed read operations may increase for smaller and/or denser bit lines.
One way to reduce the mutual capacitance between adjacent bit lines is to dispose a material having a low absolute permittivity between the bit lines. Since a mutual capacitance between electrically conductive plates, such as bit lines, is proportional to the absolute permittivity of the material between the plates (C=kA/d where C is the mutual capacitance, k is the absolute permittivity, A is the overlapping area of the electrically conductive plates, and d is the distance between the plates), the mutual capacitance may be relatively low if a material between bit lines has a relatively low absolute permittivity. Since air has an absolute permittivity substantially equal to that of free space, which has a minimum absolute permittivity, air gaps between bit lines may provide for a lowest practical mutual capacitance between the bit lines. As used herein, the term “air gap” refers to a gap of gas such as air, a vacuum gap, an air insulator, an opening, or other similar gap. The composition and degree of air gap density may be tailored to meet dielectric and mechanical goals for a device design.
One way to reduce the parasitic resistance of a bit line is to use an electrically conductive material having a high electrical conductivity to form the bit line. Copper is an example of an electrically conductive material that has a relatively high electrical conductivity. Specifically, the electrical conductivity of copper at room temperature is substantially 59.5×106 Siemens/meter (S/m), which is much higher than electrical conductivities of other electrically conductive materials used in semiconductor devices. By comparison, the electrical conductivities of aluminum, tungsten, iron, and titanium are substantially 35×106 S/m, 17.9×106 S/m, 10×106, and 2.38×106 S/m, respectively.
Given the relatively low absolute permittivity of air gaps and the relatively high electrical conductivity of copper, relatively low parasitic capacitances and parasitic resistances may be achieved using copper bit lines with air gaps in between. Copper bit lines with air gaps therebetween, however, may not have sufficient mechanical strength to support bit line structures through stresses applied thereto during manufacturing processes. As a result, a more suitable electrically conductive material with superior mechanical strength (e.g., tungsten) may be used for bit lines to enable placement of air gaps between the bit lines. Tungsten, however, has a lower electrical conductivity than copper. This lower electrical conductivity of tungsten may result in a higher parasitic resistance of tungsten bit lines as compared to a lower parasitic resistance of copper bit lines, which may also result in degraded performance of the bit lines, as discussed above.
Disclosed herein are methods of manufacturing bit lines by forming a first electrically conductive material having desirable mechanical strength characteristics, forming air gaps therebetween, reinforcing the air gaps using a low-k dielectric material and a subconformal dielectric material, recessing the first electrically conductive material, and replacing the recessed first electrically conductive material with a second electrically conductive material that is more electrically conductive than the first electrically conductive material. By way of non-limiting example, tungsten bit lines may be formed, air gaps may be formed therebetween, the air gaps may be reinforced (e.g., with a low-k dielectric material), and at least a portion of the tungsten may be recessed and replaced with copper. Accordingly, apparatuses manufactured according to embodiments disclosed herein may benefit from the superior electrical conductivity of copper while simultaneously benefitting from the low absolute permittivity of air gaps and the low absolute permittivity of the low-k dielectric material therebetween. Bit lines manufactured according to embodiments disclosed herein may thus have relatively low parasitic resistances and capacitances, which may be beneficial given the ever persistent demand for smaller and denser devices in semiconductor devices. These bit lines may be used in three-dimensional NAND devices (e.g., may be connected to strings of NAND memory cells, without limitation).
Referring to
In some embodiments at least some of the bit lines 102a-102g include a first electrically conductive material 112 in a first portion and a second electrically conductive material 114 in a second portion. The second electrically conductive material 114 may be more electrically conductive than the first electrically conductive material 112. By way of non-limiting example, the first electrically conductive material 112 may include tungsten, which has an electrical conductivity of substantially 17.9×106 (S/m) (at 20° centigrade), and the second electrically conductive material 114 may include copper, which has an electrical conductivity of substantially 59.5×106 S/m (at 20° centigrade). Accordingly, in some embodiments at least some of the bit lines 102a-102g include tungsten in a first portion and copper in a second portion. In some embodiments the entirety of the bit lines 102a-102g may include substantially only the second electrically conductive material 114, substantially excluding the first electrically conductive material 112 (not shown). Although copper may not be as mechanically strong as tungsten, the added support provided by the low-k dielectric material 126 may provide mechanical support to the copper, which enables the use of the more conductive, though less mechanically strong, copper as the second electrically conductive material 114. In some embodiments the contacts 132 may include the first electrically conductive material 112 (e.g., tungsten).
Since the low-k dielectric material 126 has a relatively low absolute permittivity, the low-k dielectric material 126 may provide the mechanical support to the bit lines 102a-102g without having a large impact on increasing the total effective absolute permittivity of the material between the bit lines 102a-102g relative to the absolute permittivity of the air gaps 104a-104f. Accordingly, the mutual capacitance between the bit lines 102a-102g may be relatively low.
In some embodiments the apparatus 100 includes a liner material 124 between the electrically insulating material 108 and the bit lines 102a-102g. As a specific, non-limiting example, the liner material 124 may include tantalum or tantalum nitride.
In some embodiments the electrically insulating material 108 includes oxide materials 116 (e.g., silicon dioxide) staggered with (e.g., alternating with) nitride materials 118 (e.g., silicon nitride). In some embodiments an apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, strings of memory cells, and contacts. The low-k dielectric material mechanically supports the copper. The apparatus also includes air gaps between the bit lines. The strings of memory cells extend at least substantially perpendicularly to the bit lines. The contacts electrically connect the strings of memory cells to the bit lines.
Various embodiments according to the method 400 of
At operation 402 the method 400 includes forming bit line trenches 436 in the electrically insulating material 424 on or in the circuitry 426 of the memory device.
Since bit lines 102a-102g (
At operation 404 the method 400 includes forming a first electrically conductive material 112 in the bit line trenches 436.
At operation 406 the method 400 includes removing overlying portions of the first electrically conductive material 112 to expose the underlying electrically insulating material 424 between the bit line trenches 436 filled with the first electrically conductive material 112.
At operation 408 the method 400 includes removing portions of the electrically insulating material 424 to form air gaps 438 between the first electrically conductive material 112 in the bit line trenches 436. Sidewalls of the electrically insulating material 424 and the first electrically conductive material 112 define the air gaps 438. The air gaps 438 extend partially through the electrically insulating material 424, such as through the upper nitride material 434 and the oxide material 432 and into the lower nitride material 434.
At operation 410 the method 400 includes forming a low-k dielectric material 126 to conform to the first electrically conductive material 112.
At operation 412 the method 400 includes forming a subconformal dielectric material 128 to form air gaps 438 between the first electrically conductive materials 112 in the bit line trenches 436. The subconformal dielectric material 128 may be an oxide material or a low-k dielectric material.
At operation 414 the method 400 includes polishing the subconformal dielectric material 128 and the low-k dielectric material 126 to expose the first electrically conductive material 112.
In some embodiments the subconformal dielectric material 128 and the low-k dielectric material 126, in combination with the first electrically conductive material 112, may provide desirable mechanical strength properties to provide sufficient strength to support the structures of the first electrically conductive material 112 (e.g., bit line structures) through manufacturing process operations such as operation 412 and operation 414, which are illustrated in
At operation 416 the method 400 includes recessing the first electrically conductive material 112 in the bit line trenches 436.
As a specific, non-limiting example, a phosphoric-acetic-nitric acid (PAN) chemistry may be used if the first electrically conductive material 112 is tungsten to selectively remove the tungsten without substantially removing the low-k dielectric material 126 or the subconformal dielectric material 128 (e.g., the PAN chemistry may be tuned for oxide selectivity). Using a PAN chemistry process may result in a relatively rough upper surface of the remaining portions of the first electrically conductive material 112, which may contribute to the rough interface 302 illustrated in
At operation 418 the method 400 includes replacing the first electrically conductive material 112 that was removed from within the bit line trenches 436 with a second electrically conductive material 114.
As described above for
In some embodiments replacing the first electrically conductive material 112 that was removed with the second electrically conductive material 114 includes forming a liner material 124 to line the bit line trenches 436, and subsequently filling the lined bit line trenches 436 with the second electrically conductive material 114. In some embodiments forming the liner material 124 includes forming a tantalum liner material. In some embodiments replacing the first electrically conductive material 112 that was removed with the second electrically conductive material 114 includes replacing the first electrically conductive material 112 that was removed with copper. In some embodiments replacing the first electrically conductive material 112 that was removed with copper includes reflowing copper. In some embodiments replacing the first electrically conductive material 112 includes depositing the copper using a PVD process. In some embodiments replacing the first electrically conductive material 112 that was removed with a the second electrically conductive material 114 (e.g., copper) may include forming the second electrically conductive material 114 and recessing the second electrically conductive material 114 to smooth (e.g., planarize) the second electrically conductive material 114. In some embodiments recessing the second electrically conductive material 114 includes performing CMP on the second electrically conductive material 114.
At operation 420 the method 400 includes forming a cap material 440 on the second electrically conductive material 114, the low-k dielectric material 126, and the subconformal dielectric material 128.
As may be seen by inspecting
In some embodiments a method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material over vertical strings of memory cells, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, forming a subconformal dielectric material to form air gaps between the bit line trenches, removing at least a portion of the first electrically conductive material from the bit line trenches, and forming a second electrically conductive material in the bit line trenches to replace the removed first electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material.
In some embodiments a method of manufacturing a memory device includes forming bit line trenches in an electrically insulating material over vertical strings of memory cells of the memory device, forming a first electrically conductive material in the bit line trenches to form bit lines, and removing excess portions of the first electrically conductive material to expose the electrically insulating material between the bit line trenches. The method also includes removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, forming a subconformal dielectric material to form air gaps laterally adjacent to the low-k dielectric material on the first electrically conductive material within the bit line trenches, and removing a portion of the subconformal dielectric material and the low-k dielectric material to expose the first electrically conductive material within the bit line trenches. The method further includes recessing the first electrically conductive material within the bit line trenches, and forming a second electrically conductive material over the first electrically conductive material and within the bit line trenches. The second electrically conductive material is more electrically conductive than the first electrically conductive material.
The microelectronic device structure 500 may also include a stair step structure 520 defining contact regions for connecting access lines 506 to conductive tiers 505 (e.g., conductive layers, conductive plates. The microelectronic device structure 500 may include vertical strings 507 (e.g., vertical strings 130 of
Vertical conductive contacts 511 (e.g., the contacts 132 of
The first select gates 514 may extend horizontally in a first direction (e.g., the X-direction) and may be electrically connected to respective first groups of vertical strings 507 of memory cells 503 at a first end (e.g., an upper end) of the vertical strings 507. The second select gate 510 may be formed in a substantially planar configuration and may be electrically connected to the vertical strings 507 at a second, opposite end (e.g., a lower end) of the vertical strings 507 of memory cells 503.
The bit lines 502 may extend horizontally in a second direction (e.g., in the Y-direction) that is at an angle (e.g., perpendicular) to the first direction in which the first select gates 514 extend. The bit lines 502 may be electrically connected to respective second groups of the vertical strings 507 at the first end (e.g., the upper end) of the vertical strings 507. A first group of vertical strings 507 electrically connected to a respective first select gate 514 may share a particular vertical string 507 with a second group of vertical strings 507 electrically connected to a respective bit line 502. Thus, a particular vertical string 507 may be selected at an intersection of a particular first select gate 514 and a particular bit line 502. Accordingly, the first select gates 514 may be used for selecting memory cells 503 of the vertical strings 507 of memory cells 503.
The conductive tiers 505 (e.g., word line plates) may extend in respective horizontal planes. The conductive tiers 505 may be stacked vertically, such that each conductive tier 505 is electrically connected to all of the vertical strings 507 of memory cells 503, and the vertical strings 507 of the memory cells 503 extend vertically through the stack of conductive tiers 505. The conductive tiers 505 may be electrically connected to or may form control gates of the memory cells 503 to which the conductive tiers 505 are electrically connected. Each conductive tier 505 may be electrically connected to one memory cell 503 of a particular vertical string 507 of memory cells 503.
The first select gates 514 and the second select gates 510 may operate to select a particular vertical string 507 of the memory cells 503 between a particular bit line 502 and the source tier 504. Thus, a particular memory cell 503 may be selected and electrically connected to a bit line 502 by operation of (e.g., by selecting) the appropriate first select gate 514, second select gate 510, and conductive tier 505 that are electrically connected to the particular memory cell 503.
The staircase structure 520 may be configured to provide electrical connection between the access lines 506 and the conductive tiers 505 through the vertical conductive contacts 511. In other words, a particular level of the conductive tiers 505 may be selected via an access line 506 in electrical communication with a respective vertical conductive contact 511 in electrical communication with the particular tier 505.
The bit lines 502 may be electrically connected to the vertical strings 507 through conductive contact structures 534 (e.g., the contacts 132 of
In some embodiments the bit lines 620a-620c may include copper to provide for a relatively high electrical conductivity of the bit lines 620a-620c and thereby provide for a relatively low parasitic resistance of the bit lines 620a-620c. In some embodiments air gaps (not shown) similar to the air gaps 104a-104f of
The memory device 600 includes word lines 622a-622d. The memory device 600 also includes a memory cell array 602, which is similar to the array 120 of memory cells of
By way of specific, non-limiting examples, memory cell 604a may correspond to an intersection between bit line 620a and word line 622a, memory cell 604b may correspond to an intersection between bit line 620a and word line 622b, memory cell 604c may correspond to an intersection between bit line 620a and word line 622c, memory cell 604d may correspond to an intersection between bit line 620a and word line 622d, memory cell 604e may correspond to an intersection between bit line 620b and word line 622a, memory cell 604f may correspond to an intersection between bit line 620b and word line 622b, memory cell 604g may correspond to an intersection between bit line 620b and word line 622c, memory cell 604h may correspond to an intersection between bit line 620b and word line 622d, memory cell 604i may correspond to an intersection between bit line 620c and word line 622a, memory cell 604j may correspond to an intersection between bit line 620c and word line 622b, memory cell 604k may correspond to an intersection between bit line 620c and word line 622c, and memory cell 604l may correspond to an intersection between bit line 620c and word line 622d.
The memory device 600 also includes periphery circuitry 606 electrically connected to the memory cell array 602 via at least the bit lines 620a-620c. The periphery circuitry 606 illustrated in
In some embodiments selection of one of the word lines 622a-622d may be performed by the row decoder 612, while selection of one of the bit lines 620a-620c may be performed by the column decoder 616. By way of non-limiting example, a row address signal and a bank address signal may be supplied to the row decoder 612, while a column address signal and the bank address signal may be supplied to the column decoder 616. Internal commands may also be supplied to the column decoder 616 and the row decoder 612.
The bit lines 620a-620c are electrically connected to the sense amplifier 608. When data is read from the memory cell array 602, data sensed from the one of the bit lines 620a-620c is amplified by the sense amplifier 608, and thereafter transferred to the ECC circuit 614 via local data lines, the transfer gate 610 (e.g., a switch circuit), and main data lines. When data is written to the memory cell array 602, data outputted from the ECC circuit 614 may be transferred to the sense amplifier 608 via the main data lines, the transfer gate 610, and the local data lines, and written to one of the memory cells 604a that is connected to a selected one of the bit lines 620a-620c. A parity bit (e.g., from the ECC circuit 614) may also be written.
In some embodiments an apparatus includes bit lines comprising copper, air gaps between the bit lines, a low-k dielectric material between the bit lines and the air gaps, word lines, and a memory cell array including memory cells corresponding to intersections between the bit lines and the word lines.
In some embodiments the one or more processors 704 may include a central processing unit (CPU) or other processor configured to control the computing system 700. In some embodiments the one or more memory devices 702 include random access memory (RAM), such as volatile data storage (e.g., dynamic RAM (DRAM) static RAM (SRAM), etc.). In some embodiments the one or more non-volatile data storage devices 710 include a hard drive, a solid state drive, Flash memory, erasable programmable read only memory (EPROM), other non-volatile data storage devices, or any combination thereof. In some embodiments the one or more input devices 706 include a keyboard 714, a pointing device 718 (e.g., a mouse, a track pad, etc.), a microphone 712, a keypad 716, a scanner 720, a camera 728, other input devices, or any combination thereof. In some embodiments the output devices 708 include an electronic display 722, a speaker 726, a printer 724, other output devices, or any combination thereof.
The one or more memory devices 702 include the microelectronic device structure 500 of
In some embodiments a computing system includes a memory cell array including memory cells. The computing system also includes bit lines over the memory cell array, the bit lines electrically connected to the memory cells. The bit lines include a first electrically conductive material and a second electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material. The computing system further includes a low-k dielectric material between the bit lines.
As used in the present disclosure, the term “combination” with reference to a plurality of elements may include a combination of all the elements or any of various different subcombinations of some of the elements. For example, the phrase “A, B, C, D, or combinations thereof” may refer to any one of A, B, C, or D; the combination of each of A, B, C, and D; and any subcombination of A, B, C, or D such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.
Terms used in the present disclosure and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including, but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes, but is not limited to,” etc.).
Additionally, if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations.
In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” or “one or more of A, B, and C, etc.” is used, in general such a construction is intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc.
Further, any disjunctive word or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” should be understood to include the possibilities of “A” or “B” or “A and B.”
While the present disclosure has been described herein with respect to certain illustrated embodiments, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications to the illustrated and described embodiments may be made without departing from the scope of the invention as hereinafter claimed along with their legal equivalents. In addition, features from one embodiment may be combined with features of another embodiment while still being encompassed within the scope of the invention as contemplated by the inventor.
This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application Ser. No. 63/266,024, filed Dec. 27, 2021, the disclosure of which is hereby incorporated herein in its entirety by this reference.
Number | Date | Country | |
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63266024 | Dec 2021 | US |