Patent Application
20160148883
Disclosed embodiments relate to bond pads for integrated circuits.
Integrated circuits (IC) devices are usually fabricated on a semiconductor wafer which has a plurality of IC device die each including a plurality of bond pads on its top surface that connect to various nodes in the device, such as for signal input, signal output and power supply nodes. The bond pads are generally connected by a bond wire or other electrically conductive structure to permit utilization of the IC die. Known methods for connecting an IC device to a lead frame or other support include wire bonding, Tape Automated Bonding (TAB), Controlled Collapse Chip Connection (C4) or bump bonding, and the use of electrically conductive adhesives.
To provide a reliable and low resistance attachment to the bond pad surface, such as by bond wires, some packaging technologies have used multi-layered bond pads having a top metal layer that is both electrically conductive and resistant to oxidation to provide high reliability (good corrosion performance) and high performance (low resistance), such as for wire bonding to the bond pads. One such bond pad arrangement deposits a dielectric passivation layer(s) over an oxidizable uppermost metal interconnect layer such as copper or aluminum, and then forms a trench including dielectric sidewalls from the passivation layer. A barrier layer comprising a refractory metal (e.g., Ta, TaN or Ti) is then deposited that lines the passivation sidewalls which provides good adhesion to the passivation material. A multi-layer metal stack is formed on the barrier layer which can comprise palladium (Pd) as the final (top) layer on a nickel layer over the uppermost metal interconnect layer to provide a stable surface for wire bonding. Pd being a platinum group metal has a low propensity for oxidation and is a good outer capping layer for the bond pad to prevent chemical attack of the oxidizable uppermost metal interconnect layer material thereunder.
This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.
Disclosed embodiments recognize although known multi-layer bond pad stacks for integrated circuits (IC) devices including palladium (Pd) on nickel (Ni) on an oxidizable uppermost metal interconnect layer material such as copper or aluminum generally provide high reliability (low corrosion susceptibility leading to good corrosion performance) and high performance (low resistance), Pd deposition and layer definition is generally an expensive process. Moreover, a barrier layer generally comprising a refractory metal is needed to line the sidewalls of the passivation trench to provide good adhesion for the Ni layer which does not directly adhere well to the passivation material(s).
Disclosed embodiments recognize ruthenium (Ru) provides strong adhesion to conventional passivation dielectrics such as silicon oxide and/or silicon nitride, which enables bond pads for IC devices having Ru as the metal to be in direct contact with the passivation sidewalls of the trench and the bond pad areas of the uppermost metal interconnect layer. This disclosed arrangement eliminates the need for a conventional refractory metal comprising barrier layer lining the passivation sidewalls of the bond pads. Moreover, Ru is recognized to have an electrically conductive oxide which reduces contact resistance to the Ru layer as compared to Pd when surface oxidized to PdO which has significantly less electrical conductivity.
Replacing Pd with Ru on the bond pads is recognized to provide other advantages too. Disclosed embodiments recognize Pd can getter organics in the surrounding ambient so that airborne organics can attach thereon, which can result in adhesion problems to Pd, such as between bond wires and the top surface of the Pd layer. Pd Chemical Mechanical Polishing/Planarizing (CMP) can also generally be difficult to achieve since Pd has a low corrosion susceptibility as compared to Ru, generally requiring a custom-made CMP polishing slurry with the limitation of relatively low Pd polishing rate as compared to more standard metal CMP processes, such as copper CMP.
Ru is also recognized to have a hardness 7 times (˜700%) higher than Pd rendering it less susceptible to cracking, and such as during the bond wire attachment process. Moreover, Ru has about a 40% lower bulk electrical resistance as compared to Pd translating into improved electrical signal transmission and improved matching with copper or gold bond wires which are commonly used wire materials for connection to bond pads.
Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
The substrate can comprise silicon, silicon-germanium, or other semiconductor materials including III-V or II-VI materials. The uppermost metal interconnect layer can comprise copper or aluminum, or alloys thereof.
Step 102 comprises depositing a Ru layer directly on the dielectric sidewalls of the trench and directly on the metal bond pad area. As used herein, the Ru layer being “directly on the metal bond pad area” includes the conventional contact arrangement where the uppermost metal interconnect layer has a native oxide layer formed at room temperature that is about 2 nm thick, such as primarily Cu2O in the case of copper. The direct Ru attachment removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer can be sputter deposited using a Ru sputtering target for sputter coating on the substrate (e.g., wafer) surface. the Ru sputter can be performed at a relatively low temperature, such as 25° C. to 300° C. Due to the about 10× lower cost of Ru as compared to Pd, Ru targets are about 35% to 55% lower cost for when compared to Pd targets. The Ru layer may be a Ru alloy, such as including Zr or another transition metal from 1 ppm up to 10 wt. %, such as 0.5 wt. % to 5 wt. %. The thickness of the Ru layer is generally 0.05 μm to 2 μm, such as from 0.2 μm to 2 μm.
Step 103 comprises patterning the Ru layer to provide a bond pad surface for the plurality of bond pads for bonding to the plurality of bond pads. CMP can be used to remove overburden Ru above the top of the passivation layer(s) while preserving the Ru within the bond pad. For example, an aqueous slurry for polishing Ru can comprise about 0.5 wt. % to about 12 wt. % abrasive particles, such as comprising alumina, silica, cerium oxide or titania, at least one oxidizer in a concentration from 0.05 M to 1 M such as hydrogen peroxide, and a pH range from about 1 to 8.5.
Plugs 121 are shown coupling M3 to M2, plugs 122 coupling M2 to Ml, and plugs 123 coupling M1 to node 109a shown as a diffusion (e.g., n+ or p+) and to 109b shown as a gate electrode node (circuitry not shown, with 109b being a contact to a metal oxide semiconductor (MOS) gate 112 on a gate dielectric 111 on the semiconductor surface of a substrate 108, such as a silicon comprising surface in one embodiment. The plugs 121, 122, 123 and 124 can all comprise tungsten, or other suitable electrically conductive plug material.
M4 comprises an oxidizable metal material such as copper shown damascened into ILD4 framed/lined by a refractory metal comprising barrier layer 127. For example, the barrier layer 127 can comprise Ta, TaN, Ti or TiN. M4 can also comprise aluminum. Metal bond pad areas 141 and 142 are shown coupled by plug 124 though dielectric layer 133 and ILD3 to M3, and from M3 all the way to features on the semiconductor surface, such as from metal bond pad area 141 to node 109b.
IC device 200 includes at least one passivation layer(s) which defines a trench over the metal bond pad areas 141 and 142, with the passivation shown in
IC devices having disclosed bond pads including a layer of Ru directly on the dielectric sidewalls of the trench and directly on the metal bond pad area of the uppermost metal interconnect layer will generally achieve the similar or better performance and reliability as known Pd on Ni. Like Pd, Ru is recognized to be a platinum group metal with low oxidation potential. Ru has about a 40% lower bulk resistivity compared to Pd. Utilizing a Ru layer in place of a Pd layer on Ni layer on a barrier layer reduces back end of the line (BEOL) processing cost and cycle time. Moreover, as noted above, Ru is expected to provide better bond adhesion as compared to Pd due to a reduced tendency to getter organics from the surrounding ambient, resulting in an improvement in bond strength and a resulting reliability improvement.
Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different semiconductor integrated circuit (IC) devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die, such as PoP configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.
Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.
Under 35 U.S.C. §120, this continuation application claims priority to and benefits of U.S. patent application Ser. No. 14/278,613, filed on May 15, 2014, the entirety of which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14278613 | May 2014 | US |
| Child | 15010022 | US |
