Patent Application
20240321789
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-045023, filed on Mar. 22, 2023; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a bonding-type interconnection member.
A structure is known in which two chips are bonded by bonding metals.
According to one embodiment, a bonding-type interconnection member includes a first substrate; a first interconnection portion stacked on the first substrate and including a first insulating layer, a first interconnection layer provided in the first insulating layer, and a first connection hole reaching the first interconnection layer from a surface of the first insulating layer; a second substrate facing the first interconnection portion in a first direction; a bonding metal portion provided between the first connection hole and the second substrate in the first direction; a first conductive film provided in the first connection hole and in contact with the first interconnection layer on a bottom surface of the first connection hole; and a second conductive film provided between the first conductive film and the bonding metal portion, and in contact with the first conductive film and the bonding metal portion, the first conductive film being made of a material different from a material of the second conductive film and a material of the bonding metal portion.
Hereinafter, embodiments will be described with reference to the drawings.
The drawings are schematic or conceptual. A relationship between a thickness and a width of each portion, a ratio of sizes between portions, and the like are not necessarily the same as the actual ones. Even if the same portions are shown, dimensions and ratios may be shown differently from each other in the drawings.
Same components are denoted by same reference numerals.
As shown in
The first chip 100 includes a first substrate 10. The first substrate 10 has a first surface 11 and a second surface 12 located on an opposite-side surface from the first surface 11 in the first direction Z. The first substrate 10 is, for example, a silicon substrate.
The second chip 200 includes a second substrate 20. The second substrate 20 has a third surface 21 facing the first surface 11 of the first substrate 10 in the first direction Z, and a fourth surface 22 located on an opposite-side surface from the third surface 21 in the first direction Z. The second substrate 20 is, for example, a silicon substrate.
The first chip 100 includes a first interconnection portion 30 stacked on the first substrate 10. The first interconnection portion 30 is provided on the first surface 11 of the first substrate 10. In the first direction Z, the first interconnection portion 30 is located between the first substrate 10 and the second substrate 20. The first interconnection portion 30 includes a first insulating layer 33 and first interconnection layers 31 provided in the first insulating layer 33. The first interconnection layer 31 is made of, for example, a material mainly containing copper. Although
The first insulating layer 33 has a surface 33a facing the second substrate 20 in the first direction Z. The first interconnection portion 30 has first connection holes 32 reaching the first interconnection layers 31 from the surface 33a of the first insulating layer 33. The first connection hole 32 has an opening on a surface 33a side of the first insulating layer 33 and a bottom surface on a first interconnection layer 31 side. The first interconnection portion 30 has, for example, a plurality of the first connection holes 32. A plurality of the bonding metal portions 50 are arranged in at least one of the second direction X and the third direction Y corresponding to positions of the plurality of first connection holes 32. The bonding metal portion 50 is provided between the first connection hole 32 and the second substrate 20 in the first direction Z.
The first chip 100 further includes first conductive films 61 provided in the first connection holes 32 and in contact with the first interconnection layers 31 on the bottom surfaces of the first connection holes 32. The first conductive film 61 is provided to be continuous with the surface 33a of the first insulating layer 33 and a side surface and the bottom surface of the first connection hole 32. The first conductive film 61 includes a first portion 61a located in the first connection hole 32 and a second portion 61b located on the surface 33a of the first insulating layer 33.
The first chip 100 further includes second conductive films 71 provided between the first conductive films 61 and the bonding metal portions 50 and in contact with the first conductive films 61 and the bonding metal portions 50. A plurality of the second conductive films 71 are separated from each other and provided under the plurality of bonding metal portions 50.
The bonding metal portion 50 is electrically connected to the first interconnection layer 31 via the first conductive film 61 and the second conductive film 71. The bonding metal portion 50 includes a first metal portion 51a located in the first connection hole 32 and a second metal portion 51b facing the second portion 61b of the first conductive film 61.
The second conductive film 71 is in contact with the first conductive film 61 and the bonding metal portion 50 between the second metal portion 51b of the bonding metal portion 50 and the second portion 61b of the first conductive film 61. The second conductive film 71 is in contact with the first conductive film 61 and the bonding metal portion 50 between side surfaces of the first metal portion 51a of the bonding metal portion 50 and the first portion 61a of the first conductive film 61.
In
The first conductive film 61 is made of a material different from a material of the second conductive film 71 and a material of the bonding metal portion 50. Here, the material represents a material mainly constituting each member. For example, the bonding metal portion 50 mainly contains gold, the first conductive film 61 mainly contains titanium nitride, and the second conductive film 71 mainly contains palladium or titanium. The second conductive film 71 may be a stacked film of a palladium film and a titanium film.
As described later, the second conductive film 71 functions as a seed layer when the bonding metal portion 50 is formed by a plating method, and after the bonding metal portion 50 is precipitated, a process of removing an unnecessary portion of the second conductive film 71 on the surface 33a of the first insulating layer 33 is performed. For example, when misalignment occurs between the bonding metal portion 50 and the first connection hole 32 located on the left side in
According to the embodiment, by previously forming the first conductive film 61 in contact with the first interconnection layer 31 in the first connection hole 32 with a material different from that of the second conductive film 71, the first conductive film 61 in contact with the first interconnection layer 31 can reliably remain in the first connection hole 32 even after an etching process of the second conductive film 71. Accordingly, the first interconnection layer 31 can be electrically connected to the bonding metal portion 50 via the first conductive film 61. As a result, reliability of the bonding-type interconnection member 1 can be improved.
According to the embodiment, as shown in the bonding metal portion 50 located on the left side in
The second chip 200 may have the same configuration as the first chip 100. For example, the second chip 200 includes a second interconnection portion 40 stacked on the second substrate 20. The second interconnection portion 40 is provided on the third surface 21 of the second substrate 20. The second interconnection portion 40 is located between the first interconnection portion 30 and the second substrate 20 in the first direction Z. The second interconnection portion 40 includes a second insulating layer 43 and second interconnection layers 41 provided in the second insulating layer 43. The second interconnection layer 41 is made of, for example, a material mainly containing copper. Although
The second insulating layer 43 has a surface 43a facing the first interconnection portion 30 in the first direction Z. The second interconnection portion 40 has second connection holes 42 reaching the second interconnection layers 41 from the surface 43a of the second insulating layer 43. The second connection hole 42 has an opening on a surface 43a side of the second insulating layer 43 and a bottom surface on a second interconnection layer 41 side. The second interconnection portion 40 has, for example, a plurality of the second connection holes 42 corresponding to positions of the plurality of bonding metal portions 50. The bonding metal portion 50 is provided between the first connection hole 32 and the second connection hole 42 in the first direction Z.
The second chip 200 further includes third conductive films 62 provided in the second connection holes 42 and in contact with the second interconnection layers 41 on the bottom surfaces of the second connection holes 42. The third conductive film 62 is provided to be continuous with the surface 43a of the second insulating layer 43 and a side surface and the bottom surface of the second connection hole 42. The third conductive film 62 includes a third portion 62a located in the second connection hole 42 and a fourth portion 62b located on the surface 43a of the second insulating layer 43.
The second chip 200 further includes fourth conductive films 72 provided between the third conductive films 62 and the bonding metal portions 50 and in contact with the third conductive films 62 and the bonding metal portions 50. A plurality of the fourth conductive films 72 are separated from each other and provided on the plurality of bonding metal portions 50.
The bonding metal portion 50 is electrically connected to the second interconnection layer 41 via the third conductive film 62 and the fourth conductive film 72. The bonding metal portion 50 includes a third metal portion 52a located in the second connection hole 42 and a fourth metal portion 52b facing the fourth portion 62b of the third conductive film 62.
The fourth conductive film 72 is in contact with the third conductive film 62 and the bonding metal portion 50 between the fourth metal portion 52b of the bonding metal portion 50 and the fourth portion 62b of the third conductive film 62. The fourth conductive film 72 is in contact with the third conductive film 62 and the bonding metal portion 50 between side surfaces of the third metal portion 52a of the bonding metal portion 50 and the third portion 62a of the third conductive film 62.
The first interconnection layer 31 of the first chip 100 is electrically connected to the second interconnection layer 41 of the second chip 200 via the first conductive film 61, the second conductive film 71, the bonding metal portion 50, the fourth conductive film 72, and the third conductive film 62.
As will be described later, one bonding metal portion 50 is formed by integrating a first bonding metal portion 51 provided on a first chip 100 side and a second bonding metal portion 52 provided on a second chip 200 side by metal diffusion bonding by applying heat and a force.
Next, a manufacturing method of the bonding-type interconnection member 1 according to the first embodiment will be described with reference to
As shown in
After the first connection hole 32 is formed, as shown in
After the first conductive film 61 is formed, as shown in
After the second conductive film 71 is formed, the first bonding metal portion 51 is formed. As shown in
After the first bonding metal portion 51 is formed, the resist mask 91 is removed. By the removal of the resist mask 91, as shown in
As shown in
The resist mask 91 shown in
When the positional deviation occurs in the opening 91a2, as shown in
According to the embodiment, by previously forming the first conductive film 61 in contact with the first interconnection layer 31 in the first connection hole 32 with a material different from that of the second conductive film 71, the first conductive film 61 in contact with the first interconnection layer 31 can reliably remain in the first connection hole 32 even after the etching process of the second conductive film 71. When the opening 91a2 of the resist mask 91 is deviated to the right side, in the second metal portion 51b of the first bonding metal portion 51, a width (a width in the second direction X) of the other portion 51b2 extending to the right side opposite to the portion 51b1 is larger than the width (the width in the second direction X) of the portion 51b1. Therefore, the second conductive film 71 can remain between the other portion 51b2 and the second portion 61b of the first conductive film 61. Accordingly, the etchant does not enter the first connection hole 32 from the other portion 51b2 side, and the second conductive film 71 can remain between the first metal portion 51a of the first bonding metal portion 51 and the first portion 61a of the first conductive film 61 on a side surface of the first connection hole 32 on the right side. Accordingly, even when the positional deviation between the first bonding metal portion 51 and the first connection hole 32 occurs, the first interconnection layer 31 and the first bonding metal portion 51 can be electrically connected via the first conductive film 61 and the second conductive film 71 on a side in a direction to which the position is deviated (the right side in this example).
The second chip 200 can also be formed by the same process as the first chip 100 described above. In the second chip 200, the third conductive film 62 is also made of a material different from the material of the fourth conductive film 72 and the material of the bonding metal portion 50. For example, the bonding metal portion 50 mainly contains gold, the third conductive film 62 mainly contains titanium nitride, and the fourth conductive film 72 mainly contains palladium or titanium. Accordingly, in the second chip 200, the third conductive film 62 in contact with the second interconnection layer 41 can also reliably remain in the second connection hole 42 even after an etching process of the fourth conductive film 72. Accordingly, the second interconnection layer 41 can be electrically connected to the bonding metal portion 50 via the third conductive film 62 and the fourth conductive film 72.
After the first chip 100 and the second chip 200 are formed, the first bonding metal portion 51 of the first chip 100 and the second bonding metal portion 52 of the second chip 200 face each other and are brought into contact with each other. Thereafter, heat and a force are applied to diffuse metals (in the example, gold) of the first bonding metal portions 51 and the second bonding metal portions 52, and the first bonding metal portions 51 and the second bonding metal portions 52 are bonded.
As shown in
Due to the pressing force during the bonding of the first chip 100 and the second chip 200, the stress of the first conductive film 61 itself formed in the first connection hole 32, the thermal stress in the subsequent process, or the like, it is considered that cracks may occur particularly in a portion of the first conductive film 61 located at a corner of the bottom surface of the first connection hole 32. As described above, even when the gap is formed between the portion 51b1 of the first bonding metal portion 51 and the second portion 61b of the first conductive film 61, the gap is closed when the first chip 100 and the second chip 200 are bonded. Therefore, it is possible to prevent abnormal oxidation of the first interconnection layer 31 through cracks formed in the first conductive film 61 by heating during the bonding of the first chip 100 and the second chip 200.
In the bonding-type interconnection member 2 according to the second embodiment, the first substrate 10 has a first through-hole 13, and the first interconnection portion 30 has a first interconnection portion through-hole 35. The first through-hole 13 and the first interconnection portion through-hole 35 extend in the first direction Z and are continuous with each other in the first direction Z. The second substrate 20 has a second through-hole 23, and the second interconnection portion 40 has a second interconnection portion through-hole 45. The second through-hole 23 and the second interconnection portion through-hole 45 extend in the first direction Z and are continuous with the first interconnection portion through-hole 35 and the first through-hole 13 in the first direction Z.
For example, a charged particle beam passes through the second through-hole 23, the second interconnection portion through-hole 45, the first interconnection portion through-hole 35, and the first through-hole 13. By bonding the two chips (the first chip 100 and the second chip 200) each having the through-holes, the bonding-type interconnection member 2 having deep through-holes, which is difficult to be formed in a single chip, can be implemented.
The bonding-type interconnection member 2 further includes fifth conductive films 81 provided on side surfaces of the first interconnection portion through-hole 35 and sixth conductive films 82 provided on side surfaces of the second interconnection portion through-hole 45.
The side surfaces of the first interconnection portion through-hole 35 are covered with the fifth conductive films 81, and the first insulating layer 33 of the first interconnection portion 30 is not exposed on the side surfaces of the first interconnection portion through-hole 35. The side surfaces of the second interconnection portion through-hole 45 are covered with the sixth conductive films 82, and the second insulating layer 43 of the second interconnection portion 40 is not exposed on the side surfaces of the second interconnection portion through-hole 45. Accordingly, under a usage environment, during preparation for usage, or during storage of the bonding-type interconnection member 2, moisture absorption to side surfaces of the first insulating layer 33 and side surfaces of the second insulating layer 43 can be prevented, and oxidation of the first interconnection layers 31 and the second interconnection layers 41 can be prevented. As a result, reliability of the bonding-type interconnection member 2 can be improved.
Charging of the side surfaces of the first insulating layer 33 and the side surfaces of the second insulating layer 43 can be prevented, and abnormal deflection of the charged particle beam can be prevented by the fifth conductive films 81 and the sixth conductive films 82.
When the first conductive film 61 is formed, the fifth conductive film 81 can be formed continuously with the first conductive film 61 using the same material as that of the first conductive film 61. When the third conductive film 62 is formed, the sixth conductive film 82 can be formed continuously with the third conductive film 62 using the same material as that of the third conductive film 62.
The first chip 100 and a second chip 300 are bonded via the bonding metal portions 50. The second chip 300 includes the second substrate 20. An interconnection portion is stacked only on the first substrate 10 of the first chip 100, and is not stacked on the second substrate 20 of the second chip 300. The second substrate 20 has the second through-hole 23 continuous with the first interconnection portion through-hole 35 and the first through-hole 13. The second bonding metal portions 52 are provided on the third surface 21 of the second substrate 20.
A first electrode film 83 and a second electrode film 84 are provided on side surfaces of the second through-hole 23 of the second substrate 20. The first electrode film 83 and the second electrode film 84 face each other and are spaced apart from each other in the second direction X, and are not connected in the second through-hole 23.
Lower end portions of the first electrode film 83 and the second electrode film 84 are connected to the second bonding metal portions 52. Each of the first electrode film 83 and the second electrode film 84 is electrically connected to the first interconnection layer 31 via the bonding metal portion 50, the second conductive film 71, and the first conductive film 61. The first interconnection layer 31 electrically connected to the first electrode film 83 and the first interconnection layer 31 electrically connected to the second electrode film 84 are not electrically connected, and different potentials can be applied to the first electrode film 83 and the second electrode film 84. Accordingly, a charged particle beam passing through the second through-hole 23 can be deflected.
For example, when the second substrate 20 has conductivity such as a silicon substrate, insulating films 85 are provided between the first electrode film 83 and the second substrate 20 and between the second electrode film 84 and the second substrate 20. When the second substrate 20 is an insulating substrate, the first electrode film 83 and the second electrode film 84 may be directly formed on the second substrate 20.
For example, the plurality of bonding metal portions 50 are arranged in the second direction X and the third direction Y. A plurality of the second conductive films 71 are separated from each other and provided under the plurality of bonding metal portions 50.
The first conductive films 61 electrically connect the plurality of bonding metal portions 50 to each other via the second conductive films 71. In the example shown in
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-045023 | Mar 2023 | JP | national |
