The present invention is directed to nanostructures. More particularly, the invention provides bulk nanohole structures. Merely by way of example, the invention has been applied to thermoelectric devices. However, it would be recognized that the invention has a much broader range of applicability, including but not limited to use in transistor, solar power converter, battery electrodes and/or energy storage, catalysis, and/or light emitting diodes.
Nanohole and nanomesh devices have been shown to have good thermoelectric figures of merit ZT. ZT=S2σ/k, where S is the material's thermopower, σ is the electrical conductivity, and k is the thermal conductivity. These devices have been formed in thin silicon-on-insulator epitaxial layers or formed from arrays of nanowires, and result in nanoscale structures in thin films that are very small in physical size. For example, some conventional silicon nanoholes have been fabricated from a thin silicon film of 10-1000 nm within a conventional silicon wafer, whereby the remainder of the silicon wafer that is about 500 μm thick is etched and discarded. In another example, the resulting conventional structures are thin films and resemble ribbons, which have been shown to be microns wide and microns long, tens to hundreds of nanometers thick, with 1-100 nm diameter holes within. These conventional structures demonstrate the ability of closely-packed nanostructures to affect phonon thermal transport by reducing thermal conductivity while not affecting electrical properties greatly, thereby improving thermoelectric efficiency ZT.
Hence, it is highly desirable to improve techniques of nanohole devices.
The present invention is directed to nanostructures. More particularly, the invention provides bulk nanohole structures. Merely by way of example, the invention has been applied to thermoelectric devices. However, it would be recognized that the invention has a much broader range of applicability, including but not limited to use in transistor, solar power converter, battery electrodes and/or energy storage, catalysis, and/or light emitting diodes.
According to one embodiment, an array of nanoholes includes a plurality of nanoholes. Each of the plurality of nanoholes corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 μm. Each of the plurality of nanoholes corresponds to a cross-sectional area associated with a distance across, and the distance across ranges from 5 nm to 500 nm. Each of the plurality of nanoholes is separated from at least another nanohole selected from the plurality of nanoholes by a semiconductor material associated with a sidewall thickness, and the sidewall thickness ranges from 5 nm to 500 nm.
According to another embodiment, a structure including an array of nanoholes includes a semiconductor substrate with a plurality of nanoholes. The semiconductor substrate includes a first surface, a second surface opposite to the first surface, a third surface extending from the first surface towards the second surface, and a fourth surface extending from the first surface towards the second surface. Each of the plurality of nanoholes corresponds to a first end at the first surface and a second end. Additionally, the structure includes a first thermal and electrical contact material coupled to the third surface, and a second thermal and electrical contact material coupled to the fourth surface. Each of the plurality of nanoholes corresponds to a cross-sectional area associated with a distance across, and the distance across ranges from 5 nm to 500 nm. Each of the plurality of nanoholes is separated from at least another nanohole selected from the plurality of nanoholes by a semiconductor sidewall associated with a sidewall thickness. The semiconductor sidewall is a part of the semiconductor substrate, and the sidewall thickness ranges from 5 nm to 500 nm.
According to yet another embodiment, a method for forming an array of nanoholes includes providing a semiconductor substrate including a first surface and forming a mask on the first surface. The mask includes mask regions separated by corresponding mask holes, and portions of the first surface are exposed within the corresponding mask holes. Additionally, the method includes etching the semiconductor substrate through at least the exposed portion of the first surface to form at least nanoholes. Each of the nanoholes corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 μm. Each of the nanoholes corresponds to a cross-sectional area associated with a distance across ranging from 5 nm to 500 nm. Each of the nanoholes is separated from at least another of the nanoholes by a semiconductor sidewall associated with a sidewall thickness ranging from 5 nm to 500 nm, and the semiconductor sidewall is a part of the semiconductor substrate.
According to yet another embodiment, a method for forming a structure including an array of nanoholes includes providing a semiconductor substrate including a first surface and forming a mask on the first surface. The mask includes mask regions separated by corresponding mask holes, and portions of the first surface are exposed within the corresponding mask holes. Additionally, the method includes etching the semiconductor substrate through at least the exposed portion of the first surface to form at least nanoholes. Each of the nanoholes corresponds to a first end at the first surface and a second end. Each of the nanoholes corresponding to a cross-sectional area associated with a distance across ranging from 5 nm to 500 nm. Each of the nanoholes is separated from at least another of the nanoholes by a semiconductor sidewall associated with a sidewall thickness ranging from 5 nm to 500 nm, and the semiconductor sidewall is a part of the semiconductor substrate. Also, the method includes etching the semiconductor substrate to form at least a first trench and a second trench, forming a first thermal and electrical contact within the first trench with the semiconductor substrate, and forming a second thermal and electrical contact within the second trench with the semiconductor substrate.
Depending upon the embodiment, one or more benefits may be achieved. These benefits and various additional objects, features, and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow.
The present invention is directed to nanostructures. More particularly, the invention provides bulk nanohole structures. Merely by way of example, the invention has been applied to thermoelectric devices. However, it would be recognized that the invention has a much broader range of applicability, including but not limited to use in transistor, solar power converter, battery electrodes and/or energy storage, catalysis, and/or light emitting diodes.
To improve techniques of nanohole devices, it is of interest to transform nanohole structures into bulk electronic devices. These devices may be transistors, thermoelectrics, or other electronic devices. For example, a bulk nanohole thermoelectric device used for power generation should transport a significant amount of electric current from one electrode to another, where a temperature gradient is applied to the thermoelectric material and the Seebeck effect is employed to generate a gradient in voltage and in turn the flow of electrical current. In another example, a bulk nanohole thermoelectric device used for refrigeration should carry an appreciable amount of heat with an applied electric current by way of the Peltier effect. In both of these configurations for thermoelectric devices, ZT of the thermoelectric material is one indicator of the material's efficiency in either converting heat to electricity (e.g., thermopower) or pumping heat with electricity.
In certain embodiments, in a bulk nanohole thermoelectric device, electrodes should be placed on either ends of the thermoelectric material in order to collect a current from the thermoelectric material or transmit a current through the thermoelectric material. For example, these electrodes should be made such that the electrodes make low resistance electrical and thermal contact to the thermoelectric material with high ZT, and furthermore allow each thermoelectric unit of p-type or n-type semiconductor thermoelectric material (e.g., each thermoelectric leg) to be wired together with one or more other thermoelectric units and/or the external circuitry.
In some embodiments, the interesting applications for bulk nanohole thermoelectric device include heat energy scavenging for powering sensors, Peltier cooling of electronics hot-spots, and waste-heat recovery from exhaust and other heat sources, among others. According to one embodiment, in order for a bulk nanohole thermoelectric device to be usefully applied to one or more of these applications, as an example, not only should suitable electrodes be made on the thermoelectric material, but an appreciable amount of the thermoelectric material itself should be fabricated to meet the geometrical and electrical specifications of the application. According to another embodiment, in thermoelectric power generation from a heat source using the Seebeck effect, enough volume of thermoelectric material should be present between a hot-junction and a cold junction (e.g., in a counter-flow gas phase heat exchanger) so as to allow both an appreciable temperature gradient to evolve across thermoelectric legs and to allow enough current to be carried due to the temperature-induced voltage.
In more detail, a thermoelectric material fabricated with small outer dimensions, such as the conventional structures demonstrated incorporating nanoholes with relative short lengths, usually suffer from very high current densities that may preclude their use in a thermoelectric application. Furthermore, such thermoelectric structure often may not generate sufficient power or heat pumping that is applicable or cost-effective. Hence, the ability to process nanostructures for making high-performance thermoelectric devices would have signification cost advantages, if the nanostructures are fabricated with methods that are compatible with the processing of silicon and other semiconductor wafers, according to some embodiments.
For example, one may consider a thin-film thermoelectric material whose dimensions laterally in the x-y plane (e.g., in the plane of a semiconductor wafer) are on the order of hundreds of microns to millimeters, and whose dimensions vertically (e.g., cross the plane of a semiconductor wafer) are only 10-1000 nm. In another example, the thermoelectric generation power density, δ, of such a device in a load-matched condition, where the temperature gradient is applied in the z direction, is:
where I is the current in the sample-load circuit, Rinternal is the internal resistance of the thermoelectric material, Rload is the resistance of the load, R is the sum of Rinternal and Rload. Additionally, A is the x-y cross-sectional area of the thermoelectric material that is orthogonal to the temperature gradient applied in the z direction, V is the voltage generated by the thermoelectric material, and ρ is the electrical resistivity of the thermoelectric material. Moreover, Lx, Ly, and Lz are the sample dimensions in the x, y, and z directions respectively.
As shown in Equation 1, for per unit area of power-generation thermoelectric material sample, the thermoelectric power can increase if the voltage generated by the sample is larger or if the electrical resistance of the sample is lower according to one embodiment. For example, the voltage generated by the sample can be increased by selecting a thermoelectric material with a larger Seebeck coefficient S (e.g., S is equal to dV/dT). In another example, the electrical resistance of the sample can be lowered by decreasing the sample length Lz along the axis of the temperature gradient and/or selecting a thermoelectric material with lower resistivity.
According to another embodiment, the total amount of power P produced by the thermoelectric material sample, rather than the power density, is then:
As shown in Equation 2, for example, the thermoelectric sample that is larger in lateral x and y dimensions can produce more power, because there would be more thermoelectric material participating in the generation of voltage from an applied temperature gradient, and therefore more current generated. In another example, the thermoelectric power generation becomes problematic if a thermoelectric device is made from a thin thermoelectric film where the direction of thermal and electrical transport is in the x-y plane of the thin film, and not in the z direction.
For a conventional thermoelectric thin film with nanoholes within it, the temperature gradient often needs to be applied in a direction that is orthogonal to the z direction of the thin film so as to take advantage of the beneficial effects of the nanohole structure within the material. But, in such an arrangement, a very small amount of thermoelectric material usually can contribute to the thermoelectric conversion. For example, if the temperature gradient is applied in the y direction, referring to Equation 2, the transverse area (e.g., the cross-sectional area that is exposed to a temperature gradient through which a current may flow) is no longer Lx×Ly, but instead is equal to Lx×Lz where z is the cross-plane direction (e.g., thickness direction) of the thin film. If the z height of the thin film is only about 100 nm and the lateral dimensions are as large as several millimeters, the thermoelectric conversion would be significantly restricted in terms of the amount of electric power it can generate according to one embodiment. In another embodiment, since P is linearly proportional to the transverse area, going from a thin film thicknesses of 100 nm to greater than 100 μm would increase power generation by about 1000 times.
Therefore, when fabricating thermoelectric nanostructures from a finite wafer of material or the like, it is desirable to transform as much of the starting wafer material as possible into the thermoelectric nanostructures according to some embodiments. For example, since the commercial performance, and thus usefulness, of a power generation thermoelectric device is governed by its cost-per-Watt, it is beneficial to process a piece of material in such a fashion that maximizes its use as a thermoelectric material, because most of the two-dimensional semiconductor fabrication processes or the like usually cost about the same amount regardless of the thickness of the material being processed.
Specifically, some conventional silicon nanoholes have been fabricated from a thin silicon film of 10-1000 nm within a conventional silicon wafer, whereby the remainder of the silicon wafer that is about 500 μm thick is etched and discarded. As an example, such a resulting nanohole thermoelectric structure can possibly generate only about 1 watt of power per 8-inch silicon wafer in a temperature gradient of about 250 K. In another example, if a nanohole thermoelectric structure is made to utilize the entire thickness of the 500 μm wafer, the thermoelectric structure can increase the power generation by 500-50,000 times, or would generate 500-50,000 watts of power per wafer. In yet another example, at typical fabrication costs in semiconductor IC, MEMS, or PV processing of $5-$1,000 per wafer, using only a thin film of a silicon wafer to make a nanohole structure can be prohibitively expensive for power generation, but in contrast, using the entire wafer thickness to make a nanohole structure can result in costs-per-watt of $0.50 or less that is needed for commercial adoption according to some embodiments.
According to certain embodiment, it is therefore important to utilize far greater thicknesses of thermoelectric material than conventional technology in order to achieve significant commercial applicability. For example, it is highly desirable to improve techniques for the formation of very large or bulk nanohole structures comprising arrays of ultra-long nanoholes in a silicon wafer or other semiconductor materials (e.g., semiconductor materials that are less expensive and/or less toxic). In another example, it is also highly desirable to transform these bulk nanohole structures into thermoelectric legs by forming corresponding conductive patches at two sides of each array of ultra-long nanohole structures.
In one embodiment, the method for making one or more arrays of nanoholes in a substrate includes the following sequential processes (a) through (d):
As shown in
As shown in
As shown in
In yet another embodiment, the nanoholes 120 form an array of nanoholes 120. For example, the density of the array of nanoholes 120 has a hole density characterized by separations of the holes 114 (e.g., the pitch sizes). For example, the average pitch size is about 70 nm. In another example, the cross-sectional areas of corresponding nanoholes 120 determine the porosity of the resulting substrate structure as shown in
According to some embodiments, the anisotropic wet etching process can create roughened and/or porous sidewall surfaces for the nanoholes 120 and therefore reduce the thermal conductivity. According to certain embodiments, the nanoholes 120 are formed by applying an anisotropic etching process with an etchant solution that includes HF, AgNO3, and H2O. For example, the molar concentration of HF in the etchant solution varies from 2M to 10M. In another example, the molar concentration of AgNO3 in the etchant solution varies from 0.001M to 0.5M. In yet another example, other molar concentrations vary depending on the etching parameters desired. In yet another embodiment, KNO3 is added to the etchant solution. In one example, the KNO3 is added to the etchant solution after a certain time period of initial etching without KNO3 in the etchant solution. In another example, KNO3 is added to the etchant solution all at once. In yet another example, KNO3 is added to the etchant solution continuously at a predetermined rate. In yet another example, KNO3 is added to the etchant solution to maintain the proper balance between Ag and Ag+ to control the etching rate, the anisotropy, and/or other etch characteristics. In yet another embodiment, other oxidizing agents other than KNO3 are added to the etchant solution. In yet another embodiment, the anisotropic etching process of the substrate 100 includes multiple subprocesses. In one example, a first etchant solution including HF, AgNO3, and H2O is used for a first time period and then a second etchant solution including HF, H2O2, and H2O is used for a second time period. In another example, a third etchant solution including HF, AgNO3, and H2O is used for a third time period and then a fourth etchant solution including HF, Fe(NO3)3, and H2O is used for a fourth time period. According to some embodiments, the anisotropic dry etching process is a plasma dry etching process.
As shown in
In another embodiment, the cross-section of the structure 130 (e.g., the cross-section perpendicular to the vertical depth direction) can be in millimeters, centimeters, or as large as the whole substrate size. For example, the structure 130 is a bulk nanohole structure. In another example, by adjusting the masking process as shown in
As discussed above and further emphasized here,
As shown in
As discussed above and further emphasized here,
In one embodiment, within each of the nanoholes 210 (e.g., the nanoholes 120, the nanoholes 132), there is no nanowire. In another embodiment, within each of the nanoholes 210 (e.g., the nanoholes 120, the nanoholes 132), there are one or more nanowires, which, for example, are generated by the anisotropic wet etching process.
According to some embodiments, referring to
According to some embodiments, referring to
(1) In the process for applying the mask 110 onto the substrate surface 102 of the substrate 100, during the photolithography, overexposing the one or more photoresist materials to increase the hole size and therefore reduce the sidewall thickness;
(2) In the process for forming the multiple nanoholes 120 in the substrate 100, during the anisotropic wet etching process with an etchant solution, adjusting the etchant concentration to change the degree of anisotropicity in order to reduce the sidewall thickness at certain depths into the substrate 100; and/or
(3) After the nanoholes 120 and/or the nanoholes 132 are formed, oxidizing the nanoholes and then removing the resulting oxide in order to reduce the sidewall thickness.
As shown in
As discussed above and further emphasized here,
In one embodiment, the substrate 300 (e.g., a silicon wafer) is diced along the X-X′ lines and the Y-Y′ lines to form multiple patches. For example, each patch 310 (e.g., each die) serves as the substrate 100. In another example, each patch 310 has a cross-section dimension in millimeter or centimeter range in the top view. In yet another example, a patch 310 is entirely doped to p type. In yet another example, a patch 310 is entirely doped to n-type.
In another embodiment, one or more metal materials are added in the regions defined by the Y-Y′ lines and form one or more metal contacts. For example, after the substrate 300 is diced, one or more portions of the one or more metal contacts stay in order to couple with the one or more arrays of nanoholes that are to be formed in each patch 310, resulting in one or more bulk nanohole structures each with two side thermal and electrical contacts.
In one embodiment, the substrate 300 (e.g., a silicon wafer) is diced along the X-X′ lines to form multiple stripes. For example, each stripe 320 includes multiple patches 310, which are doped alternately to n-type or p-type. In another example, different stripes 320 can have various number of pitches 310, and therefore also various length. In yet another example, each stripe 320 serves as one or more substrates 100.
In another embodiment, one or more metal materials are added in the regions defined by the Y-Y′ lines and form one or more metal contacts. For example, within each stripe 320, one or more bulk nanohole structures 130 is formed and bounded by the metal contacts (e.g., the metal contacts each serving as a thermal and electrical contact). In yet another embodiment, each strip 320 with multiple bulk nanohole structures 130 can be used to form one or more thermoelectric devices. For example, the thermal gradient is applied in the direction (e.g., in the X direction) that is the same as the direction of electrical current flow along the strip length. In another example, the thermal gradient is applied in the direction (e.g., in the Y direction) perpendicular to the direction of electrical current flow.
In one embodiment, the method for making one or more arrays of nanoholes in a substrate includes the following sequential processes (a) through (h):
As shown in
As shown in
In another embodiment, at least one mask region 416 includes multiple mask islands 412 separated by multiple holes 414. For example, within each hole 414, the substrate surface 402 is exposed. In yet another example, the holes 414 are in nanoscopic scale, and the hole-to-hole separations (e.g., the pitch sizes) are also in nanoscopic scale. According to one embodiment, one or more co-polymer materials including metal particles are used to form the mask 410. According to another embodiment, one or more photoresist materials are used to pattern another inorganic material layer in order to form the mask 410.
As shown in
In another embodiment, the nanoholes 420 are substantially vertical to the substrate surface 402, extending into the substrate 400 with corresponding depths. For example, the corresponding depths each exceed 100 μm. In another example, the corresponding depths each are at least 200 μm. In yet another example, the corresponding depths each are at least 400 μm. In yet another example, the corresponding depths each are at least 500 μm. In yet another example, the corresponding depths each are up to the total thickness of the substrate 400. In yet another embodiment, the trenches 428 have corresponding widths each of a few tens or hundreds of microns or greater, and corresponding depths approximately equal to the corresponding depths of the nanoholes 420.
In yet another embodiment, the nanoholes 420 that correspond to the same mask region 416 form an array of nanoholes 420, and two adjacent arrays of nanoholes 420 are separated by at least a trench 428. For example, the density of the array of nanoholes 420 has a hole density characterized by separations of the holes 414 (e.g., the pitch sizes). In another example, the average pitch size is about 70 nm. In yet another embodiment, the cross-sectional areas of corresponding nanoholes 420 determine the porosity of the resulting substrate structure as shown in
According to one embodiment, a top view of the array of nanoholes 420 as shown in
According to some embodiments, the anisotropic wet etching process can create roughened and/or porous sidewall surfaces for the nanoholes 420 and therefore reduce the thermal conductivity. According to certain embodiments, the nanoholes 420 are formed by applying an anisotropic etching process with an etchant solution that includes HF, AgNO3, and H2O. For example, the molar concentration of HF in the etchant solution varies from 2M to 10M. In another example, the molar concentration of AgNO3 in the etchant solution varies from 0.001M to 0.5M. In yet another example, other molar concentrations vary depending on the etching parameters desired. In yet another embodiment, KNO3 is added to the etchant solution. In one example, the KNO3 is added to the etchant solution after a certain time period of initial etching without KNO3 in the etchant solution. In another example, KNO3 is added to the etchant solution all at once. In yet another example, KNO3 is added to the etchant solution continuously at a predetermined rate. In yet another example, KNO3 is added to the etchant solution to maintain the proper balance between Ag and Ag+ to control the etching rate, the anisotropy, and/or other etch characteristics. In yet another embodiment, other oxidizing agents other than KNO3 are added to the etchant solution. In yet another embodiment, the anisotropic etching process of the substrate 400 includes multiple subprocesses. In one example, a first etchant solution including HF, AgNO3, and H2O is used for a first time period and then a second etchant solution including HF, H2O2, and H2O is used for a second time period. In another example, a third etchant solution including HF, AgNO3, and H2O is used for a third time period and then a fourth etchant solution including HF, Fe(NO3)3, and H2O is used for a fourth time period. According to some embodiments, the anisotropic dry etching process is a plasma dry etching process.
As shown in
As shown in
In one embodiment, the barrier layer 440 includes titanium nitride and/or tungsten nitride. In another embodiment, the barrier layer 440 includes tungsten silicide and/or tungsten nitride. In yet another embodiment, the barrier layer 440 includes titanium silicide and/or titanium nitride. In yet another embodiment, the barrier layer 440 use the same one or more materials used for the mask 430.
As shown in
As shown in
As shown in
In another embodiment, each structure 470 includes an array of nanoholes 432 and at least parts of two conductive materials 474, and the substrate 400 includes two substrate surfaces 1402 and 1404. For example, the array of nanoholes 432 is sandwiched by the two conductive materials 474. In another yet example, the part of one of the two conductive materials 474 serves as a thermal and electrical contact region on one side of the array of nanoholes 432 (e.g., serving as a thermal and electrical contact to a substrate surface 1406 of the substrate 400) for the corresponding structure 470. In yet another example, the part of the other one of the two conductive materials 474 serves as a thermal and electrical contact region on another side of the array of nanoholes 432 (e.g., serving as a thermal and electrical contact to a substrate surface 1408 of the substrate 400) for the corresponding structure 470. In yet another example, the two conductive materials 474 are the remaining portions of the corresponding conductive materials 460 after the polishing process. According to one embodiment, the substrate surface 1406 extends from the substrate surface 1402 towards the substrate surface 1404. For example, the substrate surface 1406 is in direct contact with both the substrate surfaces 1402 and 1404. According to another embodiment, the substrate surface 1408 extends from the substrate surface 1402 towards the substrate surface 1404. For example, the substrate surface 1408 is in direct contact with both the substrate surfaces 1402 and 1404.
In yet another embodiment, the nanoholes 432 are parallel with each other (e.g., being vertically-aligned nanoholes). For example, the nanoholes 432 are either the same as the corresponding nanoholes 420 or shorter than the corresponding nanoholes 420, respectively. In another example, each of the nanoholes 432 has a depth that is larger than 100 μm. In yet another example, each of the nanoholes 432 has a depth that is larger than 200 μm. In yet another example, each of the nanoholes 432 has a depth that is larger than 400 μm. In yet another example, each of the nanoholes 432 has a depth that is larger than 500 μm.
In yet another embodiment, the cross-section of the structure 470 (e.g., the cross-section perpendicular to the vertical depth direction) can be in millimeters, centimeters, or as large as the whole substrate size. For example, the structure 470 is a bulk nanohole structure.
In another example, by adjusting the masking process as shown in
As discussed above and further emphasized here,
As shown in
According to one embodiment, the structure 470 is a single die. For example, the structure 470 has dimensions in both directions within the top view, ranging from millimeters and above. According to another embodiment, the structure 470 can form a thermoelectric (TE) leg. For example, if the substrate material in the structure 470 is doped to n type, the structure 470 serves as an n-type thermoelectric leg. In another example, if the substrate material in the structure 470 is doped to p type, the structure 470 serves as a p-type thermoelectric leg.
As shown in
As shown in
In one embodiment, the structure 500 includes array regions 530, 532, and 534. For example, each of these array regions 530, 532, and 534 is the same as the array region 510. In another embodiment, the structure 500 includes conductive regions 542, 544, and 546. For example, each of the conductive regions 542, 544, and 546 is the same as the region 474. In another example, the conductive region 544 is a combination of the conductive region 520 of the structure 570 and the conductive region 522 of the structure 572. In yet another embodiment, the structure 500 includes a structure 580, which is the same as the structure 480 as shown in
According to one embodiment, the substrate material of the structure 500 is doped to n type. For example, the structure 500 serves as an n-type thermoelectric leg. In another example, the temperature gradient is applied between the conductive regions 542 and 546, and the electrical current flows between the conductive regions 542 and 546. According to another embodiment, the substrate material of the structure 500 is doped to p type. For example, the structure 500 serves as a p-type thermoelectric leg. In another example, the temperature gradient is applied between the conductive regions 542 and 546, and the electrical current flows between the conductive regions 542 and 546.
According to yet another embodiment, the substrate material corresponding to two array regions that are separated by a conductive region (e.g., by the conductive region 542 or by the conductive region 544) are doped alternately to n type or p type. For example, if the substrate material for the array region 530 is doped to n type, the substrate material for the array region 532 is doped to p type. In another example, if the substrate material for the array region 530 is doped to p type, the substrate material for the array region 532 is doped to n type. In yet another example, by alternating the doping types, the structure 500 can be directly applied as thermoelectric devices in one or more configurations with each structure 510 (e.g., the structure 570, 572, or 574) being coupled thermally and electrically in different manners and/or orientations.
As discussed above and further emphasized here,
In one embodiment, the method for making one or more arrays of nanoholes in a substrate includes the following sequential processes (a) through (p):
As shown in
As shown in
As shown in
As shown in
According to one embodiment, the mask region 634 includes multiple mask islands 637 separated by multiple holes 638. For example, within each hole 638, the silicon carbide layer 620 is exposed. In another example, a hole 638 separates a mask island 637 from either another mask island 637 or the mask region 632 or 636. In yet another example, the holes 638 are in nanoscopic scale, and the hole-to-hole separations (e.g., the pitch sizes) are also in nanoscopic scale. According to another embodiment, one or more co-polymer materials including metal particles are used to form the mask 630. According to yet another embodiment, one or more photoresist materials are used to pattern another inorganic material layer in order to form the mask 630.
As shown in
As shown in
In yet another embodiment, the nanoholes 640 form an array of nanoholes 640. For example, the density of the array of nanoholes 640 has a hole density characterized by separations of the holes 640 (e.g., the pitch sizes). In another example, the average pitch size is about 70 nm. In yet another embodiment, the cross-sectional areas of corresponding nanoholes 640 determine the porosity of the resulting substrate structure as shown in
According to one embodiment, a top view of the array of nanoholes 640 as shown in
According to some embodiments, the nanoholes 640 are formed in the substrate 600 by anisotropic wet chemical etching process for an extended period of time. For example, the structure as shown in
According to some embodiments, the anisotropic wet etching process can create roughened and/or porous sidewall surfaces for the nanoholes 640 and therefore reduce the thermal conductivity. According to certain embodiments, the nanoholes 640 are formed by applying an anisotropic etching process with an etchant solution that includes HF, AgNO3, and H2O. For example, the molar concentration of HF in the etchant solution varies from 2M to 10M. In another example, the molar concentration of AgNO3 in the etchant solution varies from 0.001M to 0.5M. In yet another example, other molar concentrations vary depending on the etching parameters desired. In yet another embodiment, KNO3 is added to the etchant solution. In one example, the KNO3 is added to the etchant solution after a certain time period of initial etching without KNO3 in the etchant solution. In another example, KNO3 is added to the etchant solution all at once. In yet another example, KNO3 is added to the etchant solution continuously at a predetermined rate. In yet another example, KNO3 is added to the etchant solution to maintain the proper balance between Ag and Ag+ to control the etching rate, the anisotropy, and/or other etch characteristics. In yet another embodiment, other oxidizing agents other than KNO3 are added to the etchant solution. In yet another embodiment, the anisotropic etching process of the substrate 600 includes multiple subprocesses. In one example, a first etchant solution including HF, AgNO3, and H2O is used for a first time period and then a second etchant solution including HF, H2O2, and H2O is used for a second time period. In another example, a third etchant solution including HF, AgNO3, and H2O is used for a third time period and then a fourth etchant solution including HF, Fe(NO3)3, and H2O is used for a fourth time period.
As shown in
As shown in
In another embodiment, one or more photoresist materials (e.g., a photoresist material used for silicon processing) are used to pattern another inorganic material layer in order to form the mask 666.
As shown in
In another embodiment, the removal of the portions of the substrate 600 (e.g., the etching of the portions of the silicon substrate 600) is less anisotropic than the removal of the corresponding portions of the one or more oxide materials 650, the corresponding portions of the silicon carbide layer 620, and the corresponding portions of the oxide layer 610. For example, the trenches 672 and 674 have widths that are larger than the widths of the removed corresponding portions of the one or more oxide materials 650, the removed corresponding portions of the silicon carbide layer 620, and the removed corresponding portions of the oxide layer 610, and the trenches 672 and 674 have depths that are approximately equal to the corresponding depths of the nanoholes 640. In another example, the widths of the trenches 672 and 674 are greater than a few hundreds of micrometers, a few millimeters or greater. In yet another example, the etching of the portions of the silicon substrate 600 is performed using the TMAH etching technique, although other wet or dry etching techniques can also be used.
As shown in
In one embodiment, the mask 660 is removed by a chemical process. In another embodiment, the silicon carbide layer 620 and the oxide layer 610 are removed by a mechanical polishing process. In yet another embodiment, the trench 672 is used for forming a thermal and electrical contact of a nanohole structure associated with the array of nanoholes 640, and the trench 674 is also used for forming a thermal and electrical contact of the nanohole structure associated with the array of nanoholes 640.
As shown in
As shown in
In one embodiment, the one or more conductive materials 692 at least partially fill the trench 672, and also cover at least part of the surface 682 and the substrate surface 684. For example, the trench 672 has a depth that is approximately equal to the corresponding depths of the nanoholes 640, and the one or more conductive materials 692 within the trench 672 form a thermal and electrical contact with a side of the substrate material that is adjacent to one or more of the nanoholes 640. In another example, the one or more conductive materials 692 on the surface 682 and the substrate surface 684 can be used to extend the thermal and/or electrical path above the top end of the array of nanoholes 640 in order to form a thermal and/or electrical contact with one or more external terminals (e.g., one or more external electrodes).
In another embodiment, the one or more conductive materials 694 at least partially fill the trench 674, and also cover at least part of the surface 682 and the substrate surface 686. For example, the trench 674 has a depth that is approximately equal to the corresponding depths of the nanoholes 640, and the one or more conductive materials 694 within the trench 674 form a thermal and electrical contact with a side of the substrate material that is adjacent to one or more of the nanoholes 640. In another example, the one or more conductive materials 694 on the surface 682 and the substrate surface 686 can be used to extend the thermal and/or electrical path above the top end of the array of nanoholes 640 in order to form a thermal and/or electrical contact with one or more external terminals (e.g., one or more external electrodes).
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As shown in
In yet another embodiment, the nanoholes 640 are parallel with each other (e.g., being vertically-aligned nanoholes). For example, the nanoholes 640 as shown in
As discussed above and further emphasized here,
In one embodiment, the structure 1600 as shown in
In one embodiment, the method for making one or more arrays of nanoholes in a substrate includes the following sequential processes (a) through (e):
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As shown in
As shown in
According to one embodiment, a top view of the array of nanoholes 720 as shown in
According to some embodiments, the nanoholes 720 are formed in the substrate 700 by anisotropic wet chemical etching process for an extended period of time. For example, the structure as shown in
According to some embodiments, the anisotropic wet etching process can create roughened and/or porous sidewall surfaces for the nanoholes 720 and therefore reduce the thermal conductivity. According to certain embodiments, the nanoholes 720 are formed by applying an anisotropic etching process with an etchant solution that includes HF, AgNO3, and H2O. For example, the molar concentration of HF in the etchant solution varies from 2M to 10M. In another example, the molar concentration of AgNO3 in the etchant solution varies from 0.001M to 0.5M. In yet another example, other molar concentrations vary depending on the etching parameters desired. In yet another embodiment, KNO3 is added to the etchant solution. In one example, the KNO3 is added to the etchant solution after a certain time period of initial etching without KNO3 in the etchant solution. In another example, KNO3 is added to the etchant solution all at once. In yet another example, KNO3 is added to the etchant solution continuously at a predetermined rate. In yet another example, KNO3 is added to the etchant solution to maintain the proper balance between Ag and Ag+ to control the etching rate, the anisotropy, and/or other etch characteristics. In yet another embodiment, other oxidizing agents other than KNO3 are added to the etchant solution. In yet another embodiment, the anisotropic etching process of the substrate 700 includes multiple subprocesses. In one example, a first etchant solution including HF, AgNO3, and H2O is used for a first time period and then a second etchant solution including HF, H2O2, and H2O is used for a second time period. In another example, a third etchant solution including HF, AgNO3, and H2O is used for a third time period and then a fourth etchant solution including HF, Fe(NO3)3, and H2O is used for a fourth time period.
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As shown in
In another embodiment, the trenches 740 have depths that are approximately equal to the corresponding depths of the nanoholes 720. In yet another embodiment, the trenches 740 are used for forming electrical and/or thermal contacts of a nanohole structure (e.g., a bulk nanohole structure including the nanoholes 720 between the trenches 740) associated with the array of nanoholes 720. For example, one of the trenches 740 is used for forming a thermal and electrical contact to a substrate surface 1706 of the substrate 700. In another example, another one of the trenches 740 is used for forming a thermal and electrical contact to a substrate surface 1708 of the substrate 700. According to one embodiment, the substrate surface 1706 extends from the substrate surface 702 towards the substrate surface 704. For example, the substrate surface 1706 is in direct contact with the substrate surface 702 but not with the substrate surface 704. In another example, the substrate surface 1706 is substantially perpendicular to both the substrate surfaces 702 and 704. According to another embodiment, the substrate surface 1708 extends from the substrate surface 702 towards the substrate surface 704. For example, the substrate surface 1708 is in direct contact with the substrate surface 702 but not with the substrate surface 704. In another example, the substrate surface 1708 is substantially perpendicular to both the substrate surfaces 702 and 704. In yet another embodiment, a top view of the array of nanoholes 720 as shown in
As discussed above and further emphasized here,
In another embodiment, the trenches 740 are formed also to provide patterned patches on the substrate 700 and used for completely dicing out the substrate 700 into a plurality of unit blocks of material. For example, the patch size (e.g., a distance between two trenches 740) can be selected to be in millimeter or centimeter range so that each block of material becomes a nanohole structure, which includes one or more arrays of nanoholes 720.
In another example, such one or more arrays of nanoholes 720 are formed across a bulk lateral dimension (e.g., the patch size) within each patch, and bound by thermal and electrical contacts formed on the sides of the patch (e.g., opposite sides of the patch) that are approximately in parallel to the corresponding depths of the nanoholes 720.
Certain Embodiments provide a bulk nanohole structure including arrays of nanoholes having ultra-long lengths exceeding 100 micrometers formed substantially vertically into a semiconductor substrate. For example, the arrays of ultra-long nanoholes are distributed with a pitch size about 60 nm to 100 nm and an average hole size of about 20 nm to 40 nm. In an embodiment, the arrays of ultra-long nanoholes and a plurality of patterned trenches are formed together by etching from a first patterned mask with porous nanoscopic sized holes. The first patterned mask includes porous nanoscopic sized holes within any of a plurality of patterned patches divided by a set of line patterns across the semiconductor substrate. For example, each patch has bulk dimensions ranging from a few millimeters to 10 centimeters and greater, for the arrays of ultra-long nanoholes formed therein. Along the set of line patterns, at least partially, a contact metal or conductive material can be formed therein. In another example, the semiconductor substrate can be diced along the sets of line patterns, with contact metal filled therein, to form a single block of material or a stripe of material having multiple blocks. In yet another example, the single block of material forms a bulk nanohole structure including arrays of ultra-long nanoholes formed in each patch with two conductive contacts coupled from two sides, based on which a single thermoelectric leg is formed. The stripe of material having multiple blocks are simply multiple blocks without being diced into multiple single blocks and the whole stripe itself can be used to form alternative thermoelectric devices, according to some embodiments.
In another embodiment, a first mask is applied to specifically form the arrays of ultra-long nanoholes using a chemical wet etching technique. The arrays of ultra-long nanoholes are formed substantially vertically into the semiconductor substrate having lengths exceeding hundreds of micrometers and a density characterized by a pitch size of less than 100 nanometers. The first mask is removed and the arrays of ultra-long nanoholes are filled by oxide material. Then a second mask is applied to determine bulk-sized patches and be used to perform another etching process to form a plurality of contact regions along boundaries of each patch. A metal material is deposited to form electric contacts at the plurality of contact regions before a dicing process is applied to transform the bulk-sized patches into multiple bulk nanohole structures with two conductive side contacts coupled to arrays of ultra-long nanoholes therein according to certain embodiments.
In yet another embodiment, bulk nanohole structures include arrays of ultra-long nanoholes formed substantially vertically into bulk semiconductor substrates. The arrays of nanoholes have lengths of several hundred micrometers and a density characterized by a pitch size less than 100 nm. The bulk nanohole structures can be formed into any sized blocks as large as centimeter-range patterns within a silicon wafer. Each block is configured to couple with a pair of contact electrodes from two sides, which are formed directly in the same silicon wafer substantially in parallel to the arrays of nanoholes. For example, the block with the bulk nanohole structures provides a mechanically strong material unit with high electrical conductance but with much lower thermal conductivity than same sized bulk material. In yet another embodiment, certain methods are provided for forming the ultra-long nanoholes, the bulk nanohole structures, based on which various electronic devices including high-performance thermoelectric devices are formed.
According to another embodiment, an array of nanoholes includes a plurality of nanoholes. Each of the plurality of nanoholes corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 μm. Each of the plurality of nanoholes corresponds to a cross-sectional area associated with a distance across, and the distance across ranges from 5 nm to 500 nm. Each of the plurality of nanoholes is separated from at least another nanohole selected from the plurality of nanoholes by a semiconductor material associated with a sidewall thickness, and the sidewall thickness ranges from 5 nm to 500 nm. For example, the array of nanoholes is implemented according to at least
According to yet another embodiment, a structure including an array of nanoholes includes a semiconductor substrate with a plurality of nanoholes. The semiconductor substrate includes a first surface, a second surface opposite to the first surface, a third surface extending from the first surface towards the second surface, and a fourth surface extending from the first surface towards the second surface. Each of the plurality of nanoholes corresponds to a first end at the first surface and a second end. Additionally, the structure includes a first thermal and electrical contact material coupled to the third surface, and a second thermal and electrical contact material coupled to the fourth surface. Each of the plurality of nanoholes corresponds to a cross-sectional area associated with a distance across, and the distance across ranges from 5 nm to 500 nm. Each of the plurality of nanoholes is separated from at least another nanohole selected from the plurality of nanoholes by a semiconductor sidewall associated with a sidewall thickness. The semiconductor sidewall is a part of the semiconductor substrate, and the sidewall thickness ranges from 5 nm to 500 nm. For example, the array of nanoholes is implemented according to at least
According to yet another embodiment, a method for forming an array of nanoholes includes providing a semiconductor substrate including a first surface and forming a mask on the first surface. The mask includes mask regions separated by corresponding mask holes, and portions of the first surface are exposed within the corresponding mask holes. Additionally, the method includes etching the semiconductor substrate through at least the exposed portion of the first surface to form at least nanoholes. Each of the nanoholes corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 μm. Each of the nanoholes corresponds to a cross-sectional area associated with a distance across ranging from 5 nm to 500 nm. Each of the nanoholes is separated from at least another of the nanoholes by a semiconductor sidewall associated with a sidewall thickness ranging from 5 nm to 500 nm, and the semiconductor sidewall is a part of the semiconductor substrate. For example, the method is implemented according to at least
According to yet another embodiment, a method for forming a structure including an array of nanoholes includes providing a semiconductor substrate including a first surface and forming a mask on the first surface. The mask includes mask regions separated by corresponding mask holes, and portions of the first surface are exposed within the corresponding mask holes. Additionally, the method includes etching the semiconductor substrate through at least the exposed portion of the first surface to form at least nanoholes. Each of the nanoholes corresponds to a first end at the first surface and a second end. Each of the nanoholes corresponding to a cross-sectional area associated with a distance across ranging from 5 nm to 500 nm. Each of the nanoholes is separated from at least another of the nanoholes by a semiconductor sidewall associated with a sidewall thickness ranging from 5 nm to 500 nm, and the semiconductor sidewall is a part of the semiconductor substrate. Also, the method includes etching the semiconductor substrate to form at least a first trench and a second trench, forming a first thermal and electrical contact within the first trench with the semiconductor substrate, and forming a second thermal and electrical contact within the second trench with the semiconductor substrate. For example, the method is implemented according to at least
Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. For example, various embodiments and/or examples of the present invention can be combined. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims.
This application claims priority to U.S. Provisional Application No. 61/597,254, filed Feb. 10, 2012, commonly assigned and incorporated by reference herein for all purposes.
Number | Date | Country | |
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61597254 | Feb 2012 | US |