Patent Application
20240334669
Chemical etching is a process used in semiconductor manufacturing. Chemical etching may include usage of a chemical solution to selectively remove material from a surface in order to create a desired pattern or shape. The surface is first coated with a resist material that is resistant to the etching solution, except in the areas where the pattern or shape is desired. The resist is then exposed to a mask or template that defines the pattern or shape, and the exposed resist is removed to reveal the areas where the etching solution can penetrate and remove the underlying material. In some instances, chemical etching may remove excessive material and introduce unwanted open circuits in an integrated circuit device.
In some integrated circuit devices, the connections between S/Ds of certain transistors and gates of other transistors (e.g., as required in an SRAM cell) may be accomplished using a metal layer of the interconnect layers 202 (e.g., a metal 0 layer that is closest to the device layer(s) 200. However, in various embodiments of the present disclosure, at least some of the S/D to gate connections (e.g., 210) are formed in the device layer(s) 200, e.g., these S/D to gate connections may be formed directly on the gate and S/D materials.
In various embodiments, (such as the embodiment depicted), gate-all-around transistors (e.g., such as those depicted in
Although not shown, in various embodiments, the S/D to gate connection 210 may couple an S/D of an additional transistor to the gate 206. For example, a third transistor may be formed above the second transistor in the device layer(s) in a stacked transistor topography and an S/D of the third transistor may be coupled to the gate 206 of the first transistor through the same S/D to gate connection 210.
The S/D to gate connection 302 couples the S/D material 308 (e.g., doped epitaxial silicon or other suitable material) of the first transistor to the gate material 312 of the second transistor. The SRAM cell 300 also includes a low-k dielectric 314. In various embodiments, the low-k dielectric 314 may be buried underneath a portion of the S/D to gate connection 302. During fabrication, the low-k dielectric 314 acts as an etch stop layer, protecting one or more material layers underneath the low-k dielectric from an etching process, so as not to expose ohmic contact material 316 (e.g., a silicide, such as titanium silicide) or the S/D material 308 to unwanted removal which could cause formation of an open circuit between the S/D material 308 of the first transistor and the S/D to gate connection 302 and thus also an open circuit between the S/D material 308 and the gate material 312 of the second transistor.
At least a portion of the low-k dielectric 314 may be formed over an area between gate material 312 and the S/D material 308. Because the low-k dielectric 314 may be formed in a film, the low-k dielectric 314 may be present in other portions of the SRAM cell 300, such as over an area between the S/D material 308 and the other gate material 310.
The low-k dielectric 314 may also be present in other portions (not shown) of the SRAM cell 300 as well in other logic 350 that is cointegrated (e.g., in the same plane) as the SRAM cell 300. For example, the low-k dielectric 314 may be present above an area between S/D material 354 and gate material 352 or above an area between S/D material 354 and an isolation dielectric 318. Because this low-k dielectric 314 may replace volume that would otherwise be occupied by a higher-k dielectric, a reduction in parasitic capacitance in transistors of the other logic 350 may also be achieved in some embodiments.
During fabrication, the low-k dielectric 314 may be capped with a nitride cap material 320 to protect it from one or more subsequent operations. A large portion of this nitride cap material 320 may be removed during fabrication, but portions of it may persist (e.g., some of the nitride cap material 320 may be present within small recesses formed in the low-k dielectric 314) or above the isolation dielectric 318.
In various embodiments, the low-k dielectric 314 may comprise silicon, oxygen, and carbon. In some embodiments, the low-k dielectric 314 comprises silicon oxide doped with carbon. In various embodiments, the low-k dielectric comprises silicon and has one or more of the following constraints on atomic percentage: nitrogen <20%, oxygen>20%, and carbon>5%. Any or all of these composition ranges may result in a low-k dielectric 314 that is less like silicon nitride and more like silicon oxide, thus having a lower etch rate and lower k value than pure silicon nitride.
In various embodiments, the low-k dielectric 314 may have a high etch selectivity to silicon nitride, that is, the etch rate of the low-k dielectric 314 may be relatively low compared to the etch rate of silicon nitride, thus the low-k dielectric 314 may be used as an etch stop during an etch in which other materials comprising a relatively large amount of silicon nitride may be wholly or partially removed.
In various embodiments, the low-k dielectric 314 may have a dielectric constant (k) value that is higher than silicon oxide, but lower than silicon nitride. In some embodiments, the low-k dielectric 314 may have a k value of between 3.8 to 5 (although embodiments aren't limited thereto) as this may result from a composition of the low-k dielectric 314 that makes it suitable to protect lower layers through its etch selectivity.
Example phases of manufacture are now described for the portion of the SRAM cell 300 and the logic 350 in
Phase 400 of
Logic 350 comprises (among other portions such as 402, 404, 406 that may be similar to those in SRAM cell 300) a channel 408 comprising nanoribbons 410, S/D material 354, and gate material 352. However, in the logic 350, an additional instance of the gate material has been removed and replaced with an insulator. Thus, in place of an additional gate material, the logic 350 includes a nitride liner 416 (e.g., comprising silicon nitride) filled with an isolation dielectric 418 (e.g., silicon oxide) and a nitride plug 422 (e.g., comprising silicon nitride) on top of the isolation dielectric 418. Such a technique may be used, for instance, in fin trim isolation (FTI) fabrication.
Phase 450 depicts SRAM cell 300 and logic 350 after a nitride recessing operation has been performed. This operation may include the removal (e.g., by etching) of nitride based materials. For example, as depicted, this operation may remove portions of the nitride-like spacer material 402 and nitride liner 404. This operation may also cause some damage to the top of the trench contact oxide 406 (the damage will be removed in a future polishing operation). For the logic 350, this operation also removes some of the nitride liner 416 and a large portion of the nitride plug 422.
Phase 500 of
Phase 550 of
Phase 600 of
Phase 650 of
Phase 700 of
Phase 750 of
Phase 800 of
Phase 850 of
Phase 900 of
Phase 950 of
Phase 1000 of
Phase 1050 of
Phase 1100 of
Phase 1150 of
Although various embodiments herein describe a low-k dielectric 314 and nitride cap material 320 used during fabrication of an SRAM cell, the teachings herein may be applied to any suitable S/D to gate connection for transistors of any suitable circuits or to other locations within an integrated circuit device (e.g., to reduce parasitic capacitances of devices). Moreover, the techniques may be used with either or both of N type transistors or P type transistors.
The integrated circuit device 1300 may include one or more device layers 1304 disposed on the die substrate 1302. The device layer 1304 may include features of one or more transistors 1340 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1302. The transistors 1340 may include, for example, one or more source and/or drain (S/D) regions 1320, a gate 1322 to control current flow between the S/D regions 1320, and one or more S/D contacts 1324 to route electrical signals to/from the S/D regions 1320. The transistors 1340 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1340 are not limited to the type and configuration depicted in
Returning to
The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1340 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1340 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1302 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1302. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1302 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1302. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1320 may be formed within the die substrate 1302 adjacent to the gate 1322 of individual transistors 1340. The S/D regions 1320 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1302 to form the S/D regions 1320. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1302 may follow the ion-implantation process. In the latter process, the die substrate 1302 may first be etched to form recesses at the locations of the S/D regions 1320. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1320. In some implementations, the S/D regions 1320 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1320 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1320.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1340) of the device layer 1304 through one or more interconnect layers disposed on the device layer 1304 (illustrated in
The interconnect structures 1328 may be arranged within the interconnect layers 1306-1310 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1328 depicted in
In some embodiments, the interconnect structures 1328 may include lines 1328a and/or vias 1328b filled with an electrically conductive material such as a metal. The lines 1328a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1302 upon which the device layer 1304 is formed. For example, the lines 1328a may route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias 1328b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate 1302 upon which the device layer 1304 is formed. In some embodiments, the vias 1328b may electrically couple lines 1328a of different interconnect layers 1306-1310 together.
The interconnect layers 1306-1310 may include a dielectric material 1326 disposed between the interconnect structures 1328, as shown in
A first interconnect layer 1306 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1304. In some embodiments, the first interconnect layer 1306 may include lines 1328a and/or vias 1328b, as shown. The lines 1328a of the first interconnect layer 1306 may be coupled with contacts (e.g., the S/D contacts 1324) of the device layer 1304. The vias 1328b of the first interconnect layer 1306 may be coupled with the lines 1328a of a second interconnect layer 1308.
The second interconnect layer 1308 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1306. In some embodiments, the second interconnect layer 1308 may include via 1328b to couple the lines 1328 of the second interconnect layer 1308 with the lines 1328a of a third interconnect layer 1310. Although the lines 1328a and the vias 1328b are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines 1328a and the vias 1328b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
The third interconnect layer 1310 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1308 according to similar techniques and configurations described in connection with the second interconnect layer 1308 or the first interconnect layer 1306. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1319 in the integrated circuit device 1300 (i.e., farther away from the device layer 1304) may be thicker that the interconnect layers that are lower in the metallization stack 1319, with lines 1328a and vias 1328b in the higher interconnect layers being thicker than those in the lower interconnect layers.
The integrated circuit device 1300 may include a solder resist material 1334 (e.g., polyimide or similar material) and one or more conductive contacts 1336 formed on the interconnect layers 1306-1310. In
In some embodiments in which the integrated circuit device 1300 is a double-sided die, the integrated circuit device 1300 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1304. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1306-1310, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1304 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1300 from the conductive contacts 1336.
In other embodiments in which the integrated circuit device 1300 is a double-sided die, the integrated circuit device 1300 may include one or more through silicon vias (TSVs) through the die substrate 1302; these TSVs may make contact with the device layer(s) 1304, and may provide conductive pathways between the device layer(s) 1304 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1300 from the conductive contacts 1336. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device 1300 from the conductive contacts 1336 to the transistors 1340 and any other components integrated into the circuit device (e.g., die) 1300, and the metallization stack 1319 can be used to route I/O signals from the conductive contacts 1336 to transistors 1340 and any other components integrated into the circuit device (e.g., die) 1300.
Multiple integrated circuit devices 1300 may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).
In some embodiments, the circuit board 1502 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1502. In other embodiments, the circuit board 1502 may be a non-PCB substrate. The integrated circuit device assembly 1500 illustrated in
The package-on-interposer structure 1536 may include an integrated circuit component 1520 coupled to an interposer 1504 by coupling components 1518. The coupling components 1518 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1516. Although a single integrated circuit component 1520 is shown in
The integrated circuit component 1520 may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., the die 1202 of
In embodiments where the integrated circuit component 1520 comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).
In addition to comprising one or more processor units, the integrated circuit component 1520 can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.
Generally, the interposer 1504 may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer 1504 may couple the integrated circuit component 1520 to a set of ball grid array (BGA) conductive contacts of the coupling components 1516 for coupling to the circuit board 1502. In the embodiment illustrated in
In some embodiments, the interposer 1504 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 1504 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1504 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1504 may include metal interconnects 1508 and vias 1510, including but not limited to through hole vias 1510-1 (that extend from a first face 1550 of the interposer 1504 to a second face 1554 of the interposer 1504), blind vias 1510-2 (that extend from the first or second faces 1550 or 1554 of the interposer 1504 to an internal metal layer), and buried vias 1510-3 (that connect internal metal layers).
In some embodiments, the interposer 1504 can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer 1504 comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer 1504 to an opposing second face of the interposer 1504.
The interposer 1504 may further include embedded devices 1514, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1504. The package-on-interposer structure 1536 may take the form of any of the package-on-interposer structures known in the art.
The integrated circuit device assembly 1500 may include an integrated circuit component 1524 coupled to the first face 1540 of the circuit board 1502 by coupling components 1522. The coupling components 1522 may take the form of any of the embodiments discussed above with reference to the coupling components 1516, and the integrated circuit component 1524 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1520.
The integrated circuit device assembly 1500 illustrated in
Additionally, in various embodiments, the electrical device 1600 may not include one or more of the components illustrated in
The electrical device 1600 may include one or more processor units 1602 (e.g., one or more processor units). As used herein, the terms “processor unit”, “processing unit” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor unit 1602 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU).
The electrical device 1600 may include a memory 1604, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory 1604 may include memory that is located on the same integrated circuit die as the processor unit 1602. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the electrical device 1600 can comprise one or more processor units 1602 that are heterogeneous or asymmetric to another processor unit 1602 in the electrical device 1600. There can be a variety of differences between the processing units 1602 in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units 1602 in the electrical device 1600.
In some embodiments, the electrical device 1600 may include a communication component 1612 (e.g., one or more communication components). For example, the communication component 1612 can manage wireless communications for the transfer of data to and from the electrical device 1600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication component 1612 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication component 1612 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1612 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1612 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication component 1612 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1600 may include an antenna 1622 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication component 1612 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component 1612 may include multiple communication components. For instance, a first communication component 1612 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 1612 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 1612 may be dedicated to wireless communications, and a second communication component 1612 may be dedicated to wired communications.
The electrical device 1600 may include battery/power circuitry 1614. The battery/power circuitry 1614 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1600 to an energy source separate from the electrical device 1600 (e.g., AC line power).
The electrical device 1600 may include a display device 1606 (or corresponding interface circuitry, as discussed above). The display device 1606 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1600 may include an audio output device 1608 (or corresponding interface circuitry, as discussed above). The audio output device 1608 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.
The electrical device 1600 may include an audio input device 1624 (or corresponding interface circuitry, as discussed above). The audio input device 1624 may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device 1600 may include a Global Navigation Satellite System (GNSS) device 1618 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 1618 may be in communication with a satellite-based system and may determine a geolocation of the electrical device 1600 based on information received from one or more GNSS satellites, as known in the art.
The electrical device 1600 may include another output device 1610 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1610 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1600 may include another input device 1620 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1620 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.
The electrical device 1600 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device 1600 may be any other electronic device that processes data. In some embodiments, the electrical device 1600 may comprise multiple discrete physical components. Given the range of devices that the electrical device 1600 can be manifested as in various embodiments, in some embodiments, the electrical device 1600 can be referred to as a computing device or a computing system.
Throughout this specification, plural instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.
Although an overview of embodiments has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of embodiments of the present disclosure.
The embodiments illustrated herein are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. The Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
It will also be understood that, although the terms “first,” “second,” and so forth may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first gate and the second contact are both contacts, but they are not the same contact.
As used in the description of the example embodiments and the appended examples, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
The description may use the phrases “in an embodiment,” “according to some embodiments,” “in accordance with embodiments,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
As used herein, the term “module” refers to being part of, or including an ASIC, an electronic circuit, a system on a chip, a processor (shared, dedicated, or group), a solid state device, a memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
As used herein, “electrically conductive” in some examples may refer to a property of a material having an electrical conductivity greater than or equal to 107 Siemens per meter (S/m) at 20 degrees Celsius. Examples of such materials include Cu, Ag, Al, Au, W, Zn and Ni.
In the corresponding drawings of the embodiments, signals, currents, electrical biases, or magnetic or electrical polarities may be represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, polarity, current, voltage, etc., as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
Throughout the specification, and in the claims, the term “connected” means a direct connection, such as electrical, mechanical, or magnetic connection between the elements that are connected, without any intermediary devices. The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the elements that are connected or an indirect connection, through one or more passive or active intermediary devices. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or layer over or under another may be directly in contact or may have one or more intervening materials or layers. Moreover, one material between two materials or layers may be directly in contact with the two materials/layers or may have one or more intervening materials/layers. In contrast, a first material or layer “on” a second material or layer is in direct contact with that second material/layer. Similar distinctions are to be made in the context of component assemblies.
Unless otherwise specified in the specific context of use, the term “predominantly” means more than 50%, or more than half. For example, a composition that is predominantly a first constituent means more than half of the composition (e.g., by volume) is the first constituent (e.g., >50 at. %). The term “primarily” means the most, or greatest, part. For example, a composition that is primarily a first constituent means the composition has more of the first constituent (e.g., by volume) than any other constituent. A composition that is primarily first and second constituents means the composition has more of the first and second constituents than any other constituent. The term “substantially” means there is only incidental variation. For example, composition that is substantially a first constituent means the composition may further include <1% of any other constituent. A composition that is substantially first and second constituents means the composition may further include <1% of any constituent substituted for either the first or second constituent.
As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms.
Unless otherwise specified in the explicit context of their use, the terms “substantially equal,” “about equal” or “approximately equal” mean that there is no more than incidental variation between two things so described. In the art, such variation is typically no more than +/−10% of a predetermined target value.
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
Although the figures may illustrate embodiments where structures are substantially aligned to Cartesian axes (e.g., device structures having substantially vertical sidewalls), positive and negative (re-entrant) sloped feature sidewalls often occur in practice. For example, manufacturing non-idealities may cause one or more structural features to have sloped sidewalls. Thus, attributes illustrated are idealized merely for the sake of clearly describing salient features. It is to be understood that schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.
The following examples are non-limiting recitations of the subject matter contemplated herein.
Example 1 includes an apparatus comprising a source or drain of a field effect transistor (FET); a first dielectric between a portion of the source or drain and a FET gate, the first dielectric comprising silicon nitride; and a second dielectric above at least a portion of the first dielectric, the second dielectric comprising silicon oxide doped with at least one of oxygen or carbon, the second dielectric having a dielectric constant lower than the first dielectric.
Example 2 includes the subject matter of Example 1, and further including a third dielectric formed within a recess in the second dielectric, the third dielectric comprising silicon nitride.
Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the second dielectric is below and in contact with a conductive material connecting the source or drain to the gate.
Example 4 includes the subject matter of any of Examples 1-3, and wherein the source or drain is a source or drain of a first FET of a static random access memory (SRAM) cell and the gate is a gate of a second FET of the SRAM cell.
Example 5 includes the subject matter of any of Examples 1-4, and wherein the source or drain is a source or drain of a transistor and the gate is a gate of the same transistor.
Example 6 includes the subject matter of any of Examples 1-5, and wherein the second dielectric has an atomic percentage of nitrogen that is less than 20%.
Example 7 includes the subject matter of any of Examples 1-6, and wherein the second dielectric has an atomic percentage of carbon that is greater than 5%.
Example 8 includes the subject matter of any of Examples 1-7, and wherein the second dielectric has an atomic percentage of oxygen that is greater than 20%.
Example 9 includes the subject matter of any of Examples 1-8, and further including a third dielectric in between and in contact with the source or drain and the second dielectric.
Example 10 includes the subject matter of any of Examples 1-9, and further including a nitride liner in contact with the source or drain and the third dielectric.
Example 11 includes the subject matter of any of Examples 1-10, and further including an integrated circuit die comprising the source or drain, the first dielectric, and the second dielectric.
Example 12 includes the subject matter of any of Examples 1-11, and further including a circuit board coupled to the integrated circuit die.
Example 13 includes the subject matter of any of Examples 1-12, further comprising at least one of a network interface, battery, or memory coupled to the integrated circuit die.
Example 14 includes an integrated circuit device comprising a first transistor comprising a source or drain; a second transistor comprising a gate; an electrically conductive connection between the source or drain of the first transistor and the gate of the second transistor; a first dielectric under and in contact with the electrically conductive connection; and a second dielectric under and in contact with the first dielectric.
Example 15 includes the subject matter of Example 14, and wherein the first dielectric comprises silicon oxide and has an atomic percentage of nitrogen that is less than 20%, an atomic percentage of carbon that is greater than 5%, and an atomic percentage of oxygen that is greater than 20%.
Example 16 includes the subject matter of any of Examples 14 and 15, and wherein the second dielectric comprises silicon nitride.
Example 17 includes the subject matter of any of Examples 14-16, and wherein the first dielectric has a dielectric constant that is lower than the second dielectric.
Example 18 includes the subject matter of any of Examples 14-17, and further including a third dielectric formed within a recess in the first dielectric, the third dielectric comprising silicon nitride.
Example 19 includes the subject matter of any of Examples 14-18, and wherein the source or drain is a source or drain of a first FET of a static random access memory (SRAM) cell and the gate is a gate of a second FET of the SRAM cell.
Example 20 includes the subject matter of any of Examples 14-19, and wherein the first dielectric has an atomic percentage of nitrogen that is less than 20%.
Example 21 includes the subject matter of any of Examples 14-20, and wherein the first dielectric has an atomic percentage of carbon that is greater than 5%.
Example 22 includes the subject matter of any of Examples 14-21, and wherein the first dielectric has an atomic percentage of oxygen that is greater than 20%.
Example 23 includes the subject matter of any of Examples 14-22, and further including a third dielectric in between and in contact with the source or drain and the first dielectric.
Example 24 includes the subject matter of any of Examples 14-23, and further including a nitride liner in contact with the source or drain and the third dielectric.
Example 25 includes the subject matter of any of Examples 14-24, and further including an integrated circuit die comprising the source or drain, the first dielectric, and the second dielectric.
Example 26 includes the subject matter of any of Examples 14-25, and further including a circuit board coupled to the integrated circuit die.
Example 27 includes the subject matter of any of Examples 14-26, and further including at least one of a network interface, battery, or memory coupled to the integrated circuit die.
Example 28 includes a method comprising forming a source or drain of a field effect transistor (FET); forming a first dielectric between a portion of the source or drain and a FET gate, the first dielectric comprising silicon nitride; and forming a second dielectric above at least a portion of the first dielectric, the second dielectric comprising silicon oxide doped with at least one of oxygen or carbon, the second dielectric having a dielectric constant lower than the first dielectric.
Example 29 includes the subject matter of Example 28, and further including forming a third dielectric on the second dielectric, the third dielectric comprising silicon nitride.
Example 30 includes the subject matter of any of Examples 28 and 29, and further including forming a conductive connection between the source or drain and the FET gate, wherein the conductive connection is formed in direct contact with the second dielectric.
Example 31 includes the subject matter of any of Examples 28-30, and further including forming a third dielectric formed within a recess in the second dielectric, the third dielectric comprising silicon nitride.
Example 32 includes the subject matter of any of Examples 28-31, and further including forming the second dielectric below and in contact with a conductive material connecting the source or drain to the gate.
Example 33 includes the subject matter of any of Examples 28-32, and wherein the source or drain is a source or drain of a first FET of a static random access memory (SRAM) cell and the gate is a gate of a second FET of the SRAM cell.
Example 34 includes the subject matter of any of Examples 28-33, and wherein the source or drain is a source or drain of a transistor and the gate is a gate of the same transistor.
Example 35 includes the subject matter of any of Examples 28-34, and wherein the second dielectric has an atomic percentage of nitrogen that is less than 20%.
Example 36 includes the subject matter of any of Examples 28-35, and wherein the second dielectric has an atomic percentage of carbon that is greater than 5%.
Example 37 includes the subject matter of any of Examples 28-36, and wherein the second dielectric has an atomic percentage of oxygen that is greater than 20%.
Example 38 includes the subject matter of any of Examples 28-37, and further including forming a third dielectric in between and in contact with the source or drain and the second dielectric.
Example 39 includes the subject matter of any of Examples 28-38, and further including forming a nitride liner in contact with the source or drain and the third dielectric.
Example 40 includes the subject matter of any of Examples 28-39, and further including forming an integrated circuit die comprising the source or drain, the first dielectric, and the second dielectric.
Example 41 includes the subject matter of any of Examples 28-40, and further including coupling a circuit board to the integrated circuit die.
Example 42 includes the subject matter of any of Examples 28-41, and further including coupling at least one of a network interface, battery, or memory to the integrated circuit die.
