Claims
- 1. A process of fabricating a semiconductor device package comprising:
providing a semiconductor wafer comprising a plurality of dice separated by scribe lines, each die comprising a semiconductor device, a surface of a front side of each die comprising a passivation layer and at least one connection pad; attaching a conductive substrate to a back side of the wafer; cutting through the wafer along a scribe line to form a first cut, the first cut exposing the substrate and a side edge of a die, a kerf of the first cut having a first width W1; forming a metal layer which extends from the portion of the conductive substrate exposed by the first cut, along the side edge of the die, and onto at least a portion of the passivation layer; cutting through the conductive substrate along a line that corresponds to the scribe line to form a second cut, a kerf of the second cut having a second width W2 that is smaller than the first width W1 such that at least a portion of the metal layer remains on the side edge of the die and forms a part of a conductive path between the conductive substrate and a location on the front side of the die.
- 2. The process of claim 1 further comprising thinning the semiconductor wafer before attaching a conductive substrate to a back side of the wafer.
- 3. The process of claim 2 wherein thinning the semiconductor wafer comprises grinding the back side of the wafer.
- 4. The process of claim 2 wherein thinning the semiconductor wafer comprises lapping the back side of the wafer.
- 5. The process of claim 2 wherein thinning the semiconductor wafer comprises etching the back side of the wafer.
- 6. The process of claim 1 wherein attaching a conductive substrate to a back side of the wafer comprises using a conductive cement.
- 7. The process of claim 1 wherein the conductive substrate is made of a material selected from the group consisting of copper and aluminum.
- 8. The process of claim 1 wherein cutting through the wafer along the scribe line comprises sawing.
- 9. The process of claim 1 wherein cutting through the wafer along the scribe line comprises photolithographic patterning and etching.
- 10. The process of claim 1 wherein forming a metal layer comprises sputtering a first metal sublayer and sputtering a second metal sublayer over the first metal sublayer.
- 11. The process of claim 10 wherein the first metal sublayer comprises titanium and the second metal sublayer comprises aluminum.
- 12. The process of claim 11 wherein forming a first metal layer comprises plating a third metal sublayer on the second metal sublayer.
- 13. The process of claim 12 wherein the third metal sublayer comprises nickel.
- 14. The process of claim 13 wherein forming a first metal layer comprises plating a fourth metal sublayer on the third metal sublayer.
- 15. The process of claim 14 wherein the fourth metal sublayer comprises gold.
- 16. The process of claim 1 wherein forming a metal layer comprises:
depositing a metal sublayer on the front side of the die, the side edge of the dice and the exposed portion of the conductive substrate; depositing a mask layer; patterning the mask layer, removing a portion of the mask layer so as form an opening that exposes a first portion of the metal sublayer, a remaining portion of the mask layer covering a second portion of the metal sublayer, the second portion of the metal sublayer being in contact with the conductive substrate, and the side edge of the die; removing the first portion of the metal sublayer; and removing the remaining portion of the mask layer.
- 17. The process of claim 16 wherein depositing the metal sublayer comprises sputtering.
- 18. The process of claim 16 wherein forming a metal layer comprises plating a second metal sublayer over the metal sublayer.
- 19. The process of claim 1 further comprising forming at least one solder post on at least a part of the metal layer.
- 20. The process of claim 1 further comprising forming at least one solder ball on at least a part of the metal layer.
- 21. The process of claim 20 wherein forming at least one solder ball comprises screen-printing.
- 22. The process of claim 20 wherein forming at least one solder ball comprises solder jetting.
- 23. The process of claim 1 further comprising forming at least one conductive polymer ball on at least a part of the metal layer.
- 24. The process of claim 1 wherein cutting through the conductive substrate along the scribe line comprises sawing.
- 25. The process of claim 1 further comprising cutting through the wafer and the conductive substrate in a direction perpendicular to the first and second cuts to separate the dice.
- 26. The process of claim 25 wherein cutting through the wafer and the conductive substrate comprises photolithographic patterning and etching.
- 27. The process of claim 1 wherein the semiconductor device is a MOSFET and the front side of the die comprises a source connection pad and a gate connection pad, the conductive substrate being in contact with a drain terminal on the back side of the die, a drain portion of the metal layer being in contact with the conductive substrate, and wherein the metal layer also includes a source portion in contact with the source connection pad and a gate portion in contact with the gate connection pad, the source, gate and drain portions of the metal layer being electrically insulated from each other.
- 28. The process of claim 1 wherein the semiconductor device comprises a MOSFET.
- 29. The process of claim 1 wherein the semiconductor device comprises a diode.
- 30. The process of claim 1 wherein the semiconductor device comprises a JFET.
- 31. The process of claim 1 wherein the semiconductor device comprises a bipolar transistor.
- 32. The process of claim 1 wherein the semiconductor device comprises an IC.
- 33. A process of fabricating a package for a power MOSFET comprising:
providing a semiconductor wafer having a front side and a back side and comprising a plurality of dice separated by scribe lines, each die comprising a power MOSFET, a surface of a front side of a die comprising a passivation layer, a gate connection pad and a source connection pad, a back side of the die comprising a drain terminal; attaching a conductive substrate to the back side of the wafer; cutting through the semiconductor wafer from the front side of the wafer in the scribe line area to form a first cut, the first cut having a first kerf W1 and exposing a part of the conductive substrate; forming a gate metal layer in electrical contact with the gate connection pad; forming a source metal layer in electrical contact with the source connection pad, the gate and source metal layers being electrically insulated from each other; forming a drain metal layer, the drain metal layer contacting the exposed part of the conductive substrate in an area of contact and extending along an edge of the die and onto the passivation layer, the drain metal layer being electrically insulated from the source and gate metal layers; cutting through the conductive substrate in the scribe line area to form a second cut having a second kerf W2 that is less than the first kerf W1, the second cut leaving in place the area of contact between the drain metal layer and the conductive substrate; and cutting through the wafer and the conductive substrate in a direction perpendicular to the first and second cuts to separate the dice.
- 34. A process for making an electrical connection between a first side of a semiconductor die and a location on a second side of the semiconductor die, the process commencing while the die is a part of a semiconductor wafer, the process comprising:
attaching a conductive substrate to the first side of the wafer; cutting through the semiconductor wafer from the second side of the wafer to expose a part of the conductive substrate; forming a metal layer extending laterally from the location on the second side of the die along an edge of the die to the exposed part of the conductive substrate; and cutting through the conductive substrate while leaving intact a region of contact between the metal layer and the conductive substrate.
- 35. The process of claim 34 wherein a first kerf formed by cutting through the wafer is wider than a second kerf formed by cutting through the conductive substrate.
- 36. The process of claim 34 wherein cutting through the wafer comprises sawing.
- 37. The process of claim 34 wherein cutting through the conductive substrate comprises sawing.
- 38. A package for a semiconductor device comprising:
a die containing a semiconductor device, a front side of the die comprising a passivation layer and at least one connection pad, the connection pad being in electrical contact with the semiconductor device; a conductive plate attached to a back side of the die, the conductive plate extending beyond a side edge of the die to form a protruding portion of the conductive plate; and a metal layer extending from the protruding portion of the conductive plate, along the side edge of the die and onto the passivation layer, the metal layer being electrically insulated from the connection pad.
- 39. The package of claim 38 comprising a second metal layer in electrical contact with the connection pad.
- 40. The package of claim 38 wherein the metal layer comprises at least two metal sublayers, second metal sublayer overlying a first metal sublayer.
- 41. The package of claim 40 wherein the first metal sublayer is sputtered and the second metal sublayer is plated.
- 42. The package of claim 39 comprising at least a first solder post in contact with the metal layer and at least a second solder post in contact with the second metal layer.
- 43. The package of claim 39 comprising at least a first solder ball in contact with the metal layer and at least a second solder ball in contact with the second metal layer.
- 44. The package of claim 39 comprising at least a first conductive polymer ball in contact with the metal layer and at least a second conductive polymer ball in contact with the second metal layer.
- 45. The package of claim 38 wherein the conductive plate has a width X2 greater than a width X1 of the die.
- 46. The package of claim 38 wherein the die comprises a vertical power MOSFET.
- 47. The package of claim 38 wherein the die comprises a diode.
- 48. The package of claim 38 wherein the die comprises a bipolar transistor.
- 49. The package of claim 38 wherein the die comprises a JFET.
- 50. The package of claim 38 wherein the die comprises a IC.
- 51. A package for a MOSFET comprising:
a semiconductor die containing a MOSFET and having a width X2, a front side of the die comprising a source connection pad in electrical contact with a source terminal and a gate connection pad in electrical contact with a gate terminal, a back side of the die comprising a drain terminal; a conductive substrate having a width X1 greater than X2 and being attached to the back side of the die and in electrical contact with the drain terminal; a drain metal layer in contact with a protruding portion of the conductive substrate and extending along an edge of the die and covering a portion of a passivation layer on the front side of the die; a source metal layer in electrical contact with the source connection pad; and a gate metal layer in electrical contact with the gate connection pad.
- 52. The package of claim 51 further comprising at least one solder post in contact with the source metal layer, at least one solder post in contact with the gate metal layer, and at least one solder post in contact with the drain metal layer.
- 53. The package of claim 51 further comprising at least one solder ball in contact with the source metal layer, at least one solder ball in contact with the gate metal layer, and at least one solder ball in contact with the drain metal layer.
- 54. The package of claim 51 further comprising at least one conductive polymer ball in contact with the source metal layer, at least one conductive polymer ball in contact with the gate metal layer, and at least one conductive polymer ball in contact with the drain metal layer.
- 55. A package for a semiconductor device comprising:
a semiconductor die containing a semiconductor device, a first side of the die comprising at least one connection pad; a conductive substrate attached to a second side of the die; a metal layer extending from the first side of the die along a side edge of the die and terminating in a flange beyond the side edge of the die, the flange being in contact with the conductive substrate, the metal layer being electrically insulated from the at least one connection pad.
- 56. The package of claim 55 wherein an edge of the conductive substrate extends laterally beyond an edge of the die
- 57. The package of claim 55 wherein the flange extends longitudinally outward from die in a direction parallel to the sides of die.
- 58. A semiconductor structure comprising:
a conductive substrate; a plurality of semiconductor dice attached to the substrate, a passivation layer on a front side of each die, rows of the dice being separated from each other by a plurality of parallel trenches; and a metal layer lining the bottoms and walls of the trenches and extending onto the passivation layer.
- 59. The structure of claim 58 wherein the front side of each die comprises at least one connection pad, the metal layer being electrically insulated from the connection pad.
- 60. The structure of claim 58 comprising a second metal layer in electrical contact with the connection pad.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to Application No. ______ [Attorney Docket No. 7573 US] and Application No. ______ [Attorney Docket No. 7791 US, both of which were filed by the same applicants on the same date as this application and both of which are incorporated herein by reference.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09395097 |
Sep 1999 |
US |
Child |
10157584 |
May 2002 |
US |