Patent Application
20240196535
This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0173923 filed in the Korean Intellectual Property Office on Dec. 13, 2022, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a circuit board, a manufacturing method thereof, and an electronic component package including the same.
A circuit board is a circuit pattern made of a conductive material such as copper on an insulating material, and as electronic devices including mobile phones in the IT field are down-sized, a method of forming a cavity on a circuit board and mounting electronic components such as an IC, or active or passive devices in the cavity, has been proposed.
Depending on a depth of the cavity of the circuit board on which the electronic component is mounted, a height of a part mounted on the circuit board among the electronic components may also change.
As the depth of the cavity of the circuit board is increased, more parts of the electronic component can be mounted in the cavity, and the entire thickness of a product packaging the electronic component and the circuit board can be reduced.
However, as the depth of the cavity of the circuit board increases, the cavity structure may interrupt the flow of the mold injected between the electronic component and the circuit board, and the circuit board may be twisted due to a difference in area of the insulating material.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the disclosure, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Embodiments are to provide a circuit board that allows a mold injected between a circuit board and an electronic component to flow smoothly, a manufacturing method thereof, and an electronic component package including the same.
However, the problem to be solved by the embodiments of the present disclosure is not limited to the above-described problem and can be variously expanded in the range of technical ideas included in the present disclosure.
A circuit board according to an embodiment includes: an insulating layer; a contact layer that is disposed on a first surface of the insulating layer; a connecting layer that includes a connecting portion embedded in the insulating layer and disposed on the contact layer; a via layer that penetrates the insulating layer and is connected to the connecting layer; and a wiring layer that is disposed on a second surface of the insulating layer opposing the first surface and connected to the via layer. The connecting portion includes a first connecting layer portion disposed on the contact layer and a second connecting layer portion disposed on the first connecting layer portion, the insulating layer includes a first portion disposed to embed the first connecting layer portion and surround the first connecting layer portion and a second portion to embed the second connecting layer portion, the insulating layer includes a cavity penetrating the second portion, and the first portion has a smaller area than the second portion.
In a plan view of the circuit board, the second connecting layer portion may have an area different from an area of the first connecting layer portion.
The connecting layer may include a plurality of the connecting portions and the insulating layer may include a plurality of the first portions.
The first portions may be spaced apart from each other and disposed independently.
The contact layer may include a contact pad corresponding to the connecting portion.
In a plan view of the circuit board, the contact pad may have an area larger than that of the first connecting layer portion.
The circuit board may further include a solder resist layer including a solder resist disposed to surround the contact pad on the first surface of the insulating layer.
The contact pad may have a circular or quadrangular shape in a plan view of the circuit board.
The solder resist may have a circular or quadrangular loop shape.
The second connecting layer portion may contain a metal.
The via layer may be tapered in a direction towards the connecting layer.
An electronic component package according to an embodiment includes: a first circuit board; a second circuit board connected to the first circuit board; and an electronic component mounted on one surface of the second circuit board. The first circuit board includes: an insulating layer; a contact layer that is disposed on a first surface of the insulating layer; a connecting layer that includes a connecting portion embedded in the insulating layer and disposed on the contact layer; a via layer that penetrates the insulating layer and is connected to the connecting layer; and a wiring layer that is disposed on a second surface of the insulating layer opposing the first surface and connected to the via layer. The connecting portion includes a first connecting layer portion disposed on the contact layer and a second connecting layer portion disposed on the first connecting layer portion, the insulating layer includes a first portion disposed to embed the first connecting layer portion and surround the first connecting layer portion and a second portion to embed the second connecting layer portion, the insulating layer includes a cavity penetrating the second portion, and the first portion has a smaller area than the second portion.
The connecting layer may include a plurality of the connecting portions and the insulating layer may include a plurality of the first portions, and the first portions may be spaced apart from each other and disposed independently.
The electronic component package may further include an encapsulant that is disposed between the first circuit board and the second circuit board and covers at least a part of the electronic component, wherein the encapsulant may be disposed in at least a part of the cavity.
The contact layer may include a contact pad corresponding to the connecting portion.
The contact pad may have a circular or quadrangular shape in a plan view of the electronic component package.
A circuit board manufacturing method according to an embodiment includes: forming a first connecting layer portion and a first sacrificial layer; forming a second connecting layer portion on a first surface of the first connecting layer portion; forming a second sacrificial layer on the first sacrificial layer to have a smaller area than the first sacrificial layer; forming an insulating layer to embed the first connecting layer portion, the second connecting layer portion, the first sacrificial layer, and the second sacrificial layer; forming a via layer through the insulating layer to be connected to the second connecting layer portion; forming a contact layer on a second surface of the first connecting layer portion opposing the first surface; and removing the first sacrificial layer and the second sacrificial layer by etching the first sacrificial layer and the second sacrificial layer.
The forming the first connecting layer portion may include forming a plurality of first connecting layer portions to be spaced apart from each other and independently disposed, and the forming the second connecting layer portion may include forming a plurality of second connecting layer portions on the first surfaces of the plurality of first connecting layer portions.
The forming the contact layer may include forming a contact pad corresponding to the first connecting layer portion.
The circuit board manufacturing method may further include forming a solder resist layer having a solder resist formed thereon to surround the contact pad on one surface of the insulating layer.
The forming the contact pad may include forming the contact pad such that the contact pad has a circular or quadrangular planar shape.
According to the embodiments, a circuit board that can suppress twist of the circuit board, improve flow characteristics in injection of a mold between the circuit board and electronic components, and enables a plating process to be performed more easily, a manufacturing method thereof, and electronic component package including the same can be provided.
Hereinafter, with reference to accompanying drawings, an embodiment of the present disclosure will be described in detail and thus a person of an ordinary skill can easily practice it in the technical field to which the present disclosure belongs. The drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. In addition, in the accompanying drawing, some constituent elements are exaggerated, omitted, or schematically shown, and the size of each constituent element does not fully reflect the actual size.
The accompanying drawing is only for easy understanding of the embodiment disclosed in this specification, and the technical idea disclosed in this specification is not limited by the accompanying drawing, and it should be understood that all changes and equivalents or substitutes included in the spirit and technical range of the present disclosure.
Terms containing ordinal numbers, such as first, second, and the like can be used to describe various configurations elements, but the constituent elements are not limited by the terms. The terms are used only for the purpose of distinguishing one constituent element from another.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, throughout the specification, the word “on” a target element will be understood to mean positioned above or below the target element, and will not necessarily be understood to mean positioned “at an upper side” based on an opposite to gravity direction.
Throughout the specification, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, constituent element, part, or combination thereof described in the specification exists, and it should be understood as not precluding the possibility of the presence or addition of and one or more other features, numbers, steps, actions, constituent elements, parts, or combinations thereof. In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.
Further, throughout the specification, the phrase “on a plane” means viewing a target portion from the top, and the phrase “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side. Throughout the specification, “connected” does not mean only when two or more constituent elements are directly connected, but also when two or more constituent elements are indirectly connected through another constituent element, or when physically connected or electrically connected, and it may include a case in which substantially integral parts are connected to each other although they are referred to by different names according to positions or functions.
Hereinafter, various embodiments and variations are described in detail with reference to drawings.
Referring to
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The circuit board 100A according to the present embodiment may be an interposer board connected to an electronic component later, but is not necessarily limited thereto.
The plurality of insulating layers IL may include a first insulating layer IL1 and a second insulating layer IL2 disposed on the first insulating layer IL1. An insulating material may be used as a material for each of the plurality of insulating layers IL, and the insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or an inorganic filler such as silica, and a reinforcing member such as glass fiber in these resins. For example, a prepreg may be used as a material for each of the plurality of insulating layers IL, but is not limited thereto, and a material that does not include a reinforcing member such as glass fiber, for example, an Ajinomoto-build up film (ABF) or the like, may be used. If necessary, a photosensitive insulating material such as photoimageable dielectric (PID) may be used as a material for each of the plurality of insulating layers IL.
The cavity CV may be disposed on a first surface of the first insulating layer IL1. The cavity CV may be formed through an etching process. In addition, when the circuit board 100A is an interposer board and is connected to a board of an electronic component later, a sealing material (400; refer to
The plurality of wiring layers ML may include a first wiring layer ML1 disposed on a second surface that faces the first surface of the first insulating layer IL1, and a second wiring layer ML2 disposed on one surface of the second insulating layer IL2. The first wiring layer ML1 may be embedded in the second insulating layer IL2. Each of the plurality of wiring layers ML may transmit a signal of the circuit board.
A metal material may be used as a material for each of the plurality of wiring layers ML. The metal material may include copper (Cu), aluminum (AI), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the plurality of wiring layers ML may perform various functions according to a design such as a ground pattern, a power pattern, and a signal pattern. Each of these patterns may have a line shape, a plane shape, or a pad shape. In the case of a wiring layer positioned at the outermost layer among a plurality of wiring layers ML, it may function as a pad for connection with other substrates or components. For example, the second wiring layer ML2 positioned on the outermost layer of the circuit board may function as a pad for connection with other boards or components.
Referring to
The plurality of via layers MV may include a first via layer MV1 disposed within the first insulating layer IL1 and a second via layer MV2 disposed within the second insulating layer IL2.
The first via layer MV1 may pass through the first insulating layer IL1 and be connected to the connecting layer CL and the first wiring layer ML1. The first via layer MV1 may electrically connect the connecting layer CL and the first wiring layer ML1.
The second via layer MV2 may pass through the second insulating layer IL2 and be connected to the first wiring layer ML1 and the second wiring layer ML2. The second via layer MV2 may electrically connect the first wiring layer ML1 and the second wiring layer ML2.
A metal material may be used as a material for each of the plurality of via layers MV. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the plurality of via layers MV may include a signal via, a ground via, a power via, and the like depending on designs. In each via of the plurality of via layers MV, each via hole may be completely filled with a metal material, or a metal material may be formed along a wall surface of the via hole. Each of the plurality of via layers MV may be formed through a plating process, such as an additive process (AP), a semi-AP (SAP) process, a modified SAP (MSAP) process, or a tenting (TT) process. Each of the plurality of via layers MV may include a seed layer, which is an electroless plating layer, and an electroplating layer formed based on the seed layer. Each via of the plurality of via layers MV may have a tapered shape in which a width of a top surface is greater than a width of a bottom surface.
Referring to
The contact layer CTL may be disposed on the first surface of the first insulating layer IL1. The contact layer CTL may include a contact pad CTP having conductivity corresponding to the connecting portion CP. The contact pad CTP may be formed through a plating process. Referring to
Each of the plurality of solder resist layers SL may be disposed on a portion of the plurality of insulating layer IL to cover a portion of the contact pad CTP or the plurality of wiring layers ML to prevent unnecessary short circuits. Each of the plurality of solder resist layers SL may include a photosensitive resin material.
The first solder resist layer SL1 may be disposed on the first surface of the first insulating layer IL1. The first solder resist layer SL1 may be disposed to expose a part of the contact pad CTP. The first solder resist layer SL1 may include a solder resist SR. The solder resist SR may be disposed on the first surface of the first insulating layer IL1 to surround the contact pad CTP. Referring to
The second solder resist layer SL2 may be disposed on the second insulating layer IL2. The second solder resist layer SL2 may be disposed to expose a portion of the second wiring layer ML2.
The connecting layer CL may be embedded in the first insulating layer IL1. The connecting layer CL may include a connecting portion CP positioned on the contact layer CTL. The connecting portion CP may include a first connecting layer portion CLP1 disposed on the contact layer CTL and a second connecting layer portion CLP2 disposed on the first connecting layer portion CLP1. The first connecting layer portion CLP1 and the second connecting layer portion CLP2 may have different flat areas. For example, the first connecting layer portion CLP1 may have a larger flat area than the second connecting layer portion CLP2. The contact pad CTP may be disposed on the first connecting layer portion CLP1 and may have a larger flat area than the first connecting layer portion CLP1. The first connecting layer portion CLP1 and the second connecting layer portion CLP2 may include a metal.
The first insulating layer IL1 may include a first portion IL1a filling the first connecting layer portion CLP1 and a second portion IL1b filling the second connecting layer portion CLP2. The cavity CV may be formed in a stepped groove shape on one surface of the first portion IL1a and one surface of the second portion IL1b. In addition, the cavity CV may have a rectangular planar shape. The first portion IL1a may be disposed to surround the first connecting layer portion CLP1, and may be independently disposed on the second portion IL1b while being spaced apart from each other. Specifically, the first portion IL1a may be independently disposed on the second portion IL1b along the circumference of the cavity CV while being spaced apart from each other. Also, the first portion IL1a may have a smaller flat area than the second portion IL1b.
Referring to
In the circuit board according to the present embodiment, although a depth of the cavity formed on the circuit board increases, the insulating material and the solder resist may be formed only in an area adjacent to a protruded contact pad, and thus bending of the circuit board can be suppressed, and it is possible to improve the flow characteristics in injection of a mold between a mold and electronic parts.
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Hereinafter, one substrate portion SUB separated from the carrier substrate CS will be described.
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The first sacrificial layer SF1 and the second sacrificial layer SF2 disposed in the region where the cavity CV is to be formed may be etched and removed using the first mask layer MSK1 and the second mask layer MSK2 as etching masks. Accordingly, the cavity CV having a stepped groove shape may be formed on one surface of the first insulating layer IL1. After that, the first mask layer MSK1 and the second mask layer MSK2 are removed, and a circuit board as shown in
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The electronic component package 1000A according to an embodiment may include a first circuit board 100A, a second circuit board 200 connected to the first circuit board 100A, an electronic component 300 mounted on one surface of the second circuit board 200, an encapsulant 400 disposed between the first circuit board 100A and the second circuit board 200 to fill a cavity CV and to cover at least a part of the electronic component 300, a conductivity member 510 electrically connecting the first circuit board 100A and the second circuit board 200, an electrode that electrically connects the second circuit board 200 and the electronic component 300, and an underfill 600.
The second circuit board 200 is a circuit board on which the electronic component 300 is mounted, and may include an insulating layer, a wiring layer, a via layer, and a solder resist layer.
The electronic component 300 may be an integrated circuit (IC) die in which hundreds to millions of devices or more are integrated into a single chip. For example, the electronic component 300 is a processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, and specifically, it may be an application processor (AP), but is not limited thereto. In addition, it may be memory such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, an analog-digital converter, or a logic such as an application-specific IC (ASIC). If necessary, the electronic component 300 may be a chip-type passive component, for example, a chip-type capacitor such as a multi-layer ceramic capacitor (MLCC), a chip-type inductor such as a power inductor (PI), and the like. The electronic component 300 may be covered by the encapsulant 400, and at least one surface may be in physical contact with the encapsulant 400.
The encapsulant 400 may be disposed on one surface of the first insulating layer IL1 to cover at least a portion of one surface of the first insulating layer IL1, one surface of the second circuit board 200, and an outer surface of the electronic component 300. In addition, the encapsulant 400 may fill at least a part of the cavity CV, and may cover at least a part of an upper surface of the electronic component 300. For example, the encapsulant 400 may physically contact at least a portion of each of the top, bottom, and side surfaces of the electronic component 300. Since the encapsulant 400 has fluidity in a state before hardening, it flows along the outer surface of the electronic component 300 and the surface of the first insulating layer IL1 to fill the inside of the cavity CV. In this case, although a depth of the cavity CV increases, an insulating material and the solder resist may be formed only in a region adjacent to a protruded contact pad CTP, such as the first portion IL1a of the first insulating layer IL1 and the first solder resist layer SL1. Therefore, it is possible to suppress the twist of the circuit board and improve the flow characteristic in injection of a mold between the circuit board and the electronic component.
The insulating material may be used as a material of the encapsulant 400, and a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide may be used as the insulating material. In addition, those resins may contain inorganic fillers such as silica. For example, an Ajinomoto build-up film (ABF) may be used as a material for the encapsulant 400. The ABF may be provided in a resin-coated copper (RCC) form, but is not limited thereto. If necessary, a photosensitive material such as a photoimageable dielectric (PIE) may be used. In addition, the encapsulant 400 may be a known epoxy molding compound (EMC), but is not limited thereto.
The conductivity member 510 may be disposed in at least a part of an opening of the second circuit board 200. The conductivity member 510 may physically and/or electrically connect the second circuit board 200 with the outside. For example, the conductivity member 510 may electrically connect an exposed wiring layer of the second circuit board 200 and the contact pad CTP of the contact layer CTL. The conductivity member 510 may be formed of tin (Sn) or an alloy containing tin (Sn), for example, solder, but is not limited thereto. For example, the conductivity member 510 may have a pillar shape in which a plurality of balls are combined, but is not limited thereto, and may be a metal post of a land, a ball, a pin, or a pillar shape.
The underfill 600 is a material filled between the electronic component 300 mounted on the cavity CV of the second circuit board 200 and the second circuit board 200, and may fix the electronic component 300 in the cavity CV. In particular, when a gap is generated between one surface of the electronic component 300 and the second circuit board 200 due to protrusion formation of the electrode 700, the underfill 600 may be charged in the gap. The electronic component 300 may be fixed by the underfill 600.
Referring to
A conductivity member 520 may be disposed at at least a part of an opening of the second circuit board 200. The conductivity member 520 may physically and/or electrically connect the second circuit board 200 with the outside. For example, the conductivity member 520 may electrically connect an exposed wiring layer of the second circuit board 200 and the contact pad CTP of the contact layer CTL. The conductivity member 520 may be formed of tin (Sn) or an alloy containing tin (Sn), for example, solder, but is not limited thereto. For example, the conductivity member 520 may be formed of a Cu core ball (CCB), but is not limited thereto, and may be a metal post of a land, a ball, a pin, or a pillar shape.
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While this invention has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0173923 | Dec 2022 | KR | national |
