CIRCUIT SUBSTRATE, CHIP, SERIES CIRCUIT, CIRCUIT BOARD AND ELECTRONIC DEVICE

Description

This application claims priority of Chinese Patent Application “Circuit substrate, chip, and electronic device” with Application No. 201810312401.9, filed with the State Intellectual Property Office of P. R. China on Apr. 9, 2018 and Chinese Patent Application “Circuit substrate, chip, and electronic device” with Application No. 201810312436.2, filed with the State Intellectual Property Office of P. R. China on Apr. 9, 2018, the entire contents of all of which are incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present invention relates to the field of chip design technology, more particularly, relates to a circuit substrate, a chip, a series circuit, a circuit board, and an electronic device.

BACKGROUND

Generally, as shown in FIG. 1, a projected view of various components on a metal layer of a traditional circuit substrate is illustrated. In particular, it can be seen from FIG. 1 that, the traditional circuit substrate may include an insulation layer 10 (not shown), a metal layer 11 configured on a first surface of the insulation layer 10, a plurality of power supply input soldering pads 12 configured on a second surface of the insulation layer 10 facing away from the metal layer 11, a plurality of power supply output soldering pads 13 (i.e., VSS pad, also known as GND pad), and a plurality of signal input/output soldering pads 14 (i.e., IO pad).

Specifically, a plurality of soldering dots are often configured in an area of the plurality of power supply output soldering pads 13 projected on the metal layer 11, such as a plurality of power supply input soldering dots 111 (i.e., VDD bump) one-to-one connected to a plurality of die input soldering dots, and a plurality of power supply output soldering dots 112 (i.e., VSS bump) one-to-one connected to a plurality of die output soldering dots. Moreover, it can be seen from FIG. 1 that, the existing power supply input soldering pads 12 are often configured on the side of the power supply output soldering pads 13 to supply a voltage to the power supply soldering dots on the metal layer 11, thereby ensuring normal operation of the die. However, according to the formula R=ρL/S (where R represents a resistance value, p represents a resistivity, L represents a distance, and S represents an area), in this case, because distances between the soldering dots on the metal layer 11 and the power supply input soldering pads 12 vary substantially, voltages at the soldering dots on the metal layer 11 vary substantially, thereby unable to achieve a voltage uniformity.

In other words, there exists a problem of variable voltages at the soldering dots on the metal layer of the existing circuit substrate.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure provides a circuit substrate. The circuit substrate includes: an insulation layer; a metal layer disposed on a first surface of the insulation layer; and a first soldering pad and a second soldering pad disposed on a second surface of the insulation layer facing away from the metal layer. Shortest distances between soldering dots on the metal layer and a projected area of the first soldering pad on the metal layer are all smaller than a distance threshold. The soldering dots on the metal layer are one-to-one corresponding to soldering dots on a corresponding die. The shortest distance is a minimum value of vertical distances between the soldering dots on the metal layer and a side edge of the projected area of the first soldering pad on the metal layer. The side edge is adjacent to a projected area of the second soldering pad on the metal layer.

In one embodiment, the distance threshold is the farthest distance between the soldering dots on the metal layer and the projected area of the first soldering pad on the metal layer. The farthest distance is a maximum value of vertical distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer.

In one embodiment, the first soldering pad is a power supply input soldering pad of the circuit substrate. The second soldering pad is a power supply output soldering pad of the circuit substrate.

In one embodiment, that the shortest distances between the soldering dots on the metal layer and the projected area of the first soldering pad on the metal layer are all smaller than the distance threshold includes: that the shortest distances between the power supply input soldering dots on the metal layer and the projected area of the first soldering pad on the metal layer are all smaller than the distance threshold.

In one embodiment, the first soldering pad is connected to the metal layer through a first through-hole. The distances between the soldering dots on the metal layer and a position of the first through-hole on the metal layer are smaller than the distance threshold.

In one embodiment, an area occupied by the projected area of the second soldering pad on the metal layer is no smaller than an area threshold.

In one embodiment, the first soldering pad includes a first soldering sub-pad and a second soldering sub-pad. The first soldering sub-pad and the second soldering sub-pad are disposed on a first side and a second side of the second soldering pad, respectively. The first side and the second side are opposite to each other.

In one embodiment, the projected area of the first soldering pad on the metal layer is a first projected area and the projected area of the second soldering pad on the metal layer is a second projected area. The distance threshold is the greater of a first farthest distance between the soldering dots on the metal layer and the first projected area and a second farthest distance between the soldering dots on the metal layer and the second projected area.

In one embodiment, the first soldering pad includes the first soldering sub-pad, the second soldering sub-pad, and a third soldering sub-pad. The first soldering sub-pad and the second soldering sub-pad are disposed on the first side and the second side of the second soldering pad, respectively. The third soldering sub-pad are disposed on a third side or a fourth side of the second soldering pad. The third side and the fourth side of the second soldering pad are opposite to each other.

In one embodiment, the first soldering pad further includes a fourth soldering sub-pad. The fourth soldering sub-pad is disposed on the fourth side of the second soldering pad.

In one embodiment, the projected area of the first soldering sub-pad on the metal layer is a third projected area, the projected area of the second soldering sub-pad on the metal layer is a fourth projected area, and the projected area of the third soldering sub-pad on the metal layer is a fifth projected area. The distance threshold is the greatest of a third farthest distance between the soldering dots on the metal layer and the third projected area, a fourth farthest distance between the soldering dots on the metal layer and the fourth projected area, and a fifth farthest distance between the soldering dots on the metal layer and the fifth projected area.

In one embodiment, the projected area of the first soldering pad on the metal layer is a concave surface. The projected area of the second soldering pad on the metal layer is a convex surface. A concave portion of the concave surface encloses a convex portion of the convex surface.

In one embodiment, when the first soldering pad is disposed on at least two outer sides of the second soldering pad, the projected area of the first soldering pad on the metal layer is the concave surface, the projected area of the second soldering pad on the metal layer is the convex surface, and the concave portion of the concave surface encloses the convex portion of the convex surface.

In one embodiment, the projected area of the first soldering pad on the metal layer encloses the projected area of the second soldering pad on the metal layer.

In one embodiment, when the first soldering pad is disposed on at least two outer sides of the second soldering pad, the projected area of the first soldering pad on the metal layer encloses the projected area of the second soldering pad on the metal layer.

In one embodiment, the projected area of the second soldering pad on the metal layer encloses the projected area of the first soldering pad on the metal layer.

In one embodiment, when the first soldering pad is disposed on at least two outer sides of the second soldering pad, the projected area of the second soldering pad on the metal layer encloses the projected area of the first soldering pad on the metal layer.

In one embodiment, the first soldering pad is disposed on at least one surface or at least two sides of the second soldering pad.

In one embodiment, the circuit substrate further includes a second insulation layer disposed between the first soldering pad and the second soldering pad. The first soldering pad is disposed on a first surface of the second soldering pad facing toward the metal layer.

In one embodiment, the circuit substrate further includes a second insulation layer disposed between the first soldering pad and the second soldering pad. The first soldering pad is disposed on a second surface of the second soldering pad facing away from the metal layer.

In one embodiment, disposing the first soldering pad on at least one surface of the second soldering pad refers to that the projected area of the first soldering pad and the projected area of the second soldering pad at least partially overlap.

In one embodiment, when the first soldering pad is disposed on at least one surface of the second soldering pad, the shortest distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are no greater than the distance threshold. The side edge is adjacent to the projected area of the second soldering pad on the metal layer.

In on embodiment, that the shortest distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are no greater than the distance threshold includes: that the shortest distances between the power supply input soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are no greater than the distance threshold.

In one embodiment, the first soldering pad is connected to the metal layer through a first through-hole. When the first soldering pad is disposed on at least one surface of the second soldering pad, the distances between the soldering dots on the metal layer and a position of the first through-hole on the metal layer are no greater than the distance threshold.

In one embodiment, when the first soldering pad is disposed on at least two sides of the second soldering pad, the shortest distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are smaller than the distance threshold. The side edge is adjacent to the projected area of the second soldering pad on the metal layer.

In one embodiment, that the shortest distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are smaller than the distance threshold includes: that the shortest distances between the power supply input soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are smaller than the distance threshold.

In one embodiment, the first soldering pad is connected to the metal layer through a first through-hole. When the first soldering pad is disposed on at least two sides of the second soldering pad, the distances between the soldering dots on the metal layer and a position of the first through-hole on the metal layer are smaller than the distance threshold.

In one embodiment, an area occupied by the projected area of the second soldering pad on the metal layer is no smaller than an area threshold.

Another aspect of the present disclosure provides another circuit substrate. The circuit substrate includes: a first insulation layer; a metal layer disposed on a first surface of the first insulation layer; a first soldering pad; and a second soldering pad disposed on a second surface of the first insulation layer facing away from the metal layer. At least two soldering dots are disposed in a projected area of the second soldering pad on the metal layer and are one-to-one corresponding to soldering dots on a corresponding die. The first soldering pad is disposed on at least one surface or at least two sides of the second soldering pad.

In one embodiment, the first soldering pad is a power supply input soldering pad of the circuit substrate; and the second soldering pad is a power supply output soldering pad of the circuit substrate.

In one embodiment, the first soldering pad includes a first soldering sub-pad and a second soldering sub-pad; and the first soldering sub-pad and the second soldering sub-pad are disposed on a first side and a second side of the second soldering pad, respectively. The first side and the second side are opposite to each other.

In one embodiment, the first soldering pad further includes a third soldering sub-pad. The third soldering sub-pad is disposed on a third side of the second soldering pad.

In one embodiment, the first soldering pad further includes a fourth soldering sub-pad. The fourth soldering sub-pad is disposed on a fourth side of the second soldering pad. The fourth side is opposite to the third side.

In one embodiment, a second insulation layer disposed between the first soldering pad and the second soldering pad. The first soldering pad is disposed on a first surface of the second soldering pad facing toward the metal layer.

In one embodiment, a second insulation layer disposed between the first soldering pad and the second soldering pad. The first soldering pad is disposed on a second surface of the second soldering pad facing away from the metal layer.

In one embodiment, disposing the first soldering pad on at least one surface of the second soldering pad refers to: that the projected area of the first soldering pad and the projected area of the second soldering pad at least partially overlap.

In one embodiment, that the shortest distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are no greater than the distance threshold includes: that the shortest distances between the power supply input soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are no greater than the distance threshold.

In one embodiment, an area occupied by the projected area of the second soldering pad on the metal layer is no smaller than an area threshold.

Another aspect of the present disclosure provides a chip. The chip includes: a die; and a disclosed circuit substrate. A die is disposed on a surface of an insulation layer facing away from a metal layer. Soldering dots on the metal layer are one-to-one connected to soldering dots on the die, respectively.

Another aspect of the present disclosure provides a series circuit. The series circuit includes: at least two chip sets connected in parallel with each other. Each chip set includes at least two disclosed chips, connected in series with each other.

Another aspect of the present disclosure provides a circuit board. The circuit board includes a disclosed series circuit.

Another aspect of the present disclosure provides an electronic device. The electronic device includes a disclosed circuit board.

Another aspect of the present disclosure provides another electronic device. The electronic device includes: a body of the electronic device; and at least one disclosed chip.

The beneficial effects of the present disclosure are as follows.

The embodiments of the present disclosure discloses a circuit substrate, a chip, a series circuit, a circuit board, and an electronic device. The circuit substrate includes: an insulation layer; a metal layer disposed on a first surface of the insulation layer; and a first soldering pad and a second soldering pad disposed on a second surface of the insulation layer facing away from the metal layer. Shortest distances between soldering dots on the metal layer and a projected area of the first soldering pad on the metal layer are all smaller than a distance threshold. The soldering dots on the metal layer are one-to-one corresponding to soldering dots on a corresponding die. Compared with the existing technology, in the embodiments of the present disclosure, distances between the soldering dots on the metal layer and the projected area of the first soldering pad on the metal layer are substantially short, and a corresponding resistance is substantially small. Thus, voltages at the soldering dots on the metal layer are balanced with each other, thereby ensuring the normal operation of the circuit substrate

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, drawings used in the description of the embodiments will be briefly described below. The drawings in the following description are only some embodiments of the present invention. Based on the drawings, other drawings may also be obtained by those of ordinary skill in the art without inventive work.

FIG. 1 illustrates a projected view of various components on a metal layer of a traditional circuit substrate;

FIG. 2A illustrates a cross-sectional view of an exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 2B illustrates a cross-sectional view of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 2C illustrates a cross-sectional view of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 3 illustrates a projected view of various components on a metal layer of an exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 4 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 5 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 6 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 7 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 8A illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 8B illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 9A illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 9B illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 10 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 11 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 12 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 13 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 14 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 15 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 16 illustrates a cross-sectional view of another exemplary circuit substrate according to disclosed embodiments of the present disclosure;

FIG. 17 illustrates a cross-sectional view of an exemplary chip according to disclosed embodiments of the present disclosure; and

FIG. 18 illustrates a structural schematic diagram of an exemplary electronic device according to disclosed embodiments of the present disclosure.

DETAILED DESCRIPTION

To make the objectives, technical solutions, and advantages of the present invention clearer, the following further describes the embodiments of the present invention in details with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of the present disclosure, rather than all of them. Based on the embodiments of the present disclosure, those of ordinary skill in the art may obtain other embodiments without creative work, which shall fall within the scope of the present disclosure.

Embodiments

To ensure that the voltages at various soldering dots on a circuit substrate are balanced with each other such that the entire circuit substrate can operate properly, the present disclosure provides the circuit substrate. FIG. 2A illustrates a cross-sectional view of an exemplary circuit substrate according to the present disclosure. The cross-sectional view may be any cross-sectional view that can clearly represent relative positions between various components on the circuit substrate and is not limited by the present disclosure.

Specifically, as shown in FIG. 2A, the circuit substrate provided by the embodiment of the present disclosure may include an insulation layer 20, a metal layer 21, a first soldering pad 22, and a second soldering pad 23. The metal layer 21 is disposed on a first surface of the insulation layer 20. The first soldering pad 22 and the second soldering pad 23 are disposed on a second surface of the insulation layer 20 facing away from the metal layer 21. A shortest distance between the soldering dots (211 or 212 in FIG. 2A) on the metal layer 21 and a projected area of the first soldering pad 22 on the metal layer 21 is smaller than a distance threshold (L_maxin FIG. 2A). The soldering dots on the metal layer 21 are one-to-one corresponding to soldering dots on a die. The shortest distance is a minimum value (e.g., L3 in FIG. 1) of vertical distances between the soldering dots and a side edge of the projected area of the first soldering pad 22 on the metal layer 21. In this case, the side edge of the projected area of the first soldering pad 22 on the metal layer 21 is a side edge adjacent to the projected area of the second soldering pad 23 on the metal layer 21.

Optionally, the distance threshold is a farthest distance from the soldering dots to the projected area of the first soldering pad 22 on the metal layer 21. The farthest distance is a maximum value of vertical distances between the soldering dots and a side edge of the projected area of the first soldering pad 22 on the metal layer 21. The side edge is adjacent to the projected area of the second soldering pad 23 on the metal layer 21.

It should be noted that, in one embodiment, the threshold distance may be a maximum value of distances between the soldering dots and the center of the first soldering pad 22 (practically, the center of the projected area of the first soldering pad 22 on the metal layer 21). The threshold distance may also be a maximum value of vertical distances between the center of a shape formed by the soldering dots (practically, the center of the projected area of the die on the metal layer 21) and the side edge of the projected area of the first soldering pad 22 on the metal layer 21. The specific value may be configured according to actual requirements to be, e.g., 5 mm, 8 mm, 1 cm or 2 cm as long as the actual requirements are satisfied. The present disclosure does not limit the distance threshold.

That is to say that, in the embodiment of the present disclosure, the shortest distances between the soldering dots on the metal layer 21 and the projected area of the first soldering pad 22 on the metal layer 21 are all smaller than the distance threshold. As such, equivalent resistances between the first soldering pad 22 and the soldering dots on the metal layer 21 are substantially small, and voltage drops between the first soldering pad 22 and the soldering dots on the metal layer 21 are substantially small. Thus, the voltages at the soldering dots on the metal layer 21 are ensured to be balanced between each other and the normal operation of the circuit substrate is ensured.

Optionally, in one embodiment, at least one power supply input soldering dot 211 and at least one power supply output soldering dot 212 may be disposed on the metal layer 21. Further, the power supply input soldering dot 211 is often physically or electrically connected to a corresponding input soldering dot (i.e., VDD bump) of the die and the power supply output soldering dot 212 is often physically or electrically connected to a corresponding output soldering dot (i.e., VSS bump) of the die.

It should be noted that, in one embodiment, the power supply input soldering dot 211 and the power supply output soldering dot 212 in different areas may correspond to different dies. For example, a plurality of soldering dots (including the power supply input soldering dots 211 and the power supply output soldering dots 212) in the upper left corner may correspond to a first die. A plurality of soldering dots (including the power supply input soldering dots 211 and the power supply output soldering dots 212) in the upper right corner may correspond to a second die. A plurality of soldering dots (including the power supply input soldering dots 211 and the power supply output soldering dots 212) in the lower left corner may correspond to a third die. A plurality of soldering dots (including the power supply input soldering dots 211 and the power supply output soldering dots 212) in the lower right corner may correspond to a fourth die.

Of course, it should be noted that, a plurality of cores may be configured on a die. Each core may include at least one power supply input soldering dot 211 and an equal number of the power supply output soldering dots 212. As such, the power supply input soldering dots 211 and the power supply output soldering dots 212 in different areas may correspond to different cores in a same die. For example, a plurality of soldering dots (including the power supply input soldering dots 211 and the power supply output soldering dots 212) in the upper left corner may correspond to a first core. A plurality of soldering dots (including the power supply input soldering dots 211 and the power supply output soldering dots 212) in the upper right corner may correspond to a second core. A plurality of soldering dots (including the power supply input soldering dots 211 and the power supply output soldering dots 212) in the lower left corner may correspond to a third core. A plurality of soldering dots (including the power supply input soldering dots 211 and the power supply output soldering dots 212) in the lower right corner may correspond to a fourth core.

In addition, the shape formed by each group of the soldering dots may be the same as the projected area of the corresponding die on the metal layer 21. Preferably, the shape formed by each group of the soldering dots may be the same as a shape formed by the soldering dots on the corresponding die. The present disclosure does limit the shape of the soldering dots.

Specifically, in one embodiment, as shown in FIG. 2A, the first soldering pad 22 may be physically or electrically connected to the power supply input soldering dots 211 through a first through-hole 24. The power supply input soldering dots 211 disposed on the metal layer 21 are connected to the metal layer 21. The second soldering pad 23 may be physically or electrically connected to the power supply output soldering dots 212 through a second through-hole 25. In practical applications, a current may flow through the first soldering pad 22, the first through-hole 24, the metal layer 21, the power supply input soldering dots 211, and the input soldering dots of the corresponding die to relevant components on the die, such as MOS transistors, etc. Then, the current may flow through the output soldering dots of the die, the power supply output soldering dots 212, the second through-hole 25, and the second soldering pad 23 to the ground.

Optionally, the first soldering pad 22 is connected to the metal layer 21 through the first through-hole 24. The distances between the soldering dots on the metal layer 21 and a position of the first through-hole 24 on the metal layer 21 are all smaller than the distance threshold.

Optionally, the first soldering pad 22 is connected to the metal layer 21 through the first through-hole 24. When the first soldering pad 22 is disposed on at least one surface of the second soldering pad 23, the distances between the soldering dots on the metal layer 21 and the position of the first through-hole 24 on the meal layer 21 are all no greater than the distance threshold.

Optionally, the first soldering pad 22 is connected to the metal layer 21 through the first through-hole 24. When the first soldering pad 22 is disposed on at least two sides of the second soldering pad 23, the distances between the soldering dots on the metal layer 21 and the position of the first through-hole 24 on the metal layer 21 are all smaller than the distance threshold.

Optionally, the distance threshold is the farthest distance between the soldering dots and the projected area of the first soldering pad 22 on the metal layer 21. The farthest distance is the maximum value of the vertical distances between the soldering dots and the side edge of the projected area of the first soldering pad 22 on the metal layer 21. The side edge is adjacent to the projected area of the second soldering pad 23 on the metal layer 21.

It should be noted that, when multiple circuit substrates (substrates configured with multiple corresponding dies) are connected in series with each other, an output voltage of the second soldering pad 23 is often non-zero and will be an input voltage of a subsequent circuit substrate. In this case, only the output voltage of the very last circuit substrate is zero. The present disclosure does not limit the configuration of multiple circuit substrates.

Further, FIG. 2B illustrates a cross-sectional view of another exemplary circuit substrate according to the present disclosure. Specifically, as shown in FIG. 2B, the circuit substrate may also include a second insulation layer 26 disposed between the first soldering pad 22 and the second soldering pad 23. The first soldering pad 22 is disposed on a first surface of the second soldering pad 23 facing toward the metal layer 21.

For example, as shown in FIG. 2B, the first soldering pad 22 is disposed between the metal layer 21 and the second soldering pad 23. The first insulation layer 20 is disposed between the metal layer 21 and the first soldering pad 22. The second insulation layer 26 is disposed between the first soldering pad 22 and the second soldering pad 23. The first through 24 is disposed through the first insulation layer 20 to transport the current between the power supply input soldering dots 211 on the metal layer 21 and the first soldering pad 22. The second through-hole 25 is disposed through the first insulation layer 20, the first soldering pad 22, and the second insulation layer 26 to transport the current between the power supply output soldering dots 212 on the metal layer 21 and the second soldering pad 23. Further description is omitted.

Further, FIG. 2C illustrates a cross-sectional view of another exemplary circuit substrate according to the present disclosure. Specifically, as shown in FIG. 2C, the circuit substrate may also include the second insulation layer 26 disposed between the first soldering pad 22 and the second soldering pad 23. The first soldering pad 22 is disposed on a second surface of the second soldering pad 23 facing away from the metal layer 21.

For example, as shown in FIG. 2C, the second soldering pad 23 is disposed between the metal layer 21 and the first soldering pad 22. The first insulation layer 20 is disposed between the metal layer 21 and the second soldering pad 23. The second insulation layer 26 is disposed between the second soldering pad 23 and the first soldering pad 22. The first through 24 is disposed through the first insulation layer 20 to transport the current between the power supply output soldering dots 212 on the metal layer 21 and the second soldering pad 23. The second through-hole 25 is disposed through the first insulation layer 20, the second soldering pad 23, and the second insulation layer 26 to transport the current between the power supply input soldering dots 211 on the metal layer 21 and the first soldering pad 22. Further description is omitted.

Optionally, disposing the first soldering pad 22 on at least one surface of the second soldering pad 23 refers to that the projected area of the first soldering pad 22 on the metal layer 21 at least partially overlaps with the projected area of the second soldering pad 23 on the metal layer 21 or that the projected area of the first soldering pad 22 on the metal layer 21 completely overlaps with the projected area of the second soldering pad 23 on the metal layer 21.

Optionally, when the first soldering pad 22 is disposed on at least one surface of the second soldering pad 23, the shortest distance between the soldering dots on the metal layer 21 and the side edge of the projected area of the first soldering pad 22 on the metal layer 21 is no greater than the distance threshold. The side edge is adjacent to the projected area of the second soldering pad 23 on the metal layer 21.

For example, the shortest distance between the power supply input soldering dots on the metal layer 21 and the side edge of the projected area of the first soldering pad 22 on the metal layer 21 is no greater than the distance threshold.

Optionally, when the first soldering pad 22 is disposed on at least two sides of the second soldering pad 23, the shortest distance between the soldering dots on the metal layer 21 and the side edge of the projected area of the first soldering pad 22 on the metal layer 21 is smaller than the distance threshold. The side edge is adjacent to the projected area of the second soldering pad 23 on the metal layer 21.

In one embodiment, the first through-hole 24 may include a plurality of through-holes to ensure a complete connection between the first soldering pad 22 and the power supply input soldering dots 211 on the metal layer 21. Moreover, a length of the first through-hole 24 may be a thickness of the first insulation layer 20, for example, 50 μm, 20 μm, or 30 μm, etc. The second through-hole 25 may also include a plurality of through-holes to ensure a complete connection between the second soldering pad 23 and the power supply output soldering dots 212 on the metal layer 21. Moreover, a length of the second through-hole 25 may be a sum of a thickness of the first insulation layer 20 and a thickness of the metal layer 21, for example, 50 μm+20 μm=70 μm, 20 μm+30 μm=50 μm, or 30 μm+24 μm=54 μm, etc. Further description is omitted.

In addition, in one embodiment, the connection between the first soldering pad 22 and the metal layer 21 (practically, the connection between the first soldering pad 22 and the power supply input soldering dots 211 on the metal layer 21) and the connection between the second soldering pad 23 and the power supply output soldering dots 212 may be achieved through the through-holes or through other means, such as wires, and electromagnetic coupling, etc. The present disclosure does not pose any limitations.

Optionally, in one embodiment, the first soldering pad 22 is often the power supply input soldering pad (i.e., VDD pad) on the circuit substrate, and the second soldering pad 23 is often the power supply output soldering pad (i.e., VSS pad) on the circuit substrate. Of course, in another embodiment, the first soldering pad 22 may be the corresponding power supply output soldering pad and the second soldering pad 23 may be the corresponding power supply input soldering pad. In this case, component placement on the circuit substrate may be adjusted accordingly. The present disclosure does not pose any limitation.

In the following embodiments of the present disclosure, the circuit substrate will be described in detail with the assumption that the first soldering pad 22 is the power supply input soldering pad and the second soldering pad 23 is the power supply output soldering pad.

It should be noted that there exists an equivalent resistance of the first soldering pad 22, the first through-hole 24, and the metal layer 21. When the distance between the first soldering pad 22 and the power supply input soldering dots 211 (e.g., the power supply input soldering dots 211 farther away from the first soldering pad 22) is substantially long, the length of the first through-hole 24 is substantially long, and the distance between the first through-hole 24 and the power supply input soldering dots 211 is substantially long, based on the formula R=ρL/S, the combined equivalent resistance between the first soldering pad 22 and the power supply input soldering dots 211 may be substantially large. Further, because the first soldering pad 22 is the power supply input soldering pad and the voltage thereof is often substantially high, a voltage drop between the first soldering pad 22 and the power supply input soldering dots 211 may be further increased. As such, the voltages at the power supply input soldering dots 211 may be unable to satisfy the actual voltage requirement. For example, assuming that the voltage at the first soldering pad 22 is 0.8V and the voltage drop between the first soldering pad 22 and the power supply input soldering dots 211 is 0.5V, then the voltage at the power supply input soldering dots 211 is 0.3V. As such, the voltages at the power supply input soldering dots 211 farther away from the first soldering pad 22 are unable to satisfy the actual operation requirement. For example, assuming that a normal operating voltage at the power supply input soldering dots is between 0.4V and 1.0V, and 0.3V<0.4V. Thus, the voltages at the soldering dots may be unbalanced between each other, thereby affecting the normal operation of the entire circuit substrate.

Optionally, because the equivalent resistances of the first soldering pad 22 and the first through-hole 24 are often substantially small and negligible, the voltage drop between the first soldering pad 22 and the power supply input soldering dots 211 is often considered the same as the voltage drop between the projected area of the first soldering pad 22 on the metal layer 21 and the power supply input soldering dots 211. Taking the consideration that the first soldering pad 22 is connected to the metal layer 21 through the first through-hole 24, the voltage drop between the first soldering pad 22 and the power supply input soldering dots 211 may actually be the voltage drop between the position of the first through-hole 24 on the metal layer 21 (the position where the metal layer 21 and the connection of the first through-hole 24 are connected) and the power supply input soldering dots 211.

Generally, because the position of the first through-hole 24 on the first soldering pad 22 is located in the periphery of the first soldering pad 22, the position of the first through-hole 24 on the metal layer 21 is close to the periphery of the projected area of the first soldering pad 22 on the metal layer 21. As such, in one embodiment, the voltage drop between the position of the first through-hole 24 on the metal layer 21 and the power supply input soldering dots 211 may be treated as the voltage drop between the first soldering pad 22 and the power supply input soldering dots 211. Further description is omitted.

It should be noted that, in one embodiment, the equivalent resistance between the first soldering pad 22 and the power supply input soldering dots 211 may often be calculated based on the shortest distance between the projected area of the first soldering pad 22 on the metal layer 21 and the power supply input soldering dots 211. The voltage drop between the first soldering pad 22 and the power supply input soldering dots 211 may further be determined. And the power supply input soldering dots 211 may be ensured to operate at the normal voltages. Of course, under the circumstances that high precision is required, the length of the first through-hole 24 (i.e., the thickness of the first insulation layer 20) and the equivalent resistance of the first soldering pad 22 itself may be included in the calculation. Further description is omitted.

Further, because each power supply input soldering dot 211 on the metal layer 21 may correspond to a unique power supply output soldering dot 212 and each pair of soldering dots (one power supply input soldering dot 211 and the corresponding power supply output soldering dot 212) may correspond to a pair of soldering dots (one first input soldering dot and the corresponding output soldering dot) on the same die, a distance between each pair of the soldering dots is substantially short. Thus, when the shortest distance is determined, any soldering dot may be selected to determine the shortest distance between the selected soldering dot and the projected area of the first soldering pad 22 on the metal layer 21. Further description is omitted.

Preferably, that the shortest distance between the soldering dots on the metal layer 21 and the projected area of the first soldering pad 22 on the metal layer 21 is smaller than the distance threshold may include that the shortest distance between the power supply input soldering dots 211 on the metal layer 21 and the projected area of the first soldering pad 22 on the metal layer 21 is smaller than the distance threshold.

In the practical operation of the circuit substrate, the current may flow through the first soldering pad 22, the first through-hole 24, the metal layer 21, the power supply input soldering dots 211, the input soldering dots of the die, internal components of the die, the output soldering dots of the die, the power supply output soldering dots 212, and the second soldering pad 23. Moreover, a connection distance between the soldering dots of the die and the power supply input soldering dots 211 or the power supply output soldering dots 212 is often substantially short and has substantially small resistance. The voltage drop during the current transmission may occur primarily between the first soldering pad 22 and the power supply input soldering dots 211. Thus, when the circuit substrate is fabricated, the distance between the projected area of the first soldering pad 22 on the metal layer 21 and the power supply input soldering dots 211 may be controlled to be smaller than the distance threshold without considering the distance between the projected area of the first soldering pad 22 on the metal layer 21 and the power supply output soldering dots 212. Further description is omitted.

In one embodiment, the first insulation layer 20 is often made of any insulation material, such as ceramic, FR-4 (fiber glass board), etc. The metal layer 21, the first soldering pad 22, and the second soldering pad 23 are often made of any metallic conductive material, such as copper, aluminum, etc., which is not limited by the present disclosure.

Preferably, the projected area of the second soldering pad 23 on the metal layer 21 is no smaller than an area threshold.

It should be noted that, in one embodiment, the area threshold may be an area of a current output cross-section of the second soldering pad 23. Moreover, the area threshold may be configured according to actual requirements. For example, the area threshold may be 6.4 mm*5.575 mm=35.68 mm²(projected area size), 6.4 mm*24 μm=0.1536 mm²(when a long side outputs a current, a cross-section area of the long side), or 5.575 mm*24 μm=0.1338 mm²(when a short side outputs the current, the cross-section area of the short side), as long as the actual requirements are satisfied. The present disclosure does not pose any limitation.

It can be seen from the above that after the current passes through the die, the current can flow from the power supply output soldering dots 212 to the second soldering pad 23. Because the voltage at the second soldering pad 23 is zero and the second soldering pad 23 has an internal resistance itself, the voltage at the power supply output soldering dots 212 may not be zero. As such, the voltage at the power supply input soldering dots 211 may not reach the operating voltage. To reduce the voltage at the power supply output soldering dots 212, the equivalent resistance of the second soldering pad 23 may further be reduced.

Specifically, in one embodiment, the size of the projected area (or the cross-section area for outputting the current) of the second soldering pad 23 on the metal layer 21 may be increased to reduce the equivalent resistance of the second soldering pad 23. That is, the area S in the formula R=ρL/S may be increased to reduce the equivalent resistance of the second soldering pad 23. Thus, the voltages at the power supply output soldering dots 212 may be reduced and the power supply input soldering dots 211 may operate in the range of the normal operating voltage. Further description is omitted.

Optionally, FIG. 3 illustrates a projected view of various components on a metal layer of an exemplary circuit substrate according to the present disclosure. Specifically, in one embodiment, as shown in FIG. 3, the circuit substrate includes the first soldering pad 22. The first soldering pad 22 includes a first soldering sub-pad 221 and a second soldering sub-pad 222. The first soldering sub-pad 221 and the second soldering sub-pad 222 are disposed on a first side and a second side of the second soldering pad 23, respectively. The first side and the second side of the second soldering pad 23 are opposite to each other.

The first side and the second side of the second soldering pad 23 may be selected according to the actual requirements. For example, as shown in FIG. 3, the first side may be the left side, the right side, the top side, or the bottom side.

Referring to FIG. 3, a maximum vertical distance (a first distance) between the soldering dots on the metal layer 21 and the projected area of the first soldering sub-pad 221 on the metal layer 21 is L_max1. A maximum vertical distance (a second distance) between the soldering dots on the metal layer 21 and the projected area of the second soldering sub-pad 222 on the metal layer 21 is L_max2. The maximum value among the L_max1and L_max2is the distance threshold. For example, assuming that L_max2is greater than L_max1, then L_max2is the distance threshold.

Optionally, the projected area of the first soldering sub-pad 221 on the metal layer 21 is a first projected area, and the projected area of the second soldering sub-pad 222 on the metal layer 21 is a second projected area. A farthest distance between the soldering dots and the first projected area is a first farthest distance. A farthest distance between the soldering dots and the second projected area is a second farthest distance. The greater of the first farthest distance and the second farthest distance is the threshold distance.

Specifically, in one embodiment, as shown in FIG. 3, one power supply input soldering pad in the existing technology may be divided into two power supply input soldering sub-pads (the first soldering sub-pad 221 and the second soldering sub-pad 222 in FIG. 3) to supply power to the corresponding die from two sides of the power supply output soldering pad (the second soldering pad 23 in FIG. 3). As such, the distance between the power supply input soldering pad and the power input soldering dots may be effectively reduced. For example, in the traditional method, the farthest distance will be L_max2in FIG. 3. In the present disclosure, the farthest distance may be L (L<L_max2). As such, the voltage drop between the first soldering pad 22 and the power supply input soldering dots 211 may further be reduced. Even the power supply input soldering dots 211 distant from the first soldering pad 22 may also operate in the range of the normal operating voltage. The normal operation of the circuit substrate is ensured. Further description is omitted.

It should be noted that, in one embodiment, the shape of the projected area of each section of the circuit substrate may be configured arbitrarily, such as a quadrilateral, a circle, a polygon, or an irregular shape, and is not limited by the present disclosure.

For illustrative purposes, the shapes of respective sections of the circuit substrate are cuboids. The thickness (or height) of the respective sections of the circuit substrate is substantially small, such as 10 μm, 20 μm, 50 μm, etc. The length and width of the respective sections are substantially large, such as 1.0 cm and 1.5 cm, 2.0 cm and 1.0 cm, etc. Further, in one embodiment, a shape formed by the large sides (length, width) is called a surface and a shape formed by the short sides (height) is called a side surface, which is not limited by the present disclosure.

Further, the first soldering pad 22 may include the first soldering sub-pad 221, the second soldering sub-pad 222, and a third soldering sub-pad 223. The first soldering sub-pad 221 and the second soldering sub-ad 222 are disposed on the first side and the second side of the second soldering pad 23, respectively. The first side and the second side of the second soldering pad 23 are opposite to each other. The third soldering sub-pad 223 is disposed on a third side or a fourth side of the second soldering pad 23. The third side and the fourth side of the second soldering pad 23 are opposite to each other.

Optionally, the projected area of the first soldering sub-pad 221 on the metal layer 21 is the first projected area. The projected area of the second soldering sub-pad 222 on the metal layer 21 is the second projected area. The projected area of the third soldering sub-pad 223 on the metal layer 21 is a third projected area. The farthest distance between the soldering dots and the first projected area is the first farthest distance. The farthest distance between the soldering dots and the second projected area is the second farthest distance. The farthest distance between the soldering dots and the third projected area is a third farthest distance. The greatest of the first farthest distance, the second farthest distance, and the third farthest distance is the threshold distance.

Specifically, FIG. 4 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. Specifically, as shown in FIG. 4, in the circuit substrate, the third soldering sub-pad 223 is disposed on the third side of the second soldering pad 23.

Referring to FIG. 4, the maximum vertical distance (the first distance) between the soldering dots on the metal layer 21 and the projected area of the first soldering sub-pad 221 on the metal layer 21 is L_max1. The maximum vertical distance (the second distance) between the soldering dots on the metal layer 21 and the projected area of the second soldering sub-pad 222 on the metal layer 21 is L_max2. A maximum vertical distance (a third distance) between the soldering dots on the metal layer 21 and the projected area of the third soldering sub-pad 223 on the metal layer 21 is L_max3. The maximum value among the L_max1, L_max2, and L_max3is the distance threshold. For example, assuming that L_max3is greater than L_max1and L_max2, then L_max3is the distance threshold.

As shown in FIG. 4, after the third soldering sub-pad 223 is configured, some soldering dots on the metal layer 21 are located closer to the side edge of the projected area of the first soldering pad 22 on the metal layer 21. For example, the distance between a certain power supply input soldering dot 211 and the first soldering pad 22 is reduced from L1 to L2 in FIG. 4. As such, the equivalent resistance between the soldering dot and the first soldering pad 22 may be further reduced. The voltage drop between the soldering dot and the first soldering pad 22 may be reduced. The voltage at the soldering dot may be substantially consistent with the voltages at other soldering dots. Thus, the voltages at the soldering dots may be balanced with each other and the soldering dots may operate in the range of the normal operating voltage.

Similarly, FIG. 5 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. Specifically, as shown in FIG. 5, in the circuit substrate, the third soldering sub-pad 223 is disposed on the fourth side of the second soldering pad 23. In this case, the circuit substrate operates in the same way as previously described. For example, the distance between a certain power supply input soldering dot 211 and the first soldering pad 22 is reduced from L1 to L2 in FIG. 5. Further description is omitted.

Optionally, in one embodiment, in addition to being separately disposed, the soldering sub-pads of the first soldering pad 22 may be disposed as a whole on respective sides of the second soldering pad 23 as shown in FIG. 6 and FIG. 7. FIG. 6 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. FIG. 7 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to present disclosure.

It should be noted that, the circuit substrates (the fourth and the fifth) shown in FIG. 6 and FIG. 7 may achieve the same technical effects as the circuit substrates (the second and the third) in FIG. 4 and FIG. 5 and will not be described in detail herein.

As shown in FIG. 6 and FIG. 7, the first soldering pad 22 is disposed on at least two outer sides of the second soldering pad 23. The projected area of the first soldering pad 22 on the metal layer 21 is a concave surface. The projected area of the second soldering pad 23 on the metal layer 21 is a convex surface. The concave portion of the concave surface encloses the convex portion of the convex surface.

Further, in one embodiment, the projected area of the first soldering pad 22 on the metal layer 21 may include at least two concave surfaces. The projected area of the second soldering pad 23 on the metal layer 21 may include at least two convex surfaces. The at least two concave surfaces are one-to-one corresponding to the at least two convex surfaces. The concave portion of the concave surface encloses the convex portion of the corresponding convex surface.

Correspondingly, FIG. 8A illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. FIG. 8B illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure.

Referring to FIG. 8A, the projected area of the first soldering pad 22 on the metal layer 21 includes two concave surfaces, referred to as a concave surface A and a concave surface B. The projected area of the second soldering pad 23 on the metal layer 21 includes two convex surfaces, referred to as a convex surface M and a convex surface N. The concave portion of the concave surface A encloses the convex portion of the convex surface M. The concave portion of the concave surface B encloses the convex portion of the convex surface N.

Referring to FIG. 8B, the projected area of the first soldering pad 22 on the metal layer 21 includes three concave surfaces, referred to as a concave surface C, a concave surface D, and a concave surface E. The projected area of the second soldering pad 23 on the metal layer 21 includes three convex surfaces, referred to as a convex surface F, a convex surface G, and a convex surface K. The concave portion of the concave surface C encloses the convex portion of the convex surface F. The concave portion of the concave surface D encloses the convex portion of the convex surface G. The concave portion of the concave surface E encloses the convex portion of the convex surface K.

It should be noted that, the concave surfaces in the projected area of the first soldering pad 22 on the metal layer 21 may face other directions. For example, the concave surface may face toward the upper side, the left side, or the right side, etc. Correspondingly, orientation of the convex surfaces in the projected area of the second soldering pad 23 on the metal layer 21 may be adjusted, such that the orientation of the concave surfaces matches the orientation of the convex surfaces.

Optionally, in some other embodiments, the projected areas of the first soldering pad 22 and the second soldering pad 23 on the metal layer 21 may have other shapes. FIG. 9A illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. For example, a T-shaped surface is shown in FIG. 9A, as long as the soldering dots on the metal layer 21 are ensured to be substantially close to the side edge of the projected area of the first soldering pad 22 on the metal layer 21. Further description is omitted.

FIG. 9B illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. In some other embodiments, as shown in FIG. 9B, the projected areas of the first soldering pad 22 and the second soldering pad 23 on the metal layer 21 may also include combination of the previously described shapes.

The projected areas of the first soldering pad 22 and the second soldering pad 23 on the metal layer 21 may have any shapes that reduce the distances between the soldering dots on the metal layer 21 and the side edge of the projected area of the first soldering pad 22 on the metal layer 21, such as a circle, a fan, or a polygon, etc. Further description is omitted.

Optionally, FIG. 10 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. Specifically, as shown in FIG. 10, the first soldering pad 22 may include a sixth soldering sub-pad 224. The sixth soldering sub-pad 224 may be disposed on the fourth side of the second soldering pad 23, opposite to the third side.

As shown in FIG. 10, after the sixth soldering sub-pad 223 is configured, some soldering dots on the metal layer 21 are located closer to the side edge of the projected area of the first soldering pad 22 on the metal layer 21. For example, the distance between a certain power supply input soldering dot 211 and the first soldering pad 22 is reduced from L1 to L2 in FIG. 8. As such, the equivalent resistance between the soldering dot and the first soldering pad 22 may be further reduced. The voltage drop between the soldering dot and the first soldering pad 22 may be reduced. The voltage at the soldering dot may be substantially consistent with the voltages at other soldering dots. Thus, the voltages at the soldering dots may be balanced with each other and the soldering dots may operate in the range of the normal operating voltage.

Further, the projected area of the second soldering pad 23 on the metal layer 21 may be increased. FIG. 11 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. Specifically, as shown in FIG. 11, the second soldering pad 23 may also include a fourth soldering sub-pad 231 and a fifth soldering sub-pad 232. Soldering dots may be disposed in the projected area of the fourth soldering sub-pad 231 on the metal layer 21 to one-to-one correspond to the soldering dots on the corresponding die. The fifth soldering sub-pad 232 is connected to the fourth soldering sub-pad 231. The area occupied by the second soldering pad 23 increases substantially to reduce the equivalent resistance of the second soldering pad 23. Thus, the voltage drop between the power supply output soldering dots 212 and the second soldering pad 23 may be reduced and the voltages at the power supply output soldering dots are balanced.

It should be noted that, the fourth soldering sub-pad 231 and the fifth soldering sub-pad 232 may be one pad or two connected pads. Further description is omitted.

Optionally, in some embodiments, the soldering sub-pads may be integrated into one pad or disposed individually. Further description is omitted.

Further, FIG. 12 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. Specifically, as shown in FIG. 12, in the circuit substrate, the projected area of the first soldering pad 22 on the metal layer 21 is a concave surface. The projected area of the second soldering pad 23 on the metal layer 21 is a convex surface. The concave portion of the concave surface encloses the convex portion of the convex surface.

It should be noted that the circuit substrate may achieve the same technical effect as previously described. Further description is omitted.

Optionally, FIG. 13 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. Specifically, as shown in FIG. 13, when the first soldering pad is disposed on at least two outer sides of the second soldering pad 23, the projected area of the first soldering pad 22 on the metal layer 21 encloses the projected area of the second soldering pad 23 on the metal layer 21.

For example, as shown in FIG. 13, the distance between the first soldering pad 22 and the power supply input soldering dots 211 is substantially short. Compared with the previously described substrate circuits, the first soldering pad 22 may supply power to the die from four sides of the die. Thus, the voltage drop between the first soldering pad 22 and the power supply input soldering dots 211 may be further reduced and the soldering dots may be ensured to operate in the range of the normal operating voltage.

It should be noted that, in one embodiment, because the first soldering pad 22, the soldering pad 23, and the metal layer 21 are all made of metallic conductive materials, such as copper, aluminum, etc., the equivalent resistance of the first soldering pad 22, the second soldering pad 23, and the metal layer 21 are often substantially small. Under the circumstances that high precision is not required, the equivalent resistance thereof may often be negligible. Further description is omitted.

Optionally, FIG. 14 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure. Specifically, as shown in FIG. 14, when the first soldering pad is disposed on at least two inner sides of the second soldering pad 23, the projected area of the second soldering pad 23 on the metal layer 21 encloses the projected area of the first soldering pad 22 on the metal layer 21.

Optionally, the second soldering pad 23 may be disposed in a ring shape. For example, the second soldering pad 23 may be a ring, a square ring, etc. Correspondingly, the first soldering pad 22 may also be disposed in the inner side of the ring of the second soldering pad 23.

For example, as shown in FIG. 14, the distance between the first soldering pad 22 and the power supply input soldering dots 211 is substantially short. Compared with the previously described substrate circuits, the first soldering pad 22 may supply power to the die from the four sides of the die. Thus, the voltage drop between the first soldering pad 22 and the power supply input soldering dots 211 may be further reduced and the soldering dots may be ensured to operate in the range of the normal operating voltage.

It should be noted that, in one embodiment, because the first soldering pad 22 and the second soldering pad 23 enclose with each other, in the actual fabrication process, additional metal layer 21 and additional first insulation layer 20 may be added to achieve the current transmission. Further description is omitted.

In addition, it should be noted that, in one embodiment, corresponding signal input output soldering pad (not shown) may be disposed on the circuit substrate to achieve corresponding signal transmission. The signal input output soldering pad may be disposed in any layer of the circuit substrate as long as the actual requirements are satisfied. The present disclosure does not pose any limitation.

Optionally, in one embodiment, to reduce the distance between the first soldering pad 22 and the soldering dots on the metal layer 21, relative position between the first soldering pad 22 and the metal layer 21 may be modified. For example, a portion of or the entire projected area of the first soldering pad 22 on the metal layer 21 may be disposed in an area disposed with soldering dots. Correspondingly, the entire structure of the circuit substrate may be adjusted. In some other embodiments, the thickness of the entire circuit substrate may be controlled not to exceed a thickness threshold, such as 1 mm, 900 μm, etc. Further description is omitted.

FIG. 15 illustrates a projected view of various components on a metal layer of another exemplary circuit substrate according to the present disclosure.

Specifically, as shown in FIG. 15, the circuit substrate may include the first insulation layer 20 (not shown), the metal layer 21, the first soldering pad 22, and the second soldering pad 23. The metal layer 21 is disposed on the first surface of the first insulation layer 20. The second soldering pad 23 (referring to FIG. 16) is disposed on the second surface of the first insulation layer 20 facing away from the metal layer 21. At least two soldering dots (the power supply input soldering dots 211 and the power supply output soldering dots 212 in FIG. 15) may be disposed in the projected area of the second soldering pad 23 on the metal layer 21 to one-to-one correspond to the soldering dots on the die. The first soldering pad 22 may be disposed on at least one surface or at least two sides of the second soldering pad 23, for example, on a top surface (not shown), a bottom surface (not shown), a first side ((1) side), and a third side ((3) side).

Specifically, FIG. 16 illustrates a cross-sectional view of another exemplary circuit substrate according to the present disclosure. The cross-sectional view may be any cross-sectional view that can clearly represent relative positions between various components on the circuit substrate and is not limited by the present disclosure.

In one embodiment, as shown in FIG. 16, surfaces of the second soldering pad 23 refer to two planes in parallel with an extension direction of the metal layer 21 and the first insulation layer 20, including a top surface and a bottom surface in FIG. 16. The side surfaces of the second soldering pad 23 may be the four surfaces perpendicular to the extension direction of the metal layer 21 and the first insulation layer 20, including (1) side, (2) side, (3) side, and (4) side as shown in FIG. 15. Further description is omitted.

It should be noted that, in one embodiment, sections of the circuit substrate may extend in a same direction, such as being consistent (parallel) with the paper surface direction of the present specification. Further description is omitted.

From the above content, in one embodiment, when the first soldering pad 22 is disposed on at least one surface of the second soldering pad 23, the voltages at the soldering dots on the metal layer 21 may be kept consistent. When the first soldering pad 22 is disposed on at least two sides of the second soldering pad 23, the differences between the voltages at the soldering dots on the metal layer 21 may be substantially small. Thus, the problem that the voltages at the soldering dots on the metal layer 21 are not balanced may be resolved and the normal operation of the circuit substrate may be ensured.

Correspondingly, the present disclosure also provides a chip. FIG. 17 illustrates a cross-sectional view of an exemplary chip according to the present disclosure. Specifically, as shown in FIG. 17, the chip may include a die 101 and a circuit substrate 102 consistent with the embodiments of the present disclosure. The die 101 is disposed on the surface of the metal layer 21 facing away from the first insulation layer 20. The soldering dots on the metal layer 21 may one-to-one connect to the soldering dots on the die 101.

It should be noted that, in one embodiment, one or more dies 101 may be disposed on the circuit substrate 102. The present disclosure does not pose any limitation.

Optionally, in one embodiment, connections between the soldering dots on the die 101 and the soldering dots on the metal layer may include one-to-one connections (physical connections, electrical connections) between input soldering dots on the die 101 and power supply input soldering dots 211 on the metal layer 21 and one-to-one connections (physical connections, electrical connections) between output soldering dots on the die 101 and the power supply output soldering dots 212 on the metal layer 21.

In the chip provided by the embodiments of the present disclosure, a power supply input soldering pad 22 and a power supply output soldering pad 23 may often be a power supply input interface and a power supply output interface, respectively. Further description is omitted.

It should be noted that the chip may also include corresponding encapsulation material. Further description is omitted.

Further, the present disclosure also provides a series circuit. The series circuit may include at least two chip sets that are connected in parallel. Each chip set may include at least two chips provided by the embodiments of the present disclosure, which are connected in turn in series.

Further, the present disclosure also provides a circuit board. The circuit board may include the series circuit provided by the embodiments of the present disclosure.

The circuit board may often be a computing board, an algorithm board, or a calculating board, etc. in an electronic device. Further description is omitted.

Further, the present disclosure also provides an electronic device. The electronic device may include at least one circuit board provided by the embodiments of the present disclosure. When there are two or more circuit boards, the circuit boards are connected in parallel with each other.

Further, the present disclosure also provides another electronic device. FIG. 18 illustrates a cross-sectional view of an exemplary electronic device according to the present disclosure. Specifically, as shown in FIG. 18, the electronic device may include a body 1101 and a chip 1102 provided by the embodiments of the present disclosure. Further description is omitted.

It should be noted that the electronic device may often be a terminal device, a personal computer, or a cryptocurrency mining device, etc. Further description is omitted.

In one embodiment, when a high computing power of the electronic device is required, for example, when the electronic device is the cryptocurrency mining device, the number of the chips 1102 in the electronic device may be more, such as 60, 100, or 200, etc. In this case, a plurality of chips are divided into a plurality of chip sets that are connected in parallel with each other. Each chip set may include a plurality of chips that are connected in series with each other. An output voltage of a preceding chip is an input voltage of a succeeding chip. In this case, power supply output interfaces of the advanced chips may output non-zero voltages. Only the power supply output interface of the very last chip may output a zero voltage. Further description is omitted.

It should be noted that all terms such as “first”, “second”, “third”, “fourth”, “fifth” are intended to distinguish different subjects, and do not limit the present disclosure.

The present disclosure provides the circuit substrate, the chip, and the electronic device. The circuit substrate includes the insulation layer, the metal layer, the first soldering pad, and the second soldering pad. The metal layer is disposed on the first surface of the insulation layer. The first soldering pad and the second soldering pad are disposed on the second surface of the insulation layer facing away from the metal layer. The shortest distance between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer is no greater than the distance threshold. The soldering dots on the metal layer are one-to-one corresponding to the soldering dots on the die. Compared to the existing technology, in the embodiments of the present disclosure, the distance between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer is substantially short, and the corresponding equivalent resistance is substantially small. Thus, the voltages at the soldering dots on the metal layer are balanced with each and the normal operation of the circuit substrate is ensured.

Those skilled in the art will appreciate that the embodiments of the present disclosure can be provided as a method, an apparatus (device), or a computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the present disclosure may take the form of the computer program product embodied on one or more computer-readable storage medium containing computer program instructions. The computer-readable storage medium includes, but is not limited to, a magnetic disk, a CD-ROM, or an optical disk, etc.

The present disclosure has been described with reference to flow charts and/or block diagrams of the method, the apparatus (device), and the computer program product provided by the embodiments of the present disclosure. It should be understood that, when being executed by a processor, the computer program instructions implement each step and/or each function of the flow chart and/or the block diagram and/or a combination of both. The computer program instructions may be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, such that executing the computer program instructions by the processor of the computer or other programmable data processing device to implement generates a device that implements one or more steps of the flow chart and/or one or more functions of the block diagram.

The computer program instructions may be stored in a computer-readable memory to instruct the computer or other programmable data processing device to operate in certain way, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising the instruction device. The instruction device implements the functions specified in one or more blocks of the block diagram and/or in one or more steps of the flow chart.

The computer program instructions may be loaded into the computer or other programmable data processing device for the computer or other programmable data processing device to execute a series of operations to perform computer-implemented processing, such that the instructions executed by the computer or other programmable data processing device provide steps for implementing the functions specified in one or more blocks of the block diagram and/or in one or more steps of the flow chart.

Although the embodiments of the present disclosure have been described, those skilled in the art may change or modify the embodiments once the basic creative concepts are known. Therefore, the appended claims are intended to be interpreted as including the embodiments and all the changes and modifications in the scope of the present disclosure.

Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and the scope of the present disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. A circuit substrate, comprising: an insulation layer;a metal layer disposed on a first surface of the insulation layer; anda first soldering pad and a second soldering pad disposed on a second surface of the insulation layer facing away from the metal layer,wherein: shortest distances between soldering dots on the metal layer and a projected area of the first soldering pad on the metal layer are all smaller than a distance threshold;the soldering dots on the metal layer are one-to-one corresponding to soldering dots on a corresponding die;the shortest distance is a minimum value of vertical distances between the soldering dots on the metal layer and a side edge of the projected area of the first soldering pad on the metal layer; andthe side edge is adjacent to a projected area of the second soldering pad on the metal layer.
2. The circuit substrate according to claim 1, wherein: the distance threshold is the farthest distance between the soldering dots on the metal layer and the projected area of the first soldering pad on the metal layer; andthe farthest distance is a maximum value of vertical distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer; andthe side edge is adjacent to the projected area of the second soldering pad on the metal layer.
3. The circuit substrate according to claim 2, wherein: the first soldering pad is a power supply input soldering pad of the circuit substrate; andthe second soldering pad is a power supply output soldering pad of the circuit substrate.
4. The circuit substrate according to claim 2, wherein that the shortest distances between the soldering dots on the metal layer and the projected area of the first soldering pad on the metal layer are all smaller than the distance threshold includes: that the shortest distances between the power supply input soldering dots on the metal layer and the projected area of the first soldering pad on the metal layer are all smaller than the distance threshold.
5. The circuit substrate according to claim 2, wherein: the first soldering pad is connected to the metal layer through a first through-hole; andthe distances between the soldering dots on the metal layer and a position of the first through-hole on the metal layer are smaller than the distance threshold.
6. The circuit substrate according to any of claims 1-5, wherein: an area occupied by the projected area of the second soldering pad on the metal layer is no smaller than an area threshold.
7. The circuit substrate according to any of claims 1-5, wherein: the first soldering pad includes a first soldering sub-pad and a second soldering sub-pad; andthe first soldering sub-pad and the second soldering sub-pad are disposed on a first side and a second side of the second soldering pad, respectively, wherein the first side and the second side are opposite to each other.
8. The circuit substrate according to claim 7, wherein: the projected area of the first soldering pad on the metal layer is a first projected area and the projected area of the second soldering pad on the metal layer is a second projected area; andthe distance threshold is the greater of a first farthest distance between the soldering dots on the metal layer and the first projected area and a second farthest distance between the soldering dots on the metal layer and the second projected area.
9. The circuit substrate according to any of claims 1-5, wherein: the first soldering pad includes the first soldering sub-pad, the second soldering sub-pad, and a third soldering sub-pad;the first soldering sub-pad and the second soldering sub-pad are disposed on the first side and the second side of the second soldering pad, respectively; andthe third soldering sub-pad are disposed on a third side or a fourth side of the second soldering pad, wherein the third side and the fourth side of the second soldering pad are opposite to each other.
10. The circuit substrate according to claim 9, wherein: the first soldering pad further includes a fourth soldering sub-pad;the fourth soldering sub-pad is disposed on the fourth side of the second soldering pad.
11. The circuit substrate according to claim 9, wherein: the projected area of the first soldering sub-pad on the metal layer is a third projected area, the projected area of the second soldering sub-pad on the metal layer is a fourth projected area, and the projected area of the third soldering sub-pad on the metal layer is a fifth projected area; andthe distance threshold is the greatest of a third farthest distance between the soldering dots on the metal layer and the third projected area, a fourth farthest distance between the soldering dots on the metal layer and the fourth projected area, and a fifth farthest distance between the soldering dots on the metal layer and the fifth projected area.
12. The circuit substrate according to any of claims 1-5, wherein: the projected area of the first soldering pad on the metal layer is a concave surface;the projected area of the second soldering pad on the metal layer is a convex surface; anda concave portion of the concave surface encloses a convex portion of the convex surface.
13. The circuit substrate according to claim 12, wherein: when the first soldering pad is disposed on at least two outer sides of the second soldering pad, the projected area of the first soldering pad on the metal layer is the concave surface, the projected area of the second soldering pad on the metal layer is the convex surface, and the concave portion of the concave surface encloses the convex portion of the convex surface.
14. The circuit substrate according to any of claims 1-5, wherein: the projected area of the first soldering pad on the metal layer encloses the projected area of the second soldering pad on the metal layer.
15. The circuit substrate according to claim 14, wherein: when the first soldering pad is disposed on at least two outer sides of the second soldering pad, the projected area of the first soldering pad on the metal layer encloses the projected area of the second soldering pad on the metal layer.
16. The circuit substrate according to any of claims 1-5, wherein: the projected area of the second soldering pad on the metal layer encloses the projected area of the first soldering pad on the metal layer.
17. The circuit substrate according to claim 16, wherein: when the first soldering pad is disposed on at least two outer sides of the second soldering pad, the projected area of the second soldering pad on the metal layer encloses the projected area of the first soldering pad on the metal layer.
18. The circuit substrate according to any of claims 1-17, wherein: the first soldering pad is disposed on at least one surface or at least two sides of the second soldering pad.
19. The circuit substrate according to claim 18, further including: a second insulation layer disposed between the first soldering pad and the second soldering pad, wherein the first soldering pad is disposed on a first surface of the second soldering pad facing toward the metal layer.
20. The circuit substrate according to claim 18, further including: a second insulation layer disposed between the first soldering pad and the second soldering pad, wherein the first soldering pad is disposed on a second surface of the second soldering pad facing away from the metal layer.
21. The circuit substrate according to claim 19 or 20, wherein disposing the first soldering pad on at least one surface of the second soldering pad refers to: that the projected area of the first soldering pad and the projected area of the second soldering pad at least partially overlap.
22. The circuit substrate according to claim 19 or 20, wherein disposing the first soldering pad on at least one surface of the second soldering pad refers to: that the projected area of the first soldering pad and the projected area of the second soldering pad completely overlap.
23. The circuit substrate according to any of claims 18-22, wherein: when the first soldering pad is disposed on at least one surface of the second soldering pad, the shortest distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are no greater than the distance threshold; andthe side edge is adjacent to the projected area of the second soldering pad on the metal layer.
24. The circuit substrate according to claim 23, wherein that the shortest distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are no greater than the distance threshold includes: that the shortest distances between the power supply input soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are no greater than the distance threshold.
25. The circuit substrate according to claim 23, wherein: the first soldering pad is connected to the metal layer through a first through-hole; andwhen the first soldering pad is disposed on at least one surface of the second soldering pad, the distances between the soldering dots on the metal layer and a position of the first through-hole on the metal layer are no greater than the distance threshold.
26. The circuit substrate according to claim 23, wherein: the distance threshold is the farthest distance between the soldering dots on the metal layer and the projected area of the first soldering pad on the metal layer;the farthest distance is a maximum value of vertical distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer; andthe side edge is adjacent to the projected area of the second soldering pad on the metal layer.
27. The circuit substrate according to any of claims 18-22, wherein: when the first soldering pad is disposed on at least two sides of the second soldering pad, the shortest distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are smaller than the distance threshold; andthe side edge is adjacent to the projected area of the second soldering pad on the metal layer.
28. The circuit substrate according to claim 27, wherein that the shortest distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are smaller than the distance threshold includes: that the shortest distances between the power supply input soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer are smaller than the distance threshold.
29. The circuit substrate according to claim 27, wherein: the first soldering pad is connected to the metal layer through a first through-hole; andwhen the first soldering pad is disposed on at least two sides of the second soldering pad, the distances between the soldering dots on the metal layer and a position of the first through-hole on the metal layer are smaller than the distance threshold.
30. The circuit substrate according to claim 27, wherein: the distance threshold is the farthest distance between the soldering dots on the metal layer and the projected area of the first soldering pad on the metal layer;the farthest distance is a maximum value of vertical distances between the soldering dots on the metal layer and the side edge of the projected area of the first soldering pad on the metal layer; andthe side edge is adjacent to the projected area of the second soldering pad on the metal layer.
31. The circuit substrate according to any of claims 18-20, wherein: an area occupied by the projected area of the second soldering pad on the metal layer is no smaller than an area threshold.
32. A circuit substrate, comprising: a first insulation layer;a metal layer disposed on a first surface of the first insulation layer;a first soldering pad; anda second soldering pad disposed on a second surface of the first insulation layer facing away from the metal layer,wherein: at least two soldering dots are disposed in a projected area of the second soldering pad on the metal layer and are one-to-one corresponding to soldering dots on a corresponding die; andthe first soldering pad is disposed on at least one surface or at least two sides of the second soldering pad.
33. The circuit substrate according to claim 32, wherein: when the first soldering pad is disposed on at least two outer sides of the second soldering pad, a projected area of the first soldering pad on the metal layer is a concave surface, the projected area of the second soldering pad on the metal layer is a convex surface, and a concave portion of the concave surface encloses a convex portion of the convex surface.
34. The circuit substrate according to claim 32, wherein: when the first soldering pad is disposed on at least two outer sides of the second soldering pad, the projected area of the first soldering pad on the metal layer encloses the projected area of the second soldering pad on the metal layer.
35. The circuit substrate according to claim 32, wherein: when the first soldering pad is disposed on at least two outer sides of the second soldering pad, the projected area of the second soldering pad on the metal layer encloses the projected area of the first soldering pad on the metal layer.
36. A chip, comprising: a die; anda circuit substrate according to any of claim 1-31 or 32-35, wherein: a die is disposed on a surface of an insulation layer facing away from a metal layer; andsoldering dots on the metal layer are one-to-one connected to soldering dots on the die, respectively.
37. A series circuit, comprising: at least two chip sets connected in parallel with each other, wherein each chip set includes at least two chips according to claim 36, connected in series with each other.
38. A circuit board, comprising a series circuit according to claim 37.
39. An electronic device, comprising at least one circuit board according to claim 38.
40. An electronic device, comprising: a body of the electronic device; andat least one chip according to claim 36.

Priority Claims (2)

Number	Date	Country	Kind
201810312401.9	Apr 2018	CN	national
201810312436.2	Apr 2018	CN	national

PCT Information

Filing Document	Filing Date	Country	Kind
PCT/CN2019/076545	2/28/2019	WO	00

CIRCUIT SUBSTRATE, CHIP, SERIES CIRCUIT, CIRCUIT BOARD AND ELECTRONIC DEVICE

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Priority Claims (2)

PCT Information