Patent Application
20200066521
Integrated circuits (IC) have continued to shrink as performance and cost demands have pushed designers to design integrated circuits with an increasing number of devices per unit area. Semiconductor manufacturing processes are continually developed and employed to enable the manufacture of smaller and smaller features on an IC.
The present disclosure described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, features illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some features may be exaggerated relative to other features for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Subtractive patterning may refer to a fabrication technique where a desired pattern (or feature) is defined by a layer, such as a resist layer, that protects the underlying materials from subsequent processes, such as etch. After etching is complete, the defining layer may be removed leaving the desired pattern or feature. A feature may be an element or physical structure of an integrated circuit, such as fin, gate, via, plug, etc., where the feature size of the element or physical structure is controllable within a tolerance. Feature size may be a physical measurement (e.g., width, length, etc.) of a feature. For electrical performance reasons, the critical dimensions of some features may be defined by spacer-based patterning techniques. For example, fabrication techniques, such as complementary patterning, may be used to create a predominantly one-dimensional pattern of spacers. Unwanted spacers may be cut or plugged to form the desired circuit pattern. As features get closer together, process variations (e.g., patterning size variation or overlay variation) may make cut or plug patterning prone to erroneously cutting the wrong spacers or miss cutting the desired spacers.
Aspects of the present disclosure addresses the above-mentioned and other deficiencies by “coloring” spacers so that every other spacer is a different material (or is associated with different etch properties). In implementations, spacer-based patterning may provide high controllability to help control features sizes for a semiconductor fabrication process. By having every other spacer (e.g., even and odd spacers) be a different material than adjacent spacers, a mask, such as a cut mask, may selectively etch spacers of a particular material per pass, allowing the cut mask to overlap a neighboring spacer of a different material without cutting the neighboring spacer. The disclosure allows for significantly more margin for edge placement errors of a mask and allows for a denser pattern of spacers to be used in a fabrication process. A denser pattern of spacers may allow for manufacture of an integrated circuit having features with tighter pitch. Pitch may refer to the sum of the feature size of a feature and the distance between the feature and another adjacent feature.
In implementations, aspects of the present disclosure adjust the etch properties associated with a first population of spacers selective to a second population of spacers. By changing the etch properties associated with a first population of spacers, either the first population of spacers or a second population of spacers may be removed selective to the other population. In some implementations, “coloring” of spacers may be performed by forming additional spacers in the areas created by the removal of the population of spacers. The additional spacers may be a different material or be associated with different etch properties than the population of spacers that were not removed.
In implementations, a first hardmask layer is formed above a substrate. In implementations, multiple backbone structures are formed above the first hardmask layer. In implementations, a first multitude of spacers of a first material are formed adjacent to first sides and second sides of the multiple backbone structures. The etch properties associated with the first multitude of spacers adjacent the second sides are adjusted. First spacers (or second spacers) of the first multitude of spacers that are adjacent to the first sides of the multitude of backbone structures are etched selective to the spacers on the opposite side of the backbone structures.
In implementations, a second multitude of spacers of a second material adjacent to the first sides and the second sides of the multiple backbone structures are formed. The third spacers of the second multitude of spacers that are adjacent to the second sides of the multiple backbone structures are asymmetrically etched. The multiple backbone structures protect fourth spacers of the second multitude of spacers that are adjacent to the first sides of the multiple backbone structures from being removed.
In implementations, the multiple backbone structures are selectively removed to leave the second spacers of the first material and the fourth spacers of the second material. In implementations, a second hardmask layer is formed above the second spacers of the first material and the fourth spacers of the second material. A trench in the second hardmask layer is etched to expose a first one of the second spacers and a first one of the fourth spacers. The first one of the second spacers is selectively etched respective the first one of the fourth spacers.
In implementations, another trench in the second hardmask layer is etched to expose a second one of the second spacers and a second one of the fourth spacers. The second one of the fourth spacers is selectively etched respective the second one of the second spacers. In implementations, the second hardmask layer is removed to expose remaining second spacers and remaining fourth spacers. The features of the integrated circuit are formed by transferring an etch pattern using the remaining second spacers and remaining fourth spacers. In implementations, the features the integrated circuit include fins of transistors. In implementations, the features the integrated circuit include gates of transistors.
In implementations, the first material of the first multitude of spacers is a different material than the second material of the second multitude of spacers. In implementations, the first material of the first multitude of spacers and the second material of the second multitude of spacers have different etch properties.
In implementations, an integrated circuit die, wafer, or computing device includes a substrate and a first multitude of features above the substrate. The integrated circuit die, wafer, or computing device includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.
In implementations, each of the first multitude of features are disposed between a different two of the second multitude of features. In implementations, the first multitude features and the second multitude of features are gates of transistors. In implementations, the first multitude features and the second multitude of features are fins of transistors.
In implementations, the first size and the second size are a width in the first direction. In implementations, the first size is an average width of the first multitude of features, and the second size is an average width of the second multitude of features where the first size is different from the second size. In implementations, the first multitude of features and the second multitude of features are a local subset of features of the integrated circuit die or computing device.
In implementations, adjusting the etch properties associated with the first multitude of spacers on the second sides includes performing angled passivation of the second spacers of the first multitude of spacers that are adjacent to the second sides include performing angled passivation of the second spacers of the first multitude of spacers that are adjacent to the second sides of the multitude of backbone structures selective to the first spacers of the first multitude of spacers that are adjacent to the first sides of the multitude of backbone structures. In implementations, etching selectively one of the first spacers or the second spacers includes etching the first spacers selective to the second spacers based on the passivated second spacers having different etch properties than the first spacers.
In implementations, adjusting the etch properties associated with the first multitude of spacers adjacent the second sides includes performing angled passivation of the second spacers of the first multitude of spacers that are adjacent to the second sides of the multitude of backbone structures selective to the first spacers of the first multitude of spacers that are adjacent to the first sides of the multitude of backbone structures. The method also includes growing a layer above the first spacers selective to the second spacers. The passivated second spacers prevent growth of the layer above the second spacers. The second spacers are etched selective to the first spacers based on the passivated second spacers having different etch properties than the layer above the first spacers.
In implementations, adjusting the etch properties associated with the first multitude of spacers adjacent the second sides includes performing angled deposition of a layer above the second spacers that are adjacent to the second sides of the multitude of backbone structures selective to the first spacers that are adjacent to the first sides of the multitude of backbone structures. The first spacers are etched selective to the second spacers based on the layer above the second spacers having different etch properties than the first spacers.
In implementations, adjusting the etch properties associated with the first multitude of spacers adjacent the second sides includes depositing a resist layer above the first spacers and the second spacers. The method also includes exposing the resist layer to off-axis illumination that exposes the resist layer in a first area adjacent the first spacers and prevents exposure of the resist layer in a second area adjacent the second spacers. In implementations, the method also includes etching the first spacers selective to the second spacers. The resist layer in the first area adjacent the first spacers is removed and the resist layer in the second area remains to prevent etch of the second spacers.
In implementations, adjusting the etch properties associated with the first multitude of spacers adjacent the second sides includes performing ion implantation on the second spacers that are adjacent to the second sides of the multitude of backbone structures selective to the first spacers that are adjacent to the first sides of the multitude of backbone. The ion implantation changes the etch properties of the second spacers. The one of the first spacers or second spacers is selectively etched based on the changed etch properties of the second spacers.
It may be noted that for purposes of illustration, rather than limitation, that aspects of the present disclosure describe processes and features for fabricating fins and gates above a substrate of an integrated circuit. It may be noted that aspects of the present disclosure may be applied to features, components, layers, etc. of an IC other than described herein. For example, processes described herein may be applied to form transistor features (e.g., gate, source, drain, fin, channel, etc.) of a transistor (e.g., bipolar junction transistors (BJT), field effect transistors (FET), such as metal-oxide-semiconductor FET, Fin FET, multiple-gate FET (MuFET) etc.). In other examples, the processes described herein may form features of diodes, light-emitting diodes (LED), or memory cells, among others. In still other examples, the processes described herein may be used on the various layers of an IC or interconnects and vias between layers.
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It may be noted that elements herein may be described using a number and letter. Elements that are described with a number and letter may be collectively described using a number without a letter. For example, backbone structure(s) 116 may refer to backbone structure 116A and/or backbone structure 116B, and/or backbone structure 116C, while reference to backbone structure 116A may refer to only backbone structure 116A, unless otherwise specified.
Hardmask layer 114A (also referred to as a “hard mask” or “protective layer” herein) may be formed, deposited, or grown above substrate 110. Hardmask layer 114B may be formed, deposited, or grown above hardmask layer 114A, In one exemplary implementation, a hardmask layer, such as hardmask layers 114, may be Silicon Nitride (Si3N4). A hard mask layer, such as hardmask layer 114, may be a variety of materials including one or more of Silicon Oxide (SiO2) or Silicon Nitride (Si3N4). In one implementation, hardmask layer 114B is a different material than hardmask layer 114A.
In one implementation, hardmask layer 114 is a dielectric material. Representative dielectric materials may include, but are not limited to, various Oxides, Nitrides and Carbides, for example, Silicon Oxide, Titanium Oxide, Hafnium Oxide, Aluminum Oxide, Oxynitride, Zirconium Oxide, Hafnium Silicate, Lanthanum Oxide, Silicon Nitride, Boron Nitride, Amorphous Carbon, Silicon Carbide, Amorphous Silicon, or other similar dielectric materials. In one implementation, hardmask layer 114A is deposited, for example, by a plasma deposition process, to a thickness to serve as a mask to substrate 110 (e.g., to protect from undesired modification of the underlying layer from energy used in a subsequent process, such as subsequent mask registration). In one embodiment, a representative thickness of hardmask layer 114 is on the order of 30 angstroms (A) ±20 A. In another embodiment, a representative thickness of hardmask layer 114 is on the order of two to five nanometers (nm). In some implementations, the thickness of hardmask layer 114 may be 5 nm to 15 nm. In other implementations, hardmask layer 114 may be any other thickness.
Process 100 illustrates the formation of backbone structures 116 above hardmask layer 114B. Backbone may also be referred to as “backbone structure” or “mandrel” or “mandrel structure,” herein. In implementations, a backbone material may be deposited or grown above the hardmask layer 114B as a conformal layer. Backbone materials include, but are not limited to, Polysilicon, Amorphous Silicon, Amorphous Carbon, Silicon Nitride and Germanium. Backbone structures 116 may offer structural support or scaffolding to create one or more spacers of different material, as described below. In an implementation, backbone structures 116 may be a different material and have different etch properties from the spacers described below.
In implementations, a layer of backbone material may be deposited above hardmask layer 114B. A photoresist material may be patterned to define one or more trenches (e.g., trenches 120) within the layer of backbone material. The photoresist material may form a pattern over the layer of backbone material that may in turn, be used to form a pattern within the backbone material for the opening of trenches 120 to form backbone structures 116A -116B, as illustrated in
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In some implementations, the spacers 220 may be formed by atomic layer deposition (ALD). ALD may be used to control the deposition of materials at the atomic level by depositing a single layer of atoms at a time. ALD may deposit spacers 220 with a feature size in the range of 1 nm to 10 nm with a tolerance of less than or equal to 2 nm. It may be noted that spacers wider than 10 nm may be formed using ALD or other processing technique.
In implementations, subsequent to depositing the spacer material for spacers 220, the hardmask layer 114B may be etched (e.g., anisotropic etch) to remove any superfluous spacer material from hardmask layer 114B, such as in the area of trenches 120 so as to prepare hardmask layer 114B for subsequent processes. It may be noted that other or additional techniques may be implemented to form spacers, such as spacers 220. In one implementation, spacers 220 may be formed using selective growth techniques or directed self-assembly (DSA), for example. In still other implementations, lithography techniques may be used to form larger spacers (e.g., greater than 50 nm).
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For the sake of illustration, rather than limitation, spacers may be referred to as odd spacers or even spacers. Odd spacers (e.g., spacers 220A, 220C, and 220E) may refer to the spacers on one side of the backbone structures 116, such as the left side of the backbone structures 116, and even spacers (e.g., spacers 220B, 220D, and 220E) may refer to spacers on the opposite side of backbone structures 116, such as the right side of backbone structures 116. It may be noted that for purposes of illustration, rather than limitation, even spacers have been removed selective to odd spacers. In other implementations, odd spacers may be removed selective to even spacers. It may be noted that the subsequent processes may be suitably adjusted and employed to address odd spacers being removed, rather than the even spacers as illustrated. In a variety of implementations, different processes may be used to remove one population of spacers (e.g., even spacers) selective to another population of spacers (e.g., odd spacers).
It may be noted that different processes to adjust the etch properties associated with one population of spacers and to remove a population of spacers selective another population of spacers are further described at least with respect to
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In implementations, the different spacer materials (e.g., spacer material A and spacer material B) may have different etch properties. Etch properties may refer to a property (e.g., etch rate) or response of a material to a particular etch process. In one example, different etch properties may refer to the etch rate of the target material (e.g., material A) compared to the etch rate of other materials (e.g., material B or others) exposed to an etch process having a high ratio (e.g., high etch selectivity). In some implementations, etch selectivity may be from 3 to 1 rates, to 1000 to 1 rates. In implementations, spacers with different etch properties may be exposed to an etch process to remove a spacer with one etch property without removing spacers having different etch properties (at least not enough to materially affect the remaining spacers).
In implementations, using spacers of different materials with different etch properties allows for the selective removal of a particular spacer without removing neighboring spacers with different etch properties. In implementations having features with tight pitch (e.g., 40 nm or below), the additional margin for error granted by the use of spacers of different materials allows for the manufacture of an IC with smaller features sizes and greater reliability.
In implementations, spacers 430 may be formed in a similar manner as described with respect to spacers 220 of
In an implementation, one or more of spacers 430 may have a feature size in the range of 3 nm to 15 nm with a tolerance of less than or equal to 2 nm. In implementations, all the spacers 430 may have the same features size (e.g. width) within a tolerance (e.g., 1 nm) and all the spacers 220 may have the same features size within a tolerance, where the features size of spacers 430 and spacers 220 are different. In implementations, the average width of spacers 220 may differ from the average width of spacers 430. In some examples, the average width of spacers 220 may differ from the average width of spacers 430 by 2 or more Angstroms. In some examples, the average width of spacers 220 may differ from the average width of spacers 430 in a range of 2 to 10 Angstroms. In implementations, difference in average width of spacers 220 may occur within a local area or across the entire, integrated circuit die, computing device, or wafer.
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In implementations, hardmask layer 714A is formed, deposited, or grown above hardmask layer 114B and cover at least spacers 220 and 430. Hardmask layer 714B is formed, deposited, or grown above hardmask layer 714A. Hardmask layer 714A and 714B may be formed in a similar manner or be a similar material as described with respect to hardmask layer 114 of
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In implementations, hardmask layer 914A is formed, deposited, or grown above hardmask layer 114B and cover at least spacers 220 and 430. In implementations, hardmask layer 914A may be the same layer as hardmask layer 714A, but with trench 732 filled, and the hardmask layer 714 re-planarized, for example. Hardmask layer 914B is formed, deposited, or grown above hardmask layer 914A. Hardmask layer 914A and 914B may be formed in a similar manner or be a similar material as described with respect to hardmask layer 114 of
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In implementations, spacers of one material (e.g., material A) may be a different width than spacers of a different material (e.g., material A). The variation in width may be attributable to at least the difference in the materials, the difference in processes, or the number of processes each spacer of a particular material undergoes. In implementations, the variation in width in the different spacer materials may affect the width of the underlying materials or features patterned from the spacers. As illustrated by integrated circuit die 1300, features 1336 made from spacers of material A may have a width 1340, and features 1338 made from spacers of material B may have a different width 1342 in the horizontal direction 326. In implementations, the average width of multiple features (e.g., group A) made from spacers of one material (e.g., features 1336 made from spacers of material A) may be different than the average width of multiple features (e.g., group B) made from spacers of a different material (e.g., features 1338 made from spacers of material B). In some implementations, the average width of the different groups of features (e.g., group A and B) may differ in width by 2 Angstroms or greater. In other implementations, the average width of the different groups of features (e.g., group A and B) may differ in the range of 2 to 10 Angstroms. Width may refer to a lateral width or size in the horizontal direction 326. In implementations, the difference in average width of features may occur within local regions (1-25 mm) or across the entire integrated circuit die, computing device, or wafer. For example, a local subset of the features of an integrated circuit die may have a difference in average width, but other regions may not have features with a difference in average width. In implementations, local or local regions may refer to a physical area (e.g., bounded physical area, such as a row or square) of an integrated circuit die, computing device, or wafer.
In implementations, the features of group A (e.g., features 1336) may interleave with features of group B (e.g., features 1338). For example, some features of group A (e.g., two or more) may be interspersed between two features of group B (not shown), in a repeating or non-repeating pattern. In other implementations, each feature of group A (e.g., features 1336 B-D, odd features) may be disposed between two different features of group B (e.g., features 1338, even features), so that the features of group A alternate with the features of group B. It may be noted that feature 1336A lies at on the end of integrated circuit die 1300 and may not be part of the group A in some implementations. In implementations, features of group A and group B may be a subgroup of features on an integrated circuit. For example, a SOC integrated circuit may have a logic circuit with features (e.g., fins) that is processed using processes 100-1200 described herein, and a memory circuit with features (e.g., fins) that are processed using different processing techniques.
In implementations, processes 100-1200 may be used to form features with tight pitch. Pitch 1324 illustrates example of a tight pitch, in accordance with implementations. In some implementations, the pitch 1324 may be in the range of 8 nm to 30 nm with a tolerance of ±2 nm. Tolerance herein may refer to plus or minus (±) a given value, unless otherwise described.
In implementations, angled passivation may be a process that encapsulates or penetrates a material to protect the underlying material or element from the environment or subsequent processes, for example. In implementations, angled passivation may be performed as a plasma process, such as fluorinating plasma process. For example, a plasma process may use plasmas to form a coating of fluorine-containing groups on the surface (or penetrate below the surface) of a population of spacers (e.g., spacers 220B, 220D, and 220F). The plasma may be deposited using an angular plasma exposure that allows passivation material to be applied to a desired depth in the selected population of spacers. In one implementation, the plasma may be made with Fluorine rich gases such as Carbon Tetrafluoride (CF4), Difluoromethane (CF2H2), or a mixture of both gases. In another implementation, the CF4 or CF2H2 may be mixed with other gases such as CH4, Silane, or other similar gases. It may be noted that other material or processes may be implemented to passivate a population of spacers selective to another population of spacers.
It may be noted that in some implementations some processes may be implemented while others are not implemented. For example in some implementations, subsequent to changing the etch properties associated with a population of spacers (e.g., even spacers) using angled passivation 1422, etch described with respect to
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In implementations, the selective growth layers 1552 may be formed from self-assembled monolayers (SAMs) that are organic molecular assemblies formed on surfaces by absorption and are organized into ordered domains. In implementations, a chemically selective reaction may occur that allows the SAMs to react with the material of the body (e.g., the surface and the exposed odd spacers or backbone structures 116) but not react with passivation layer 1426 of the even spacers. In one implementation, the SAMs may be Silane-based SAMs. In implementations, SAMs that attach preferentially to dielectric surfaces may be assembled in a solution. In another implementation, the SAMs may be deposited using a spin coating process. In an implementation, the SAMs may be applied to the center of the substrate 110 and the substrate 110 may be spun to spread the SAMs by centrifugal force. In yet another implementation, the SAMs may be deposited using a vapor phase deposition process where SAMs in a vapor phase are condensed to form a thin film. Examples of SAMs may include molecules with small or long (C1-C22) Alkyl chains or fluorinated chains and head groups that may include Alkoxysilanes, Aminosilanes and Chlorosilanes. In another implementation, the SAMs may be Thiol-based SAMs and the dielectric material may be a metal or metal oxide. SAMs that attach preferentially to metals or metal oxides may be assembled in the solution, spin coating or vapor phase deposition using molecules with head groups such as Alkenes, Alkynes, Amines, Phosphines, Thiols, Phosphonic acids or Carboxylic acids that selectively combine with metals. In some implementations, the selective growth layer 1552 may react with both metals and dielectric material.
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In still other implementations, the SAMs may form a passivation layer, rendering the surface of the selective growth layer 1552 hydrophobic, blocking the deposition of a subsequent material on the surface of the selective growth layer 1552. Other examples of chemical compounds that may be used as passivants include Octadecylphosphonic acid or Octadecylthiol. With reference to
In implementations, the angled deposition 1622 of the deposition layers 1626 may change the etch properties associated with the underlying spacers (e.g., spacers 220A, 220C, and 220E), and protect the underlying material from being subsequently etched. It may be noted that in implementations, the deposition layers 1626 may not change the etch properties of the affected spacers themselves, but form a protective layer on the associated spacer where the protective layer has different etch properties than the adjacent odd spacer, for example.
In implementations, the deposition layers 1626 may include material such as Titanium, Tantalum, Copper, Rubidium, Cobalt, Nickle, Iron, Silicon, Germanium, Aluminum or nitrides or oxides of the materials. For example, any materials that may be deposited by physical vapor deposition (PVD) may be used as deposition layers 1626. In some implementations, oxides of deposition material may be deposited by reactive sputtering. In implementations, the thickness of the deposition layers 1626 may be determined by the etch selectivity of the odd spacers and the deposition layer 1626.
It may be noted that in some implementations some processes may be implemented while others are not implemented. For example in some implementations, subsequent to changing the etch properties associated with a population of spacers (e.g., even spacers) using angled deposition 1622, etch described with respect to
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In implementations, angled ion implantation 1822 may change the material properties (such as etch properties) of the bulk of spacers 220A, 220C, and 220E. In implementations, angled ion implantation 1822 may increase the etch rate or decrease the etch rate for the affected spacers.
For example, the spacer material A may be SiO2. Argon ions may be implanted into the odd spacers using angled ion implantation 1822. The Argon doped spacers may be removed selective to the undoped SiO2 spacers. In another example, spacer material A may be amorphous Silicon (a-Si). A combination of one or more of Nitrogen gas (N2), Oxygen gas (O2), Carbon, or Methane (CH4) may be used in a high temperature annealing process to form a silicide, nitride, or oxide. The annealing process may be performed on odd spacers or even spacers. In other implementations, the annealing process may be subsequently performed on the spacers on the opposite side of backbone structures 116 to form spacers of an alternate material. Either the odd spacers or even spacers may be removed selective to the other population of spacers. In another example, spacer material A may be Carbon. Silicon ions may be implanted into the odd spacers using angled ion implantation 1822.
It may be noted that in some implementations some processes may be implemented while others are not implemented. For example in some implementations, subsequent to changing the etch properties of a population of spacers (e.g., odd spacers) using angled ion implantation 1822, etch described with respect to
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Method 1900 begins at operation 1905 by forming a hardmask layer above a substrate. At operation 1910, multiple backbone structures 116 are formed above the first hardmask layer 114. At operation 1915, a first multitude of spacers 220 of a first material are formed adjacent to first sides and second sides of the multiple backbone structures 116.
At operation, 1918, the etch properties associated with the first multitude of spacers adjacent the second sides are adjusted. At operation 1920, first spacers (or second spacers) of the first multitude of spacers 220 that are adjacent to the first sides of the multiple backbone structures 116 are etched selective to spacers 220 that are adjacent to second sides of the multiple backbone structures 116. It may be noted that the spacers 220 may be prepared (e.g., etch properties adjusted) and selectively removed in a variety of ways as described with at least to respect to
At operation 1925, a second multitude of spacers 430 of a second material adjacent to the first sides and the second sides of the multiple backbone structures 116 are formed. At operation 1930, third spacers of the second multitude of spacers 430 that are adjacent to the second sides (e.g., 350A, 350C, 350E) of the multiple backbone structures 116 are asymmetrically etched. The multiple backbone structures 116 protect fourth spacers of the second multitude of spacers 430 that are adjacent to the first sides of the multiple backbone structures 116 from being removed. At operation 1935, the multiple backbone structures 116 are selectively removed to leave the second spacers of the first material (e.g., spacers 220A, 220C, and 220E) and the fourth spacers of the second material (e.g., spacers 430B, 430D, and 430F).
Method 1900 continues from operation 1935 of method 1900, and begins at operation 1940 by forming a second hardmask layer 714A above the second spacers of the first material and the fourth spacers of the second material. At operation 1945, a trench 732 in the second hardmask layer 714A is etched to expose a first one of the second spacers (e.g., spacer 220A) and a first one of the fourth spacers (e.g., spacer 430D). At operation 1950, the first one of the second spacers (e.g., spacer 220A) is selectively etched respective the first one of the fourth spacers (e.g., spacer 430D). At operation 1955, another trench 932 in the second hardmask layer 914A is etched to expose a second one of the second spacers (e.g., spacer 220C) and a second one of the fourth spacers (e.g., spacer 430B). At operation 1960, the second one of the fourth spacers (e.g., spacer 430B) is selectively etched respective the second one of the second spacers (e.g., spacer 220C). At operation 1965, the second hardmask layer 914A is removed to expose remaining second spacers and fourth spacers (e.g., spacers 220A, 220C, 430C, and 430F). At operation 1970, features (e.g., features 1236 and 1238) of the integrated circuit are formed by transferring an etch pattern using the remaining second spacers and fourth spacers.
The interposer 2000 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
The interposer may include metal interconnects 2008 and vias 2010, including but not limited to through-silicon vias (TSVs) 2012. The interposer 2000 may further include embedded devices 2014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, or MEMS devices, may also be formed on the interposer 2000. In accordance with one or more implementations, apparatuses or processes disclosed herein may be used in the fabrication of interposer 2000.
Computing device 2100 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 2110 (e.g., DRAM), non-volatile memory 2112 (e.g., ROM or flash memory), a graphics processing unit 2114 (GPU), a digital signal processor 2116, a crypto processor 2142 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 2120, at least one antenna 2122 (in some implementations two or more antenna may be used), a display or a touchscreen display 2124 (e.g., that may include integrated circuit die 2102), a touchscreen controller 2126, a battery 2128 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 2127, a compass (not shown), a motion coprocessor or sensors 2132 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 2134, a camera 2136, user input devices 2138 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 2140 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 2100 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 2100 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 2100 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
The communications logic unit 2108 enables wireless communications for the transfer of data to and from the computing device 2100. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some implementations they might not. The communications logic unit 2108 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 2100 may include a multitude of communications logic units 2108. For instance, a first communications logic unit 2108 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 2108 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 2104 (also referred to “processing device” herein) of the computing device 2100 includes one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure. The term “processor” or “processing device” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processor 2104 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processor 2104 may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor 2104 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like.
The communications logic unit 2108 may also include one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.
In further implementations, another component housed within the computing device 2100 may contain one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.
In various implementations, the computing device 2100 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 2100 may be any other electronic device that processes data.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.
Various operations are described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
The terms “over,” “above” “under,” “between,” “adjacent,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed above or over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to Germanium, Indium Antimonide, Lead Telluride, Indium Arsenide, Indium Phosphide, Gallium Arsenide, Indium Gallium Arsenide, Gallium Antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.
A multitude of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.
Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as Hafnium, Silicon, Oxygen, Titanium, Tantalum, Lanthanum, Aluminum, Zirconium, Barium, Strontium, Yttrium, Lead, Scandium, Niobium, and Zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, Hafnium Oxide, Hafnium Silicon Oxide, Lanthanum Oxide, Lanthanum Aluminum Oxide, Zirconium Oxide, Zirconium Silicon Oxide, Tantalum Oxide, Titanium Oxide, Barium Strontium Titanium Oxide, Barium Titanium Oxide, Strontium Titanium Oxide, Yttrium Oxide, Aluminum Oxide, Lead Scandium Tantalum Oxide, and Lead Zinc Niobate. In some implementations, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, Ruthenium, Palladium, Platinum, Cobalt, Nickel, and conductive metal oxides, e.g., Ruthenium Oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, Hafnium, Zirconium, Titanium, Tantalum, Aluminum, alloys of these metals, and carbides of these metals such as Hafnium Carbide, Zirconium Carbide, Titanium Carbide, Tantalum Carbide, and Aluminum Carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as Silicon Nitride, Silicon Oxide, Silicon Carbide, Silicon Nitride doped with Carbon, and Silicon Oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a multitude of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
In implementations, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions may be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as Boron, Aluminum, Antimony, Phosphorous, or Arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a Silicon alloy such as Silicon Germanium or Silicon Carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as Boron, Arsenic, or Phosphorous. In further implementations, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further implementations, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
In other implementations, one or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, Silicon Dioxide (SiO2), Carbon doped oxide (CDO), Silicon Nitride, organic polymers such as Perfluorocyclobutane or Polytetrafluoroethylene, Fluorosilicate glass (FSG), and organosilicates such as Silsesquioxane, Siloxane, or Organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.
The words “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims may generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term “an implementation” or “one implementation” or “an implementation” or “one implementation” throughout is not intended to mean the same implementation or implementation unless described as such. The terms “first,” “second,” “third,” “fourth,” etc. as used herein are meant as labels to distinguish among different elements and may not necessarily have an ordinal meaning according to their numerical designation.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US17/25509 | 3/31/2017 | WO | 00 |
