Patent Application
20140269007
As Moore's Law has been predicted, the capacity of memory cells on silicon for the past 15-20 years has effectively doubled each year. Moore's Law roughly states that every year the amount of devices such as transistor gates or memory cells on a silicon wafer will double, thus doubling the capacity of the typical chip while the price will essentially stay the same. As the devices continue to shrink, device technology is starting to reach a barrier known as the quantum limit, that is, they are actually approaching atomic dimensions, so the cells cannot get any smaller.
Separately, disk drives have been a type of information storage which provided a significant portion peak capacity. The storage density provided by disk drives have been cheaper than semiconductor memory devices at least partially due to the way disk drives store and read individual bits of information in individual domains (magnetic transition sites) with an external probe. This method of storing and reading the information does not require individual circuit connections for each bit of storage location, thus requiring significantly less overhead than storage in semiconductor memory which does require the individual circuit connections. The individually connected semiconductor memory such as Flash memory, however, is preferable to disk drives in terms of resistance to shock as it has no moving parts which may be damaged by movement and shock.
As semiconductor device scaling passes 45 nanometer feature size, or node to 25 and 15 nanometer nodes, the semiconductor memory density are beginning to reach similar density and cost as disk drive storage. Multiple bit storage per device, where a multiple of data bits may be stored in a single cell by a division of ranges, has also been employed to increase density and reduce cost.
Semiconductor memories such as flash memory of the floating gate or charge trapping types suffer from other issues due to scaling. As the size of the devices become smaller, variations of a few electrons begin to manifest as large variations in device characteristics such as current, write speed, and erase speed. Such large variations further require increased write, read, and erase time to reach the same distribution ranges for operation and reduce the supportable dynamic ranges for multiple bit storage.
Yet one more concern for traditional flash type of semiconductor memory scaling is the reduction of the number of write/erase cycle the cell will tolerate before it permanently fails. Prior to the substantial reduction in cell size, the typical flash memory write/erase cycle tolerance rating is in the range of 1,000,000, however, as the feature size reduces in size, write/erase cycle tolerance rating has diminished to the range of 3,000 cycles. This reduction of write/erase cycle tolerance limits the applications for the memory. For example, for a memory device to also function in current SRAM and DRAM applications, such memory must tolerate data exchange at much higher repetition rates, typically several times per microsecond, resulting in 1,000,000 or more cycles.
Accordingly, what is desired are a memory device, system and method which overcome the above-identified problems. The memory device, system and method should be easily implemented, cost effective and adaptable to existing storage applications. The system and method should also be simple to integrate with other ICs in terms of processing and operating voltages. The present disclosure addresses such a need.
The present disclosure relates generally to memory devices and more particularly to memory devices that includes heterojunction metal oxide material and have asymmetric hysteresis property.
Some embodiments of the present invention disclose a memory device. The memory device comprises a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device may also includes a barrier layer coupled to the first metal oxide layer, a second metal oxide layer coupled to the barrier layer, and a second metal layer coupled to the second metal oxide layer. The memory device has a property of asymmetric hysteresis upon application electrical bias of opposite polarities.
The following detailed description, together with the accompanying drawings will provide a better understanding of the nature and advantages of the present invention.
The present disclosure relates generally to memory devices, and more particularly to a memory device that includes a heterojunction which has a property of asymmetric hysteresis behavior described herein. The following description is provided to enable one of ordinary skill in the art to make and use the disclosed memory device. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
The present disclosure is directed to a memory device, methods of forming the device, and systems comprising the device. The memory device can be utilized in a variety of applications from a free standing nonvolatile memory to an embedded device in a variety of applications. These applications include but are not limited to embedded memory used in a wide range of SOC (system on chip) or system on package, switches in programmable or configurable ASIC, solid state drive used in computers and servers, memory used in mobile electronics like camera, cell phone, electronic pad, and build in memory in micro devices such as RF chips, mobile sensors and many others.
The memory device comprises a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device may include an optional barrier layer coupled to the first metal oxide layer. The memory device includes a second metal oxide layer coupled to the optional barrier layer or the first metal oxide layer. The memory device also includes a second metal layer coupled to the second metal oxide layer. These metal layers, optional barrier layers, and metal oxide layers can be of a variety of types and their use will be within the spirit and scope of the present disclosure.
More particularly, many of the embodiments disclosed herein will include PCMO as one of the metal oxide layers. It is well understood by one of ordinary skill in the art that the present disclosure should not be limited to this metal oxide layer, metal nitride layer, metal oxynitride layer or any other specific layer disclosed herein.
In many embodiments, the formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer and there is a barrier layer of wider band gap material or higher oxygen diffusion constant than the first metal oxide, the second metal oxide, or both. The difference in the band gap or oxygen diffusion constant will form a barrier to impede oxygen ions or vacancies from moving between the first metal oxide and the second metal oxide.
This barrier can serve to improve the retention of a resistance memory state of the device even after the electric field is removed. The resistance memory state is typically formed by an externally applied electric field which drives the oxygen ions or vacancies from either the first metal oxide or the second metal oxide into the other metal oxide layer.
In some embodiments, the first metal oxide layer is described as a metal oxide layer comprising oxygen ions or vacancies. The first metal oxide layer may comprise one or more metal nitride layer or metal oxynitride layer comprising nitrogen and/or oxygen ions or vacancies. Similarly, although the second metal oxide layer is described as a metal oxide layer it also may comprise one or more metal nitride layer or a metal oxynitride layer in some embodiments.
Referring now to
In the case where the metal oxide is stoichiometric, the metal oxide typically behaves as an insulator and will not conduct electron. When the metal oxide is very thin, on the order of a few to a few 10ths of Angstroms, direct tunneling and FN tunneling may occur.
If an oxygen deficient (sub-stoichiometric) metal oxide is present in the device as shown in the center device, the oxygen deficient oxide may contain vacancies that may form defect states in the middle of the band gap. When the mean distance of the oxygen vacancy is within the range of electron path length of the metal oxide, an oxygen vacancy based conduction path can be established by percolation which may allow electron conduction.
For the situation where an oxygen rich (super-stoichiometric) metal oxide is present, the excess oxygen ions can form defect states in the middle of the band gap as well. When the mean distance of the oxygen ion is within a percolation path distance threshold, an oxygen ion based conduction path can be established and allow electron conduction through the metal oxide layer.
Referring now to
When a negative bias is applied to the top electrode, the oxygen vacancies can be pulled toward the top electrode. This vacancy movement can establish or reestablish the conduction patch. It is noted that the bias field applied to the top electrode driving the vacancy movement will stop driving the vacancy movement once electron conduction begins. Thus, the process is self limiting as long as the applied bias does not exceed a breakdown voltage beyond which irreparable damage to the oxide bonds occur. This is also known as the break down limit. Finally, the hysteresis illustration at the right hand side of
Referring now to
When a positive bias is applied to the top electrode, the oxygen ions can be pulled toward the top electrode. This ionic movement can establish or reestablish the conduction patch. It is noted that the bias field applied to the top electrode driving the ionic movement will stop driving the ionic movement once electron conduction begins. Thus, the process is self limiting as long as the applied bias does not exceed a breakdown voltage beyond which irreparable damage to the oxide bonds occur. This is also known as the break down limit. Finally, the hysteresis illustration at the right hand side of
Referring now to
A low resistance state is shown where a first top resistance (RT1) of the top metal oxide is similar in magnitude as a first base resistance (RB1) of the base metal oxide. This low resistance state can also be known as the “1” state of the memory device. At the low resistance state, the top metal oxide is shown comprising oxygen vacancy and the base metal oxide is shown comprising oxygen ions.
A positive bias can be applied to the top electrode in a reset operation which may cause recombination of the oxygen vacancy from the top metal oxide and the oxygen ions from the base metal oxide to recombine at the heterojunction result in a depletion of oxygen vacancies in the top metal oxide as previously shown in
A negative bias can be applied to the top electrode in a set operation which may cause the regeneration of the oxygen vacancies at the heterojunction to populate the top metal oxide and return the memory device to a low resistance state as is also shown in the middle illustration of
Referring now to
A low resistance state is shown where a first top resistance (RT1) of the top metal oxide is similar in magnitude as a first base resistance (RB1) of the base metal oxide. This low resistance state can also be known as the “1” state of the memory device. At the low resistance state, the top metal oxide is shown comprising oxygen ions and the base metal oxide is shown comprising oxygen vacancies.
A negative bias can be applied to the top electrode in a reset operation which may cause recombination of the oxygen ions from the top metal oxide and the oxygen vacancies from the base metal oxide to recombine at the heterojunction result in a depletion of oxygen ions in the top metal oxide as previously shown in
A positive bias can be applied to the top electrode in a set operation which may cause the regeneration of the oxygen ions at the heterojunction to populate the top metal oxide and return the memory device to a low resistance state as is previous shown by the middle illustration of
The top electrode 12 can be any metal, such as Platinum (Pt), Aluminum (Al), Ruthenium (Ru), Copper (Cu), Gold (Au), Tungsten (W), Titanium (Ti), Hafnium (Hf), Tantalum (Ta), Iridium (Ir), Zinc (Zn), Tin (Sn), Rhodium (Rh) and other metals. The bottom electrode 16 may be Platinum (Pt), Aluminum (Al), Ruthenium (Ru), Copper (Cu), Gold (Au) or any other metal or conductive substrate.
The base metal oxide layer 14 can be one or more of Praseodymium Calcium Manganese Oxide (PCMO), Lanthanum Calcium Manganese Oxide (LCMO), Lanthanum Strontium Nickel Oxide (LSNO), Nickel Oxide (NixOy), Hafnium oxide (HfxOy), Aluminum oxide (AlxOy), Tantalum oxide (TaxOy) or any other metal oxide, metal nitride or metal oxynitride. The base metal oxide layer 14 may be a combination of more than one materials, phases or configurations of metal oxide. For example, the base metal oxide layer 14, itself, may be a layered material of one or more materials, phases, or configurations of metal oxides, metal nitride or metal oxynitride.
In some embodiments, the base metal oxide layer 14 can be a multi-layered structured that includes more than one material, phases or configurations of metal oxide. For example, base metal oxide layer 14 may be multi-layered comprising an amorphous layer of LCMO with a crystalline layer of LCMO. Other examples of multi-layered metal oxide layer 14 include a layer of PCMO with a layer of LCMO formed over the PCMO layer, or a layer of Aluminum oxide with a layer of Hafnium oxide formed over the Aluminum oxide layer and a layer of Tantalum oxide formed over the Hafnium oxide layer.
The base metal oxide layer 14 may be coupled to an optional barrier layer 20. The barrier layer 20 may include one or more wide band gap (or insulating) and oxygen ion or vacancy diffusion barrier materials such as Aluminum oxide (AlxOy), Hafnium oxide (HfxOy), Nickel oxide (NixOy), Tantalum oxide (TaxOy) or any other wide band gap material that has wider band gap than tone or both of the metal oxide layers and can serve as oxygen ion or vacancy diffusion barrier. In some embodiments, barrier layer 20 may itself be a layered material of one or more materials, phases, or configurations exhibiting a characteristic of wide band gap compared to the metal oxide layer 14. In other embodiments, barrier layer 20 may be of other low oxygen ion or vacancy diffusion barrier materials other than a metal oxide.
A top electrode layer 12 is coupled to base metal oxide layer 14 or the optional barrier layer 20. The top electrode 12 may be formed from a metal such as Platinum (Pt), Aluminum (Al), Ruthenium (Ru), Copper (Cu), Gold (Au), Tantalum (Ta), Titanium (Ti), Tungsten (W) or other.
In some embodiments, top metal oxide layer 18 may form as a result of heating. In other embodiments, top metal oxide 18 may be deposited rather than formed at the interface of barrier layer 20 and top electrode 12. The deposited top metal oxide layer may have a Gibbs free energy of oxidation more or less than a Gibbs free energy of oxidation for metal oxide layer 14. Also, the deposited top metal oxide layer may have a Gibbs free energy of oxidation more or less than a Gibbs free energy of oxidation for barrier layer 20.
In some embodiments, the base metal oxide layer 14 is thicker than top metal oxide layer 18. In an embodiment, the base metal oxide layer 14 is 10 to 100 times thicker than top metal oxide layer 18. For example, the thickness of top metal oxide layer 18 may be in the range of 10 to 100 angstroms and the thickness of metal oxide layer 14 may be between 100 to 10000 angstroms.
The barrier layer 20 is preferably thin and may be between 5 to 50 angstroms to allow for direct diffusion, passing, or tunneling of oxygen ions or vacancies from metal oxide layer 14 to top electrode metal 12. This direct diffusion/passing/tunneling of oxygen ions or vacancies may be spontaneous or may occur in response to an externally applied electrical or chemical potential. In a particular embodiment, barrier layer 20 is between 20 and 30 angstroms thick. Barrier layer 20 serves to slow down or stop the diffusion of oxygen ions or vacancies between metal oxide layer 14 and top electrode metal 12 or tope metal oxide layer 18, especially when externally applied potential is removed. Thus, barrier layer 20 may improve data retention of the memory device.
The different hysteresis loops shown in
In a particular embodiment, the switch from LRS to HRS is used to ‘reset’ the memory device and the transition from HRS to LRS is used to ‘set’ the memory device. In some embodiments, the lower oxidation Gibbs free energy of the top electrode in a vacancy type device may result in a more stable top oxide layer structure which has a higher resistance in HRS than the resistance of PCMO in HRS. For example, the top metal oxide layer may be significantly thinner than PCMO and the resistance of the top metal oxide layer at LRS may be comparable to or lower than the resistance of PCMO at HRS. This feature may be utilized in the following way.
When a vacancy type device containing a top metal oxide layer is in the HRS; most of the voltage applied to the vacancy type device will drop across the top metal oxide and hence create a high internal field that causes the switching from the HRS to the LRS (‘set’). Many mechanisms for this switching are possible. For example, the internal field may push oxygen ions or vacancies through and out of the top metal oxide layer into the PCMO layer (i.e. base or bottom metal oxide layer), thus reducing the top metal oxide layer thickness. This movement of the oxygen ion or vacancy may be optionally through barrier layer 20.
On the other hand, when the vacancy type device is in the LRS, the voltage applied to the vacancy type device will be shared in the top metal oxide layer and in the PCMO layer or can be more in the PCMO layer. This allows field induced oxygen ion or vacancy migrations through and out of the PCMO layer into the top metal oxide layer and the top metal electrode layer. The influx of oxygen ions into the top metal oxide layer may cause further oxidation of the top metal electrode layer at the interface with the top metal oxide layer and may thus increase the thickness of the top metal oxide layer and cause the resistance of the device to switch from the LRS to the HRS (‘reset’). Again, this movement of the oxygen ion or vacancy out of the PCMO layer may optionally pass through barrier layer 20.
The relative layer thickness of the top metal oxide and the PCMO layers may be adjusted to secure desired levels of switching speed, switching potential, or both. These thickness adjustments may be produced by deposition condition changes and/or by depositing an initial top metal oxide layer before the deposition or the formation of top metal oxide layer 18.
Referring now specifically to the right half of
After the first IV curve 620 is measured, the electrical bias can be ramped from 4V to 0V and measure a second IV curve 630. The second IV curve 630 is shown with the square symbols in the right half of the graph. Since the first IV curve 620 and the second IV curve 630 do not overlap they combine into a hysteresis loop. The current readings in the second IV curve 630 are the sensing or read currents for the HRS reset state in the positive bias direction.
The memory can be read or sensed at a positive voltage less than the reset voltage. For example, a possible reading or sensing voltage of 1V is shown by a vertical line on the graph. At 1V bias, this device has a read current for the LRS shown by the intersection of the first IV curve 620 and the vertical line at 1V to be ˜10−8 Amp. The read current for the HRS is shown by the intersection of the second IV curve then the “set” state as 630 and the vertical line at 1V to be ˜2×10−1° Amp.
Referring now to the remaining left half of
This third IV curve 640 also represents the current to voltage relationship of the device as it is switched from a “reset” or high resistance state (HRS) to a “set” or low resistance state (LRS). The maximum applied negative voltage, in this case −4V, is the set voltage and the current readings in the third IV curve 640 are the sensing or read currents for the HRS set state in the negative bias direction.
After the third IV curve 640 is measured, the electrical bias can be ramped from −4V to 0V to measure a fourth IV curve 650. The fourth IV curve 650 is shown with the square symbols in the right half of the graph. The current readings in the fourth IV curve 650 are the sensing or read currents for the LRS reset state in the positive bias direction.
Since the third IV curve 640 and the fourth IV curve 640 do not overlap they combine into a hysteresis loop. This hysteresis loop is different than the hysteresis loop formed by the first IV curve 620 and the second IV curve 630, thus the two hysteresis loops together form an asymmetric hysteresis loop or system.
The memory can be read or sensed at a negative voltage less than the set voltage. For example, a possible reading or sensing voltage of −1V is shown by a vertical line on the graph. At 1V bias, this device has a read current for the HRS shown by the intersection of the third IV curve 640 and the vertical line at −1V to be ˜10−10 Amp. The read current for the LRS is shown by the intersection of the fourth IV curve 650 and the vertical line at −1V to be ˜4×10−8 Amp.
Since the third IV curve 640 and the fourth IV curve 640 do not overlap they combine into a hysteresis loop. This hysteresis loop is different than the hysteresis loop formed by the first IV curve 620 and the second IV curve 630, thus the two hysteresis loops together form an asymmetric hysteresis loop or system.
The positive hysteresis loop and the negative hysteresis loop are asymmetric in size, shape and maximum current delivered. The asymmetry stems from heterojunction formed by the two metal oxide layers at their interface. The asymmetry of the hysteresis loops can be tuned for the desired resistance to voltage characteristics desired for the application. For example, the current level for one bias direction can be made switchable while holding the reversed bias current essentially un-switchable by compressing the hysteresis loop in one bias direction to remove the window. The tuning can be done by changing oxygen content of the top metal oxide and the base metal oxide as well as the Gibbs free energy difference between the two layers. For example, increasing the oxygen deficiency of the top metal oxide higher increases dominance of interface resistance to the bulk resistance.
The asymmetry of the hysteresis loop between the positive and negative bias can be a powerful tool in the operation of the memory device and be used in many ways. For example, since the read currents are different between negative bias read and positive bias read, the read bias can be store separately and be used as a key to unlock the data stored in a memory for a security application. The read bias bit map can be store physically or electronically separately.
As another example, the asymmetric hysteresis can be used as a back-up or repair mode for marginal memory devices. If the primary read bias does not produce good LRS to HRS current window, the other bias can be utilized. This repair mode can be implemented at a bit level, page level, sector level, or chip level.
In some embodiments of the memory device, a barrier layer may be introduced between the base metal oxide layer and the top metal oxide layer.
Although
The deterioration of the separate resistance states HRS and LRS, such as by diffusion of oxygen ions, can result in difficulty in distinguishing the two states. When the vacancy type devices are used, for example, as memory devices, such deterioration erodes the ability to distinguish between the two resistance states and consequently deteriorates data retention capability of the memory device. Therefore a solution to this problem would be advantageous, e.g., in the utility of the vacancy type devices of the present disclosure as memory devices.
Barrier layer 20 described above can serve as a solution to the aforementioned problem of data retention. A barrier layer of wide band gap or an oxygen ion diffusion barrier material may serve to impede the drift and diffusion of the oxygen ions into or out of the top metal oxide layer thus improving the stability of the individual RHS and LHS states. This improvement can thus result in improvement in data retention of digital data written into arrays of the vacancy type devices of the present disclosure as distinct RHS and LHS states.
The barrier layer can further serve as a means for adjusting vacancy type devices in order to secure desired levels of switching speed, switching potential, or both. This adjustment may be useful in, for example, preventing early switching from occurring during voltage ramp up. For example, for the oxygen ions to diffuse through the barrier layer, a minimum voltage may be needed, thus preventing early switching of resistance states during switching. This may improve resistance switching uniformity. Barrier layer 20 may thus improve the uniformity of an array of many devices to achieve a narrow switching distribution. Such narrower switching distribution may result in better overall performance of the memory system. In some embodiments, it would be easier to distinguish between the LRS and the HRS bits in the array, thus requiring less overhead such as error correction and allow for faster response time.
Further such improved control as provided by the narrower switching distribution can be used to allow for multiple digital data bits to be stored in a single device by allowing for multiple resistance stages to be distinguished in every cell in an array. For example, if the LRS allows for 1 micro amp (μA) of current to pass through the device at 1 Volt (V) of bias, and the HRS allows for 0.1 μA of current to pass through the device at 1 V of bias, then the window would be 1-0.1=0.9 μA. Then, if groups of devices, e.g., a sector of 1000 memory devices, were to be “read” and compared to a reference cell which allows 1 μA of current at 1 V of bias to determine the cells at LRS, the distribution of the currents for the 1000 memory devices influences whether it is easy to determine whether each device is in the LRS or the HRS. If the LRS currents are centered around 1 μA with an distribution of +/−0.5 μA (i.e. 0.5 μA to 1.5 μA) and the HRS currents are centered around 0.1 μA with a distribution of +/−0.5 μA (i.e., −0.4 μA to 0.6 μA), then the two distributions would overlap and there will be some devices for which it would be difficult to discern whether they are in the LRS or the HRS.
However, if the LRS currents are centered around 1 μA with a distribution of +/−0.1 μA (i.e. 0.9 μA to 1.1 μA) and the HRS currents are centered around 0.1 μA with a distribution of +/−0.1 μA (i.e. 0 μA to 0.3 μA), then the two distributions would be easily distinguishable and no devices would be in an ambiguous state. Further, additional states between the LRS and the HRS may be distinguishable. For example a middle resistance state (MRS) may be centered on 0.5 μA with a +/−0.1 μA distribution (i.e. 0.4 μA to 0.6 μA), and still be distinguishable from LRS and HRS devices as the distributions do not overlap. If 4 distinguishable states can be supported, then two bits of memory can be stored in a single device.
An embodiment of the present invention that includes a barrier layer provides a heterojunction memory device which can potentially retain data over a long period of time (e.g., 10+ years). The heterojunction memory device may be implemented in a variety of memory functions such as dynamic random access memory (DRAM), static random access memory (SRAM), one-time programmed memory (OTP), nonvolatile memory (NVM), embedded memory, cache memory, and others.
Thereafter, a barrier layer 706 is formed over first metal oxide layer 704 as illustrated in
It should be appreciated that the specific steps illustrated in
For example,
The table 406 in
The nondestructive read can only differentiate the 00 state (LRS) from either the 01 or 10 state (HRS state). To further differentiate 01 vs. 10 state, the polarity of the switching voltage (Vb−<V<Va− or Va+<V<Vb+) needs to be tested that cause the switching of HRS resistor to LRS. Since this is a destructive read, an additional pulse is needed to reset the device to the initial state before the destructive read.
The addressable and readable tri-state of a back-to-back switching resistor device can be used to create a memory array that avoid the need of an active transistor circuit to perform the select and set/reset and read. For example, since 01 and 10 states are two addressable and distinguishable HRS, they can be assigned to be the 0 or 1 state of a memory cell. Since both 0 and 1 state have high resistance, the system should have very low leakage current. A positive or negative voltage greater than Vb+ or smaller than Vb− can set the device to 1 or reset the device to 0 state as shown in the table for
In order to address a particular memory cell, proper voltage on the read and write line are required so that the states of other cells in the memory array are not affected.
The above discussions are base on two identical heterojunction oxide resistors. If the HRS states of the two switching resistors 702 and 704 have sizable differences as illustrated in
Although the present disclosure has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present disclosure. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
This application is the non-provisional application of and claims the benefit under 35 USC §119(e) to U.S. Provisional Patent Application No. 61/786,601 filed on Mar. 15, 2013. This application is related to U.S. patent application Ser. No. 13/396,404 filed Feb. 14, 2012, which claims priority under 35 U.S.C. §371 to PCT Application No. PCT/US2010/045667, filed on Aug. 16, 2010, which in turn claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application No. 61/234,183, filed on Aug. 14, 2009. This application is also related to U.S. Provisional Application No. 61/666,933 filed on Jul. 2, 2012. The disclosures of the above mentioned applications are all incorporated by reference herein in their entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 61786601 | Mar 2013 | US |
